Voltage Biasing Considerations (From the CS atom toward the differential pair atom) Claudio Talarico, Gonzaga University

Transcription

1 Voltage Biasing Considerations (From the CS atom toward the differential pair atom) Claudio Talarico, Gonzaga University

2 Voltage Biasing Considerations In addition to bias currents, building a complete analog circuit requires the generation of various bias voltages The CS stage is very sensitive to variations in its input bias voltage In the majority of practical cases CS circuits are embedded in feedback networks that regulate the input bias voltage to the proper value, therefore absorbing process variations and mismatch effects (CMFB) This complication typically does not exist for CG stages and CD stages EE 303 Voltage Biasing Considerations 2

3 Assumptions so far So far we have implicitly assumed We have nearly ideal current and voltage sources available to set up the transistors bias points Transistor parameters and supply voltage do not vary As we move toward the practical implementation of transistor stages we we must Focus on biasing schemes that are insensitive to variations commonly seen in IC technology EE 303 Voltage Biasing Considerations 3

4 Overview Process, Voltage and Temperature Variations, Device mismatch V DD V DD V DD Supply Independent Bias Circuits Supply Independent Bias Circuit I ref»» V BIAS1 Biasing Considerations Current Mirrors V BIAS2 source: R. Dutton, B. Murmann EE 303 Voltage Biasing Considerations 4

5 Variations Process-Voltage-Temperature (PVT) variations global variations à they affect the devices on a chip uniformly Device mismatches Local variations à Typically follows Gaussian distribution Process Corners: slow, nominal fast PVT corners - slow-slow - nom-nom - fast-fast nominal = P, V, T slow = P slow, V, T fast = P fast, V, T NMOS PMOS µ T 3/2 T µ [ more temperature = more collisions = less mobility ] I V 2 V I [ more voltage = more current = less time to charge/discharge caps. ] EE 303 Voltage Biasing Considerations 5

6 PVT Variations PROCESS Variations between production lots "Slow, Nominal and Fast" corners VOLTAGE V DD is usually specified only within ±10% E.g. V DD = V TEMPERATURE Ambient temperature variations 0 70 C (or C) source: R. Dutton, B. Murmann EE 303 Voltage Biasing Considerations 6

7 Process Variations Wafer made yesterday All NMOS are slow All PMOS are nominal All R are nominal All C are fast Wafer made today All NMOS are fast All PMOS are fast All R are nominal All C are slow Parameter Slow Nominal Fast V T 0.65V 0.5V 0.35V µc ox (NMOS) 40 µa/v 2 50 µa/v 2 60 µa/v 2 µc ox (PMOS) 20 µa/v 2 25 µa/v 2 30 µa/v 2 R poly2 60Ω/ 50Ω/ 40Ω/ R nwell 1.4 kω/ 1 kω/ 0.6 kω/ C poly-poly ff/µm 2 1 ff/µm ff/µm 2 source: R. Dutton, B. Murmann EE 303 Voltage Biasing Considerations 7

8 Temperature Coefficients Mostly due to the dependence on T of the surface potential Φ S Parameter V T Approximate TC -1.2 mv/ C µc ox (NMOS) %/ C Mostly due to the dependence on T of mobility µc ox (PMOS) %/ C R poly %/ C R nwell C poly-poly2 +1 %/ C -30 ppm/ C Temperature expands and contracts dielectric thickness T t C * The default temperature in Spice is 25 degrees Celsius * The following command sets the temperature to 100 degrees Celsius.temp 100 EE 303 Voltage Biasing Considerations 8

9 Aside: V T dependence on temperature V T = V T 0 + ΔV T = V T 0 + γ ( Φ s V BS Φ ) s Source: Muller and Kamins Both V T0 and ΔV T depends on Φ S V T 0 Φ S The higher the doping N bulk the more voltage is required to produce an inversion layer: N bulk goes up à V T goes up If C ox = ε ox /t ox is higher (= t ox thinner) the less voltage is required to produce an inversion layer (Q=CV): C ox goes up à V T goes down The dependence on temperature of n i is stronger than the linear dependence in the thermal voltage term (KT/q) As a result: for T V T EE 303 Voltage Biasing Considerations 9

10 CS stage revisited Voltage Biasing for a CS stage V B Transducer R v i i I B R V o Example: V B = 2.5V V I = 1.394V I B = 500µA W/L = 20µm/1µm R = 5kΩ R i = 50kΩ V I Nominal conditions: KP=50µA/V 2, VT0= 0.5V, TEMP=25 C Fast conditions: KP=60µA/V 2, VT0= 0.35V, TEMP= 20 C source: R. Dutton, B. Murmann EE 303 Voltage Biasing Considerations 10

11 HSPICE.OP output ***.op output (nominal) element 0:mn1 region Saturati id u vgs vds vth m vod m beta m gm m gds u... ***.op output (fast, -20degC) element 0:mn1 region Linear id u vgs vds m vth m vod m beta m gm m gds u... source: R. Dutton, B. Murmann EE 303 Voltage Biasing Considerations 11

12 The Problem with This Circuit Process and temperature variations cause large changes in V T and mobility (µ) But V I is kept constant, causing large changes in I D, forcing the device into the triode region First cut idea Use another MOSFET to compute V I such that I D stays roughly constant and tracks process and temperature Note that the same trick is used in a current mirror source: R. Dutton, B. Murmann EE 303 Voltage Biasing Considerations 12

13 First Cut Solution M2 I B I B V B R V v i I R i M1 V o What we expect to see in simulation V I (=V GS1 =V GS2 ) changes with process and temperature But I D1 and V O stay roughly constant source: R. Dutton, B. Murmann EE 303 Voltage Biasing Considerations 13

14 HSPICE.OP Output ***.op output (nominal) element 0:m1 0:m2 region Saturati Saturati id u u vgs vds vth m m beta m m gm m m gds u u... ***.op output (fast, -20degC) element 0:m1 0:m2 region Saturati Saturati id u u vgs vds vth m m beta m m gm m m gds u u... EE 303 Voltage Biasing Considerations 14

15 Remaining Issue with first cut solution What if we do not have access to the node of the input transducer? Consider e.g. a sensor or another amplifier that produces a ground referenced signal with arbitrary quiescent voltage Sensor 5V I B V B 2.5V 2.5V source: R. Dutton, B. Murmann EE 303 Voltage Biasing Considerations 15

16 Second Attempt: Replica Biasing with AC Coupling M2 I B I B V B R R large M1 V o Issues Don t like R large, C large in integrated circuits R i and R large (+1/gm2) form a resistive divider Problematic if R i is large 1/g m2 C large We need R large to avoid the signal to be shorted by 1/g m2 R i v i V I The signal comes from a sensor and it has some superimposed DC V I - C large keeps the DC V I from reaching the gate of M1 - it also makes possible to do not waste DC power on R i EE 303 Voltage Biasing Considerations 16

17 Another Idea: Third Attempt Draw I B out of M 1 source Quiescent point voltage at node X changes over process, temperature, but M 1 current stays roughly constant (thanks to the M 3 - M 2 mirror) The DC voltage at the node G1 can move around without causing an issue as long as the moving around of V G1 is absorbed by V X (=V DS2 ) Make C large large enough to essentially provide a short to ground at minimum desired input frequency v i R i I B V DD I B M1 V B R X V o Issue: Don t like C large (but without we would kill the gain: A V ~ g m1 R/(1+g m1 r o2 ) V I M3 M2 C large EE 303 Voltage Biasing Considerations 17

18 Yet Another Idea (A really good one): Forth Attempt Instead of AC shorting node X with a cap. why not use another MOSFET (M1*) to provide low impedance at node X. As before, circuit is insensitive to changes in V I and transistor V T No large caps or resistors needed to accomplish this! v i R i I B I B V DD M1 V B R X V o M1* M1' The price is we lost 0.5g m (Not too bad given the alternative: a circuit that doesn t work! ) ac equivalent v i R i A V g m1 2 R R M1 v o V I M3 1/g m1' recycle V I to bias the gate of M1* Current source to keep the DC current through M1* roughly constant M 1 =M 1 * g m1 =g m1 +g mb1 EE 303 Voltage Biasing Considerations 18

19 Comments on the Improved CS Solution The structure we arrived to improve the CS is so good that it has its own name: Differential Pair The Differential Pair main feature is to evaluate the difference between two voltages In our improved CS the two voltages are V I and V I +v i To first order changes in V I and process and temperature do not affect the output voltage EE 303 Voltage Biasing Considerations 19

20 Differential Pair vs. Improved CS stage Differential Pair I d1 I d2 V ip I TAIL V im Improved CS M1* Differences: We do not necessarily need the second bottom transistor I M1 =I M1* =I TAIL /2 We usually put signal both at the gate of M1 and at the gate of M1* M TAIL EE 303 Voltage Biasing Considerations 20

21 Voltage Biasing for a CG stage (1) Compared to a CS stage, setting up the bias voltage for the gate of a CG stage is usually less intricate Example 1 Cascode Stage Source: B. Murmann Textbook p. 137 m = 5 à V DS1 = 1.45 V OV EE 303 Voltage Biasing Considerations 21

22 Voltage Biasing for a CG stage (2) Example 2 CG stage interfacing a Photodiode Source: B. Murmann Textbook p. 137 In this circuit the output swing is usually not very large, and thus the bias voltage V G2 is not tightly constrained by voltage swing requirements. Typically, V G2 is set such that the photodiode is biased at a suitable reverse bias. This is accomplished by sizing R 1 and R 2 properly. R 1 and R 2 are AC shorted (G 2 is at AC ground) EE 303 Voltage Biasing Considerations 22

23 Voltage Biasing for a CD stage (1) In a CD stage the input and output voltage bias are directly coupled Proper voltage biasing in a CD stage boils down to making sure that the input and output bias voltages are compatible with the circuits that are connecting to. V DD Source: B. Murmann Textbook p. 138 V IN v IN V GS = V Tn + V ov v OUT V OUT I B EE 303 Voltage Biasing Considerations 23

24 Voltage Biasing for a CD stage (2) In some application, the shift between the input and output bias is undesired. In this case a p-mos CD stage can be used to provide a shift in the opposite direction M 1 can be sized such that the bias voltages V IN and V OUT are approximately the same Source: B. Murmann Textbook p. 139 V Tp +V ov1 V DD I B1 M 2 When a CD is employed primarily to shift bias points the circuit is called a level shifter. Level shifters are generally useful to interface two stages that are otherwise incompatible in terms of their bias input/output voltages. v IN V IN M 1 V Tn +V ov2 v OUT V OUT I B2 EE 303 Voltage Biasing Considerations 24

25 The Challenge for Circuit Designers Making sure that the circuit is biased properly across all possible conditions And also maintain a set of performance specs (gain, bandwidth, power dissipation, ) in presence of parameter variations [source Razavi, p. 599] EE 303 Voltage Biasing Considerations 25

26 Mismatch Upon closer inspection, device parameters not only vary from lot-to-lot or wafer-to-wafer, but there are also differences between closely spaced, nominally identical devices on the same chip (local variations) These differences are called mismatch M 1 M 2 V T 1 V T 2 = ΔV T µc ox W L 1 W µc ox L 2 = Δβ C 1 C 2 C 1 C 2 = ΔC source: R. Dutton, B. Murmann EE 303 Voltage Biasing Considerations 26

27 Statistical Model Experiments over the past decades have shown that mismatches in device parameters (ΔV T, ΔC, ) are typically random and welldescribed by a Gaussian distribution With zero mean and a standard deviation that depends on the process and the size of the device Empirically, the standard deviation of the mismatch between two closely spaced devices can be modeled using the following expression σ ΔX = A X WL where WL represents the area of the device, and X is the device parameter under consideration source: R. Dutton, B. Murmann EE 303 Voltage Biasing Considerations 27

28 Example of Coefficients for 1 µm Technology Parameter A Vt A Δβ/β A ΔC/C (Poly-Poly2 capacitor) Value 20 mv-µm 2 %-µm 2.5 %-µm A ΔR/R (Poly2 resistor) 10 %-µm source: R. Dutton, B. Murmann EE 303 Voltage Biasing Considerations 28

29 Example Example: MOSFET with W= 20µm, L=1µm σ Δ 20mV 2% V = = 4. 5mV σ = = 0. 45% t Δβ β 3σ 3σ Δ V t Δβ β = 13. 5mV = 1. 35% source: R. Dutton, B. Murmann EE 303 Voltage Biasing Considerations 29