Course Outline. 4. Chapter 5: MOS Field Effect Transistors (MOSFET) 5. Chapter 6: Bipolar Junction Transistors (BJT)

Transcription

1 Course Outline 1. Chapter 1: Signals and Amplifiers 1 2. Chapter 3: Semiconductors 3. Chapter 4: Diodes 4. Chapter 5: MOS Field Effect Transistors (MOSFET) 5. Chapter 6: Bipolar Junction Transistors (BJT) 6. Chapter 2 (optional): Operational Amplifiers

2 2 Chapter 5: MOSFETs Part II

3 NMOS at DC 3 Example 5.3 (modified): NMOS Transistor Design the circuit of Figure 5.21, that is, determine the alues of R D and R S I D = 1mA and V D = +0.5V V tn = 0.4V, m n C ox = 100mA/V 2 L = 1mm, and W = 32mm Neglect the channel-length modulation effect (i. e. assume that l = 0).

4 NMOS at DC Exercises D5.9 Determine the alue of R such that V D = 0.8V V tn = 0.5V, m n C ox = 0.4 ma/v 2 W=0.72 mm, and L = 0.18 mm 4 Exercises D5.10 Combine the circuit in D5.9 with transistor Q 2 and find R 2 such that Q 2 is at the edge of saturation.

5 Example 5.8: CMOS Transistors (Inerter) NMOS and PMOS transistors in the circuit of Figure 5.26(a) are matched, with k n(w n /L n ) = k p(w p /L p ) = 1mA/V 2 and V tn = -V tp = 1V. Assume l = 0 for both deices. 5 Find the drain currents i DN and i DP for I = 0V, +2.5V, -2.5V. Find oltage O for I = 0V, +2.5V, -2.5V.

6 Obtaining a Voltage Amplifier In section 1.5, we learned that oltage controlled current source (VCCS) can sere as transconductance amplifier. Q: How can we translate current output to oltage? A: Measure oltage drop across load resistor. Transconductance Amplifier 6 (eq5. 30) function of input out supply G i R DS DD D D Figure 5.27: (a) simple MOSFET amplifier with input GS and output DS

7 Voltage Transfer Characteristic Voltage transfer characteristics (VTC) plot of output oltage s. input oltage Three regions exist in VTC GS < V t OFF OV = GS V t < 0 7 I D = 0, out = DD V t < GS < DS + V t SATURATION OV = GS V t > 0 I D = ½ k n ( GS V t ) 2 DS >> OV Figure 5.27: (b) the oltage transfer characteristic (VTC) of the amplifier out = V DD I D R D DS + V t < GS < V DD TRIODE OV = GS V t > 0 I D = k n ( GS V t DS ) DS DS < OV out = V DD I D R D

8 cutoff FET Voltage Transfer Characteristic cutoff AMP Q: What obserations can be drawn? A: Cutoff FET represents transistor off ( out =V DD ) Cutoff AMP represents out = 0 A: As GS increases, DS (effectiely) decreases i D increases out decreases nonlinearly gain decreases A: Once DS > V DD, all power is dissipated by resistor R D 8 Figure 5.27: (b) the oltage transfer characteristic (VTC) of the amplifier

9 Voltage Transfer Characteristic Q: How do we define DS in terms of GS for saturation? 9 Figure 5.27: (b) the oltage transfer characteristic (VTC) of the amplifier from preious slide Note: GS and DS are instantaneous oltages (DC+AC) (eq5.32) (eq5.33) GS this is equation is simply ohm's law / KVL 1 2 V k V R 2 V DS DD n GS t D B V t i D 2k R V 1 1 n D DD kr Q: How do we define point B boundary between saturation and triode regions? n D

10 Biasing the MOSFET to Obtain Linear Amplification 10 Q: How can we linearize VTC? A: Biasing A: DC oltage V GS is selected to obtain operation at point Q on segment AB Q: How do we choose V GS? A: Next slide (eq5.34) this equation is simply ohm's law 1 V V k V V 2 R 2 DS DD n GS t D V I R source D D Figure 5.28: biasing the MOSFET amplifier at point Q located on segment AB of VTC

11 Biasing the MOSFET to Obtain Linear Amplification 11 Bias point / DC operating pt. (Q) point of linearization for MOSFET Q: How will Q help us? A: Because VTC is linear near Q, we may perform linear amplification of signal << Q (eq5.34) this equation is simply ohm's law 1 V V k V V 2 R 2 DS DD n GS t D V I R source D D Figure 5.28: biasing the MOSFET amplifier at point Q located on segment AB of VTC

12 Biasing the MOSFET to Obtain Linear Amplification 12 Linear amplification around Q in saturation region

13 Biasing the MOSFET to Obtain Linear Amplification 13 Q: How is linear gain achieed? step #1: Bias MOSFET with dc oltage V GS as defined by (5.34) step #2: Superimpose amplifier input ( gs ) upon V GS step #3: Resultant ds should be linearly proportional to small-signal component gs (eq5.34) GS GS gs ds t gs t t V t this equation is simply ohm's law 1 V V k V V 2 R 2 DS DD n GS t D V I R source D D

14 Q: How is linear gain achieed? 14 As long as gs (t) is small, its effect on ds (t) will be linear: facilitating linear amplification.

15 Input and Output Voltages 15

16 Q: How is linear gain achieed? 16 (eq5.35) A d d DS GS V GS GS means that gs is small action: replace with (5.32) DS (eq5.35) A 1 2 DD 2 n GS t D d V k V R d GS GS V GS action: simplify (eq5.36) A k V V R n GS t D (eq5. 37 ) action: replace with V OV A k V R n OV D

17 Small-Signal Voltage Gain 17 Q: What obserations can be made about oltage gain? A: Gain is negatie (180 deg phase shift) A: Gain is proportional to: load resistance (R D ) transistor conductance parameter (k n ) oerdrie oltage ( OV ) (eq5.35) (eq5.35) (eq5.36) (eq5.37) A A d d DS GS V GS GS means that gs is small action: replace with (5.32) 1 2 DD 2 n GS t D d V k V R d action: simplify GS A k V V R n GS t D action: replace with VOV A k V R n OV D DS GS V GS

18 Small-Signal Voltage Gain 18 Equation (5.38) is another ersion of (5.37) which incorporates (5.17). It demonstrates that gain is ratio of: oltage drop across R D half of oer oltage (eq5.37) (eq5.38) A k V R A n OV D action: incorporate (5.17) i k D nov IR D D VO V /2

19 Small-Signal Voltage Gain Q: How does (5.38) relate to physical deices? A: For modern CMOS technology, OV is usually no less than 0.2V. A: This means that max achieable gain is approximately 10V DD. 19 max A max V V OV DD I D 0.1V /2 R D 10V DD For example, 0.13 μm CMOS technology with V DD = 1.3 V yields maximum gain of 13 V/V.

20 Example 5.9: MOSFET Amplifier 20 Problem Statement: Consider the amplifier circuit shown in Figure 5.29(a). The transistor is specified to hae V t = 0.4V, k n = 0.4mA/V 2, W/L = 10, and l = 0. Also, let V DD = 1.8V, R D = 17.5 kω, and V GS = 0.6V. Q(a): For gs = 0 (and hence ds = 0), find V OV, I D, V DS, and A. Q(b): What is the maximum symmetrical signal swing allowed at the drain? Hence, find the maximum allowable amplitude of a sinusoidal gs.

21 Determining the VTC ia Graphical Analysis 21 Graphical method for determining VTC is shown in Figure Draw load line based on eq.5.36 Based on obseration that, for each alue of GS, circuit will operate at intersection of i D and DS. (eq5.39) i D V R DD D R DS D Note: that slope of load line = -1/R D

22 Determining the VTC ia Graphical Analysis 22 Point A where GS = V t Point Q where MOSFET may be biased for amplifier operation Points A (open) and C (closed) are suitable for switch applications GS = V GS, DS = V DS Point B where MOSFET leaes saturation / enters triode Point C where MOSFET is deep in triode region and GS = V DD Point Q is suitable for amplifier applications

23 MOSFET as a Switch 23 Closed GS = V DD Input = 1 (V DD =2.5 V or 5 V) Open GS = V t Input = 0 (ery small) DS = V DS c Output = 0 (ery small V DS ) DS = V DD Output = 1 (V DD =2.5 V or 5 V)

24 Locating the Bias Point Q Bias point (Q) is determined by alue of GS and load resistance R D. Trade-off between Required gain Linear range: allowable signal swing at output. 24 linear range is large linear range is small gain is low gain is high

25 Locating the Bias Point Q 25 To define load resistance R D, one should refer to the i D - DS plane. Two examples of R D are shown Q 2 : too close to triode Not enough legroom (negatie peaks get cutoff) Q 1 : too close to V DD Not enough headroom (positie peaks get cut-off) Ideally, we want to be somewhere in the middle The objectie is to stop DS from clipping or entering triode region

26 5.5. Small-Signal Operation and Models 26 Output oltage Input oltage to be amplified DC bias oltages V GS and V DS Figure 5.34: Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.

27 The DC Bias Point Q: How is dc bias current I D defined? 27 (eq5.40) (eq5.41) only applies in saturation where V 1 1 I k V V k V 2 2 V V R I 2 2 D n GS t n OV DS DD D D DS V OV

28 The Signal Current in the Drain Terminal Q: What is effect of gs on i D? Step #1: Define GS as in (5.42). Step #2: Define i D, separate terms as function of V GS and gs (eq5.42) (eq5.17) (eq5.43) V GS GS gs (eq5. 43 ) action: state (5.17) 1 i k V V 2 GS i D n GS gs t D OV 2 1 VGS Vt kn 2 2 VGS Vt gs VGS gs Vt action: expand the squared term ia V V and action: simplify 1 2 id kn VGS Vt 2 1 k V V k 2 2 n GS t gs n gs 2 GS t gs 28 2 gs

29 Step #3: Classify terms. DC bias current (I D ). Linear gain is desirable. Q: What is effect of gs on i D? Nonlinear distortion is undesirable Note that to minimize nonlinear distortion, gs should be kept small. ½k n gs2 << k n (V GS -V t ) gs gs << 2(V GS -V t ) 29 gs << 2 OV (eq5.43) D n GS t n GS t gs n gs i k V V k V V k 2 2 dc bias current I D linear gain term nonlinear distortion term

30 Q: What is effect of gs on i D? If gs << 2 OV, neglect distortion 30 (eq5.43) (eq5.47) 1 1 i k V V k V V k D n GS t n GS t gs n gs dc bias current I D linear gain term MOSFET transconductance nonlinear distortion term gg k V V m = i d = k n (V GS V tn ) gs gs m n GS t id

31 MOSFET Transconductance g m 31 eq (5.49)

32 The Voltage Gain 32 Q: How is oltage gain (A ) defined? Step #1: Define DS for circuit of KVL dc component V action: apply small-signal condition V R i V R I i DS DD D D DD D D d DS action: regroup terms action: simplify V R I R i V R DD D D D d DS D DS i ds d Figure 5.34

33 The Voltage Gain 33 Step #2: Isolate ds component of DS Step #3: Sole for gain (A ) (eq5.50) (eq5.50) action: isolate ds ds R i ds D d action: insert (5.47) R g D m gs g m = i d = k n (V GS V tn ) gs (eq5.51) A ( 5.47) action: sole for gain g R ds m D gs Figure 5.34

34 The Voltage Gain 34 Output signal is shifted from input by 180 O. Input signal gs << 2(V GS V t ). Operation should remain in MOSFET saturation region DS > GS V t (negatie peak) DS < V DD (positie peak) Figure 5.36: Total instantaneous oltages GS and DS for the circuit in Figure 5.34.

35 Small-Signal Equialent Models 35 From the perspectie of the signal ( gs ), FET behaes as oltage controlled current source (VCCS). Accepts gs between gate and source Proides current (i D ) at drain Input resistance should be as high as possible gate terminal draws i G = 0 Output resistance is high Figure 5.37: Small-signal models for the MOSFET: (a) neglecting the dependence of i D on DS in saturation (the channel-length modulation effect) and (b) including the effect of channel length modulation

36 Small-Signal Equialent Models 36 Model (b) is more accurate than model (a) r o = V A / I D Small signal parameters (g m, r o ) both depend on dc bias point If channel-length modulation is considered, (5.51) becomes (5.54). (eq5.51) less accurate, b/c does not consider channel length modulation A ds m D gs ds (eq5.54) A g R r g R m D o gs more accurate, b/c does consider channel length modulation

37 The Transconductance g m 37 Obserations from (5.47) g m is proportional to m n, C ox, ratio W/L, dc component V OV MOSFET with short / wide channel proides maximum gain Gain may be increased ia V GS, but not without reducing allowable swing of gs. (eq5.47) (eq5.47) (eq5.55) g k V V gs m n GS t id m g m = i d = k n (V GS V tn ) gs g g action: make some substitutions W k n VGS Vt L k n action: simplify k W V m n OV L

38 Obserations from (5.47) g m is proportional to square root of dc bias current (I D ) For gien I D, g m is proportional to (W/L) 1/2 Dependent on 3 design parameters: W/L, V OV, I D The Transconductance g m (eq5.40) (eq5.40) V (eq5. 55) (eq5.56) g 1 W I k V 2 L 2 D n OV OV action: sole (5.40) for V 2I k W / L action: substitute for V as defined aboe 2ID kw / L (eq5. 56) g 2 k W / L I OV n OV W g k V L D m n OV m W k n L n action: simplify m n D 38

39 5.5.6: The Transconductance g m Figure 5.38 illustrates the relationship defined in (5.57). 39 (eq5.55) (eq5.56) (eq5.57) W g k V L g g m n OV m m V W action: replace kn L V GS 2I D V 2 action: simplify 2ID 2I V V t D GS t OV V OV Figure 5.38: The slope of the tangent at the bias point Q intersects the OV axis at 1/2V OV. Thus g m = I D /(1/2V OV ).

40 Example 5.10: MOSFET Amplifier 40 Figure 5.39(a): MOSFET amplifier with a drain-to-gate resistance R G for biasing purposes. The input signal I is coupled to the gate ia a large capacitor, and the output signal at the drain is coupled to the load resistance R L ia another large capacitor. V t = 1.5 V, k n(w/l) = 0.25 ma/v 2, and V A = 50 V. (a) Find small-signal oltage gain, (b) Find input resistance, and the largest allowable input signal. DC Analysis AC (small signal) Analysis

41 The T Equialent-Circuit Model 41 Figure 5.40: Deelopment of the T equialent-circuit model for the MOSFET. For simplicity, r o has been omitted; howeer, it may be added between D and S in the T model of (d).

42 The T Equialent-Circuit Model Include r o (channel-length modulation effect) 42

43 Small Signal Models of MOSFET 43 Hybrid-π model T model