Integrated Circuit Amplifiers. Comparison of MOSFETs and BJTs

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1 Integrated Circuit Amplifiers Comparison of MOSFETs and BJTs 17

2 Typical CMOS Device Parameters 0.8 µm 0.25 µm 0.13 µm Parameter NMOS PMOS NMOS PMOS NMOS PMOS t ox (nm) C ox (ff/µm 2 ) µ (cm 2 /V s) µc ox (µa/v 2 ) V t0 (V) V DD (V) V A (V/µm) C ov (ff/µm) Oxide thickness is decreasing Capacitance increases Increases electric field (V/d) 18

3 Typical CMOS Device Parameters 0.8 µm 0.25 µm 0.13 µm Parameter NMOS PMOS NMOS PMOS NMOS PMOS t ox (nm) C ox (ff/µm 2 ) µ (cm 2 /V s) µc ox (µa/v 2 ) V t0 (V) V DD (V) V A (V/µm) C ov (ff/µm) Reduced device geometry increases transistors/unit area (L 2 ) increases total power dissipation channel length modulation more pronounced increases device speed (i = C dv/dt) 19

4 Typical CMOS Device Parameters 0.8 µm 0.25 µm 0.13 µm Parameter NMOS PMOS NMOS PMOS NMOS PMOS t ox (nm) C ox (ff/µm 2 ) µ (cm 2 /V s) µc ox (µa/v 2 ) V t0 (V) V DD (V) V A (V/µm) C ov (ff/µm) Reduced operating voltage reduces power consumption (CV 2 ) V t is a larger portion of V DD 20

5 Typical BJT Device Parameters Standard high voltage process Advanced low voltage process Parameter npn Lateral pnp npn Lateral pnp A E (µm 2 ) I S (A) 5 x x x x β V A (V) V CE0 (V) t F 350 ps 30 ns 10 ps 650 ps C je0 1 pf 300 ff 5 ff 14 ff C m0 300 ff 1 pf 5 ff 15 ff r x (Ω) Good performance pnp transistors are harder to fabricate on IC than npn (b and forward transit time) 21

6 Typical BJT Device Parameters Standard high voltage process Advanced low voltage process Parameter npn Lateral pnp npn Lateral pnp A E (µm 2 ) I S (A) 5 x x x x β V A (V) V CE0 (V) t F 350 ps 30 ns 10 ps 650 ps C je0 1 pf 300 ff 5 ff 14 ff C m0 300 ff 1 pf 5 ff 15 ff r x (Ω) f T = MHz f T = GHz 22

7 Typical BJT Device Parameters Standard high voltage process Advanced low voltage process Parameter npn Lateral pnp npn Lateral pnp A E (µm 2 ) I S (A) 5 x x x x β V A (V) V CE0 (V) t F 350 ps 30 ns 10 ps 650 ps C je0 1 pf 300 ff 5 ff 14 ff C m0 300 ff 1 pf 5 ff 15 ff r x (Ω) Higher speed technology coupled with lower C-E breakdown voltage 23

8 Electronic Circuits EE359A Bruce McNair B Lecture 12 1

9 MOSFET vs. BJT current-voltage characteristic i C ( v) i D ( v) v The drain current of a MOSFET follows a square law relationship The collector current of a BJT follows an exponential relationship This means that the BJT can control a current that varies over ~5 orders of magnitude, compared to MOSFET current that varies as v OV 2 ( V), or about 1 order of magnitude. 2

10 MOSFET vs. BJT design parameters Significant parameter MOSFET W/L BJT A E (E-B junction area) Range :1 3

11 MOSFET vs. BJT design tradeoffs Available parameters MOSFET I D, V OV, W, L BJT I C, V BE, I S Useful parameters Pick any 3 I C (V BE is related and not very adjustable) 4

12 Differential and Multistage Amplifiers Ch 8 5

13 Noise issues with single ended systems Noise, interference Ground loops, offset reference 6

14 Noise issues with single ended systems Noise, interference Large effective antenna 7

15 DC offset issues with single ended systems offset reference 8

16 Differential benefits + - Differential signal Independent of ground reference + - 9

17 Differential benefits Differential amplification lends itself to twisted pair wiring + - Alternate loops cancel Small antenna loops

18 MOS differential pair MOSFETs are biased for saturation mode operation (not triode region) Resistive loads (for now) Ideal current source 11

19 Common-mode input voltage Assume identical MOSFETs, identical drain resistors 12

20 Common-mode input voltage Range of common mode voltage is limited: I V + V + V + V V V + V R 2 V CS ss CS t OV CM DD t D 13

21 Differential input voltage For all current to flow through Q 1 : 1 W I = k v V 2 L ( ) 2 ' n GS1 t 14

22 Differential input voltage For all current to flow through Q 1 : This determines limits of v id : 1 W I = k v V 2 L ( ) 2 ' n GS1 t 2V v 2V OV id OV 15

23 Differential input voltage For all current to flow through Q 1 : This determines limits of v id : 1 W I = k v V 2 L ( ) 2 ' n GS1 t 2V v 2V OV id OV Both transistors are in saturation, even though one is not conducting 16

24 Large signal operation 1 W i = k v V 2 L ( ) 2 ' D1 n GS1 t 1 W i = k v V 2 L ( ) 2 ' D2 n GS2 t v = v v = v v id GS1 GS 2 G1 G2 17

25 Large signal operation 1 W i = k v V 2 L ( ) 2 ' D1 n GS1 t 1 W i = k v V 2 L ( ) 2 ' D2 n GS2 t v = v v = v v id GS1 GS 2 G1 G2 1 W i i = k v 2 L I = i + i ' D1 D2 n id D1 D2 18

26 Large signal operation 1 W i = k v V 2 L ( ) 2 ' D1 n GS1 t 1 W i = k v V 2 L ( ) 2 ' D2 n GS2 t i D1 v = v v = v v id GS1 GS 2 G1 G2 I I vid vid /2 = VOV 2 VOV 2 1 W i i = k v 2 L I = i + i ' D1 D2 n id D1 D2 i D1 I I vid vid /2 = 1 2 VOV 2 VOV 2 19

27 Large signal operation 20

28 Large signal operation Nonlinear operating characteristics 21

29 Large signal operation Limited linear operating range v id /2 << V OV 22

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