Chapter 8 Differential and Multistage Amplifiers

Size: px

Start display at page:

Download "Chapter 8 Differential and Multistage Amplifiers"

Marilynn French
5 years ago
Views:

1 1 Chapter 8 Differential and Multistage Amplifiers

2 Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: Active-Loaded Differential Pair 4. Ch 10: Feedback 5. Ch 11: Output Stages

3 Active-Loaded Differential Pair 3 Two Stage Op Amp (MOSFET)

4 Learning Objectives 4 1) MOS and the bipolar differential amplifiers: how they reject common-mode noise or interference and amplify differential signals 2) The analysis and design of MOS and BJT differential amplifiers: utilizing passive resistive loads, currentsource loads, and cascodes 3) The structure, analysis, and design of amplifiers composed of two or more stages in cascade

5 Why Differential? 0) What is a differential signal? 1) Differential circuits are less sensitive to noise and interference 2) Differential configuration enables biasing the amplifier and coupling of amplifier stages without bypass and coupling capacitors 3) Useful in IC design because of good matching between the transistors 5

6 6 MOS Differential Pair

7 8.1. The MOS Differential Pair 7 Differential Pair Two matched transistors (Q 1 and Q 2 ) joined and biased by a constant current source I FETs should not enter triode region

8 8 Input Common Mode Range

9 Operation with a Common-Mode Input Voltage Suppose that two gate terminals are joined together and connected to a common-mode voltage (V CM ) v G1 = v G2 = V CM 9 Q 1 and Q 2 are matched Current I will divide equally between the two transistors. I D1 = I D2 = I/2, V S = V CM V GS; where V GS is the gate-tosource voltage.

10 Operation with a Common-Mode Input Voltage Equations (8.2) through (8.8) describe this circuit (channellength modulation is neglected) Note the range (max and min) of input common-mode voltage (V CM ): beyond this range the diff pair leaves saturation I 1 W (8.2) k n VGS Vt 2 2 L (8.3) V V V (8.4) (8.5) OV GS t I 1 W k n V 2 2 L V OV IW k L n 2 OV I (8.6) vd1 vd2 VDD RD 2 I (8.7) maxvcm Vt VDD RD 2 (8.8) min V V V V V 2 10 CM SS CS t OV

11 Operation with a Differential Input Voltage 11 v id is applied to Q 1 and Q 2 is grounded: v id = v GS1 v GS2 > 0 i D1 > i D2 The opposite applies if Q 1 is grounded The differential pair responds to a differencemode or differential input signals. The diff pair provides corresponding differential output signal between the two drains

12 12 Differential Input Voltage

13 Operation with a Differential Input Voltage Two input terminals connected to a differntial signal v id Bias current I of a perfectly symmetrical differential pair divides equally To steer the current completely to one side of the pair, a difference input voltage v id of at least 2V OV is needed. ( 8.9) 1 W I k v V 2 L GS1 GS1 n GS1 t id GS1 S 13 ( 8. 9) v V 2 I / k W / L (8.9) v ( 8.10) max (8.10) max t V t id 2V OV n v V v v 2V OV 2

14 14 Large Signal Operation

15 Objective: derive expressions for drain current i D1 and i D2 in terms of differential signal v id = v G1 v G Large-Signal Operation 15 Assumptions: Perfectly matched transistors Channel-length modulation is neglected Load independence is present Saturation region

16 Step #1: Expression drain currents for Q 1 and Q 2. Step #2: Take the square roots of both sides of both (8.11) and (8.12) Step #3: Subtract (8.14) from (8.15) and perform appropriate substitution. Step #4: Note the constantcurrent bias constraint Large-Signal Operation 1 W 2 (8.11) id1 k n vgs1 Vt 2 L 1 W 2 (8.12) id2 k n vgs2 Vt 2 L (8.13) 1 W i k v V 2 L D1 n GS1 t 1 W (8.14) i k v V 2 L D2 n GS2 t (8.15) v v v v v GS1 GS2 G1 G2 id 16

17 8.1.3 Large-Signal Operation 17 Step #5: Simplify (8.15). Step #6: Incorporate the constant-current bias. Step #7: Solve (8.16) and (8.17) for the two unknowns i D1 and i D2. (8.17) D1 D2 1 W 2 (8.17) 2 id1id2 I k n vid 2 L (8.23) i i I i D1 I I vid vid /2 1 2 VOV 2 VOV 2 I I vid vid /2 (8.24) id2 1 2 VOV 2 VOV 2

18 8.1.3 Large-Signal Operation Transfer characteristics of (8.23) and (8.24) are nonlinear. Linear amplification is desirable and v id will be as small as possible. For a given value of V OV, the only option is to keep v id /2 much smaller than V OV. (8.25) i (8.26) i (8. 27) i small-signal approximation D1 D2 d I I v 2 VOV 2 id I I v 2 VOV 2 I V OV v 2 id id 18

19 8.1.3 Large-Signal Operation 19 Figure 8.7: The linear range of operation of the MOS differential pair can be extended by operating the transistor at a higher value of V OV. V OV increases (smaller W/L): Gain will decrease, Linearity will increase V OV decreases (larger W/L): Gain will increase, Linearity will decrease Can increase the bias current to increase g m and gain

20 20 Small-signal Operation

21 8.2 Small-Signal Operation of the MOS Differential Pair 21 Virtual ground at the source - Elimintates need for large bypass capacitor V CM = bias voltage at the gate v id = differential small signal

22 For MOS pair, each device operates with drain current I/2 and corresponding overdrive voltage (V OV ). g m = I/V OV r o = V A /(I/2) Differential Gain 1 (8.28) vg1 VCM vid 2 1 (8.29) vg2 VCM vid 2 (8.30) 2ID 2( I/2) I V V V vid (8.31) vo1 gm RD 2 vid (8.32) vo2 gm RD 2 (8.35) g A m v OV OV OV g R od d m D vid 22

23 8.2.1 Differential Gain v i1 = V CM + v id /2 and v i2 = V CM v id /2 causes a virtual signal ground to appear on the common-source (common-emitter) connection 23 Current in Q 1 increases by g m v id /2 and the current in Q 2 decreases by g m v id /2 Voltage amplitudes of g m (R D r o )v id /2 develop at the two drains

24 The Differential Half-Circuit 24 Figure 8.9 (right): The equivalent differential halfcircuit of the differential amplifier of Figure 8.8 Here Q 1 is biased at I/2 and is operating at V OV This circuit may be used to determine the differential voltage gain of the differential amplifier A d = v od /v id.

25 8.2.3 The Differential Amplifier with Current-Source Loads 25 To obtain higher gain, the passive resistances (R D ) can be replaced with current sources. A d = g m1 (r o1 r o3 ) Figure 8.11: (a) Differential amplifier with current-source loads formed by Q 3 and Q 4. (b) Differential half-circuit of the amplifier in (a).

26 8.2.4 Cascode Differential Amplifier Gain can be increased via cascode configuration discussed in Section A d = g m1 (R on R op ) R on = (g m3 r o3 )r o1 R op = (g m5 r o5 )r o7 Figure 8.12: (a) Cascode differential amplifier; and (b) its differential half circuit.

27 27 Common Mode Rejection Ratio (CMRR)

28 8.2.5 Common-Mode Gain and Common-Mode Rejection ratio (CMRR) 28 a) v in = V CM (DC common-mode signal) + v icm (common-mode noise or interference) b) current source with fininte output resistance R SS

29 8.2.5 Common-Mode Gain and Common-Mode Rejection ratio (CMRR) 29 c) T model without r o d) common-mode half circuit

30 8.2.5 Common-Mode Gain and Common-Mode Rejection ratio (CMRR) Equation (8.43) describes effect of common-mode signal (v icm ) on v o1 and v o2. (8.41) (8.42) (8.43) (8.44) (8.45) v i icm g m m 30 D o1 o2 icm 1/ gm 2RSS o1 o2 2iR v v v 0 od o2 o1 i SS SS R v v v v vicm 1/ g 2R v vicmr 2R SS D

31 8.2.5 Common-Mode Gain and Common-Mode Rejection ratio (CMRR) When the output is taken singleended, magnitude of commonmode gain is defined in (8.46) and (8.47) Taking the output differentially results in the perfectly matched case, in zero A cm (infinite CMRR) Mismatches between the drain resistances make A cm finite even when the output is taken differentially. CMRR is the ratio of differential gain over common-mode gain (8.46) (8.48) v (8. 47) v o1 o2 R 2R R D SS RD's are mismatched D 2R v SS icm R D od o2 o1 icm 2RSS 31 vod R D R D R D (8.49) Acm vicm 2RSS 2RSS RD D v icm R v v v v ( 8.50) CMRR A A d cm

32 8.4.1 Input Offset Voltage Device mismatches cause a finite dc voltage at the output 32 Apply a small voltage of opposite polarity to cancel the offset

33 33 BJT Differential Pair

34 8.3 The BJT Differential Pair 34 Figure 8.15 shows the basic BJT differential-pair configuration It is similar to the MOSFET circuit composed of two matched transistors biased by a constant-current source and is modeled by similar expressions.

35 8.3.1 Basic Operation 35 Suppose that the two bases joined together and connected to a commonmode voltage V CM Since Q 1 and Q 2 are matched, and assuming an ideal bias current I with infinite output resistance, this current will flow equally through both transistors.

36 36 Input Common Mode Range

37 8.3.2 Input Common-Mode Range 37 The allowable range of V CM is determined at the upper end by Q 1 and Q 2 leaving the active mode and entering saturation. Equations (8.66) and (8.67) define the minimum and maximum common-mode input voltages. I (8.66) maxvcm VC 0.4 VCC RC 2 (8.67) min V V V V CM EE CS BE 0.4

38 38 Large Signal Operation

39 8.3.3 Large Signal Operation 39 (1) Note that the linear range of BJT diff pair is smaller than the MOS diff pair (2) It can be used for fast switching (ECL logic) by current steering: e.g. current flows entirely in one branch then switches to the other branch; requires only 4V T (3) The difference input signal, v id should be less than V T /2 to linear amplification

40 How to increase the linear range? 40 Figure 8.18 The transfer characteristics of the BJT differential pair (a) can be linearized (b) (i.e., the linear range of operation can be extended) by including resistances in the emitters.

41 41 Small Signal Operation

42 8.3.4 Small Signal Operation 42 Bias voltage (DC) + small signal (ac) g i c m I V C T I 2V T...(8.80) I vid vid vid gm ie 2V T 2 2 2re...(8.83)

43 8.3.4 Small Signal Operation: half-circuit 43 Virtual Ground A g d m ( RC ro )...(8.95)

44 8.3.4 Small Signal Operation: single-ended input (1) Emitter voltage is no longer at virtual ground. 44 (2) Voltage at the emitters is appx. V id /2 Note that we can apply signal in the MOS diff pair in similar fashion

45 8.3.5 Common-mode gain and CMRR 45 R...(8.98), (8.99) 2 2 C RC RC A cm REE re REE RC A R 2 d C CMRR g mree ) Acm RC...(8.100 CMRR is the ratio of differential gain over common-mode gain

46 8.4.2 Input Offset Voltage Device mismatches cause a finite dc voltage at the output 46 V OS smaller than MOS diff pair Apply a small voltage of opposite polarity to cancel the offset

47 List of Problems MOS Diff Pair p8.2: input common mode range of PMOS differential amplifier ex8.4 MOS diff pair: differential gain ex8.7 (simulate and verify) MOS diff pair: CMRR p8.15: design of MOS differential amplifier 47 BJT Diff Pair p8.34: input common mode range of npn differential amplifier ex8.13: BJT diff pair: differential gain, CMRR p8.49 (simulate): design of BJT differential amplifier p8.62 (simulation only): npn differential amplifier

Applied Electronics II

Applied Electronics II Chapter 2: Differential Amplifier School of Electrical and Computer Engineering Addis Ababa Institute of Technology Addis Ababa University Daniel D./Abel G. April 4, 2016 Chapter