Depletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET

Transcription

1 Ch. 13 MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor : I D D-mode E-mode V g The gate oxide is made of dielectric SiO 2 with e = 3.9 Depletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET Enhancement-mode operation ( 증가형 ): Using an input gate voltage to effectively increase the channel size of an FET

2 Basic Structure of MOSFET n-type D-MOSFET: n-type conduction channel is On at zero gate voltage with p-type substrate. For the switching operation, the channel should be depleted. It is operated in both the depletion and enhancement mode. n-type E-MOSFET: n-type conduction channel is Off at zero gate voltage with p-type substrate. For the switching operation, the channel should be enhanced. It is operated in the enhancement mode only.

3 Operation of D-MOSFET (1) Conduction channel is ON with I D = I DSS for V GS = 0 V For negative gate voltage of V GS < 0 V, the effective channel width of n-type semiconductor is reduced to decrease I D (and to increase the channel resistance) ~ depletion of electrons Thus I D < I DSS for V GS < 0 V I D I DSS V V GS 1 GS ( off ) 2

4 Operation of D-MOSFET (2) For positive gate voltage of V GS > 0 V, the effective channel width of n-type semiconductor is enlarged to increase I D (and to decrease the channel resistance) ~ accumulation of electrons and depletion of holes Thus I D > I DSS for V GS > 0 V ~ different from JFET I D I DSS V V GS 1 GS ( off ) 2

5 D-MOSFET : Drain curves & Transconductance 1 ma -6 V Drain current I D is constant for V DS > V P V P is proportional to V GS Transconductance is given by Saturated I D does not depend on V DS g m g m0 V V GS 1 GS ( off ) Since I D can be larger than I DSS, g m can be larger than g m0

6 D-MOSFET : Biasing circuits The gate voltage of V GS need not to be negative in D-MOSFET ~ different from JFET Gate-, self-, and voltage-divider-biasing is used for the operation of MOSFET Additionally, zero-biasing circuit is used for D-MOSFET ~ V GS = 0 V, I D = I DSS, R S = 0

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8 E-MOSFET Initially, the conduction channel is OFF (I D = 0) for V GS = 0 V For positive gate voltage of V GS > 0 V, the holes in p-type substrate is depleted and the electrons are accumulated in n-type semiconductor to open the conduction channel. More positive V GS increases both the channel width and I D.

9 E-MOSFET: Transconductance Curve V GS > V GS(th) V for the Turn On state (I D 0) I k V V D GS GS ( th) k V I D( on) V GS ( on) GS ( th) 2 2 Difference with the transconductance curve in JFET: The current-on V GS is always positive Turn-on (or turn-off) point of V GS is called as a threshold voltage of V GS(th)

10 [Ex. 13-2] For an E-MOSFET of #3N171, I D(on) = 10 ma, V GS = 10 V, and V GS(th) = 1.5 V are given. Find out I D for the circuit below. 10 ma 1.5 V 10 V I 10mA k A / V V 10V 1.5V GS ( on) V GS ( th) Since R 0, V V D( on) S GS G R 2 VG VDD 10V 5V R1R 2 2M 1M ID k VGS V GS ( th) A / V 5V 1.5V 1.69mA

11 E-MOSFET: Drain-Feedback Bias Self-bias or zero-bias circuit is not available for an E-MOSFET due to a negative V GS Voltage-divider-, gate-, and drain-feedback-bias are used for an E-MOSFET Drain-feedback bias circuit is shown below: We put gate resistance (R G ) between drain and gate Since no current flows through R G, V G = V D and thus V GS = V DS V R DD D Since V DS = V DD I D R D, I D 0 for VGS VDD VDD VDS VDD VGS VDD R for VGS 0 D RD RD When V GS = V DS, I D = I D(on) I D ( on ) V GS V DS V DD

12 [Ex. 13-3] For an E-MOSFET of #3N170 with I D(on) = 10 ma, Find out V DS and I D for the circuit below. DS DD D D( on) D( on) V V R I 20V 1k 10mA 10V I I 10mA D Small-signal operation of the E-MOSFET amplifier

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14 Dual-Gate MOSFET MOSFET as a large capacitor ~ High-frequency application is limited Two gate electrodes for a MOSFET ~ total capacitance of two capacitors in series is smaller than the respective capacitance Reduced capacitance of a MOSFET using dual-gate electrodes

15 Complementary MOSFET (CMOS) Digital signal consists of rapidly-switching dc voltage levels Logic levels ~ dc 0 V and +5 V Logic families: Groups of digital circuits with nearly identical characteristics CMOS: A logic families of MOSFETs

16 CMOS Inverter Digital circuit that converts one logic level to another Example: Input = 0 V Output = 5 V Input = 5 V Output = 0 V p-channel E-MOSFET n-channel E-MOSFET

17 CMOS Inverter: p-channel E-MOSFET I D V GS At V GS = 0, the drain current is turned off ~ I D = 0 When V GS = -5 V, the p-channel is turned on Note that V SS = +5 V and V input = 0 V or +5 V V GS = V in - V SS V in V SS V GS Q 1 +5 V +5 V 0 V OFF 0 V + 5 V -5 V ON

18 CMOS Inverter: n-channel E-MOSFET I D V GS At V GS = 0, the drain current is turned off ~ I D = 0 When V GS = +5 V, the n-channel is turned on Note that V DD = +5 V and V input = 0 V or +5 V Since the source is grounded, V GS = V in V in V GS Q 2 +5 V +5 V ON 0 V 0 V OFF

19 CMOS Inverter Q 2 as a drain resistance of Q 1 Q 1 as a drain resistance of Q 2 Q1 Q2 V in (V) Q 1 Q 2 V out (V) 0 On Off Off On 0

20 CMOS NAND gate A B AND NAND T T T F T F F T F T F T F F F T V A V B V out 5 V 5 V 0 V 5 V 0 V 5 V 0 V 5 V 5 V 0 V 0 V 5 V V SS = +5 V Input Switching Q 1 Q 2 V out V A = 5 V V A = 0 V V B = 5 V Q 2 off, Q 3 on Q 2 on, Q 3 off Q 1 off, Q 4 on V A Q 3 V B = 0 V Q 1 on, Q 4 off V B Q 4 Q1, Q2 Q3, Q4

21 CMOS fabrication

22 HW Ch.13 Due = 11/15 (Friday) 15:00 #1. Problem 13-1 #2. Problem 13-5 #3. Problem #4. Problem 13-22