Electronic Devices and Circuits Lecture 20 - Linear Amp. Analysis and Design I - Outline Announcements. )/2 [v IN1.

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1 6.012 Electronic Devices and Circuits Lecture 20 Linear Amp. Analysis and Design I Outline Announcements Handouts Lecture Outline and Summary Announcements Design Problem due in under two weeks Review Differential Amplifier Basics Difference and commonmode signals: v ID = v IN1 v IN2 and v IC = (v IN1 v IN2 )/2 [v IN1 = v IC v ID /2, v IN2 = v IC v ID /2] Halfcircuits: half of original with wires shorted or broken (familiar, easy analyses) Performance metrics specific to diff. amps. Difference and commonmode gains Commonmode rejection ratio Input and output resistances Commonmode input voltage swing; output voltage swing and DC value Nonlinear loads The limitation of resistive loads: Gain limited by voltage supply Nonlinear loads: High incremental resistance w. small voltage drop Active loads Current mirror load Lee load Clif Fonstad, 11/03 Lecture 20 Slide 1

2 Differential Amplifiers what's the big deal? Intrinsic advantages and features: large difference mode gain small common mode gain easy to cascade stages without coupling capacitors no emitter/source capacitor required in CE/CS stages Performance metrics: difference mode voltage gain, A vd common mode voltage gain, A vc common mode rejection ratio, CMRR input resistance, R in output resistance, R out common mode input voltage range output voltage swing DC offset on output Clif Fonstad, 11/03 Lecture 20 Slide 2

3 Differential Amplifier Analysis incremental analysis exploiting symmetry and superposition v in1 Linear equivalent circuit (symmetrical) v in2 v out1 v out2 v in1 a LEHC: one half of sym. LEC a LEHC: one half of sym. LEC v in2 v out1 v out2 Clif Fonstad, 11/03 Lecture 20 Slide 3

4 Differential Amplifier Analysis incremental analysis exploiting symmetry and superposition v id a LEHC: one half of sym. LEC a LEHC: one half of sym. LEC v id v id a LEHC: one half of sym. LEC v od No voltage on common links, so incrementally they are grounded. v od v od = A vd v id v ic a LEHC: one half of sym. LEC a LEHC: one half of sym. LEC v ic v ic a LEHC: one half of sym. LEC v oc No current in common links, so incrementally they are open. v oc v oc = A vc v ic Clif Fonstad, 11/03 Lecture 20 Slide 4

5 Resistor Loads: the limit on maximum gain linear resistor loads require a compromise between voltage gain and output voltage swing V v in I BIAS C O v out C E Maximum Voltage gain V [I C ] max Bipolar : A = g m = qi R C L v,max kt V thermal MOSFET* : A = g m = v,max 2 I D 2 [I D ] max [V GS V T ] [V GS V T ] min What are [I C ] max, [I D ] max, and [V GS V T ] min? Clif Fonstad, 11/03 * For a MOSFET g m = (2KI D ) 1/2 = K(V GS V T ) = 2I D /(V GS V T ) Lecture 20 Slide 5

6 Resistor Loads: cont. V What are [I C ] max, [I D ] max, and [V GS V T ] min? [I C ] max, [I D ] max : Determined by the desired voltage swing C O at output and/or the commonmode input voltage range v in [V GS V T ] min : I BIAS Determined by the process spread in i D 2 V T, and by how close to threshold V the gate can safely be biased before the depletion Actual Ideal approximation model fails. [v GS V T ] min v GS v out V T Clif Fonstad, 11/03 Lecture 20 Slide 6 C E

7 Current Source Loads: the limit on maximum gain current source loads eliminate the compromise between voltage gain and output voltage swing V I LOAD C O v in I BIAS v out C E Maximum Voltage gain V g m qi C kt V Bipolar : A = = = A,eff v,max g g ol oq I C V AL I C V AQ V thermal g m 2 I D [V GS V T ] 2V MOSFET* : A = = A,eff v,max gol g oq I D V AL I D V AQ [V GS V T ] min V AL V with AQ Typically V A,eff >> [I ] max V A,eff [ V AL V AQ ] Clif Fonstad, 11/03 Lecture 20 Slide 7

8 Active Loads: The current mirror load large R in differencemode and small R in common mode efficient conversion from doubleended to singleended output V V id Q1 Q2 id ª 2 id ic Q1 Q2 ic ª 0 id id RL vout ic ic RL vout vid/2 Q3 Q4 vid/2 vic Q3 Q4 vic IBIAS rob IBIAS rob V Differencemode inputs v out = [2g m3 /(g o2 g o4 G L ]v id /2 Commonmode inputs v out = [g ob /2(g m2 g o4 G L )]v ic g ob /2g m2 v ic V With both inputs: v out [2g m3 /(g o2 g o4 G L ]v id /2 g ob /2g m2 v ic Clif Fonstad, 11/03 Lecture 20 Slide 8

9 Active Loads The Lee load a load for a fullydifferential stage that looks like a large resistance in differencemode and small resistance in commonmode V V Q1 Q2 Q3 Q4 Q1 Q3 Q2 Q4 vout1 vout2 vout1 vout2 vin1 vout1 Q5 RL RL vout2 Q6 vin2 vin1 vout1 Q5 RL RL vout2 Q6 vin2 IBIAS rob IBIAS rob V Normal format V Drawn to highlight crosscoupling Clif Fonstad, 11/03 Lecture 20 Slide 9

10 V The Lee load: analysis for differencemode inputs vid/2 Q1 vod/2 Q5 Q3 vod/2 vod/2 RL RL Q2 vod/2 vod/2 Q6 Q4 vod/2 vid/2 IBIAS rob V vid/2 gm5vid/2 go5 go1 gm1 gm3 (= gm1) go3 (= go1) GL vod/2 Difference mode: A vd = v od /v id = g m5 /(g 05 2g o1 G L ) Clif Fonstad, 11/03 Lecture 20 Slide 10

11 V Q1 Q3 Q2 Q4 The Lee load: analysis for commonmode inputs vic voc voc voc voc voc RL RL voc Q5 Q6 vic IBIAS rob V vgs5 gm5vgs5 go5 vic go1 gm1 gm3 go3 (= gm1) (= go1) GL voc gob/2 Common mode: A vc = v oc /v ic = g ob /2(2g 01 2g m1 G L ) g ob /4g m1 Clif Fonstad, 11/03 Lecture 20 Slide 11

12 Achieving the maximum gain: Comparing linear resistors, current sources, and active loads MAXIMUM GAIN Bipolar MOSFET Bipolar MOSFET Linear resistor Linear resistor loads [I C ] max [ I D ] max V thermal [V GS V T ] min 2V Current source A,eff Current source loads V thermal 2V A,eff [V GS V T ] min Active load, A v,diff Active loads Difference mode µ Active load, A v,com Common mode µ V A,eff V thermal V thermal V A,bias V A,eff µ [ V GS V T ] min [V GS V T ] µ min V A,bias Observations: Nonlinear (current source) loads typically yield higher gain than linear resistors, i.e. V A,eff >> [I D ] max Bias level is not important to BJT stage gain A MOSFET should be biased at low level for high gain For active loads what increases A vd, decreases A vc Clif Fonstad, 11/03 Lecture 20 Slide 12

13 6.012 Electronic Devices and Circuits Fall 2003 Design Problem Circuit Full schematic 1.5 V Q 1 A Q 2 Q 3 Q 4 Q 5 Q 8 Q 10 Q 11 A Q 23 Q 9 R 1 B v IN1 B Q 7 Q 6 Q 19 v IN2 B R 2 R 3 Q 12 Q 13 Q 14 Q 15 Q 20 B Q 21 B Q B 22 Q 24 Q 16 Q 17 v OUT Q 18 Bias chain Commonsource gain stage with Lee load Sourcefollower Commonsource 1.5 V stage with gain stage with degeneration current mirror to provide load level shift Emitterfollower output stage Pushpull output stage Clif Fonstad, 11/03 Lecture 20 Slide 13

14 6.012 Electronic Devices and Circuits Fall 2003 Design Problem Circuit Conceptual schematic: full circuit 1.5 V Q 2 Q 3 Lee load Q 4 Q 5 Q 8 Q 10 Current mirror load Q11 Q 9 I BIAS5 v IN1 Q 6 Q 7 R 2 R 3 Q 12 Q 13 v IN2 Q 14 Q 15 Q 16 Q 17 v OUT I BIAS1 I BIAS2 I BIAS3 I BIAS4 I BIAS6 Commonsource gain stage with Lee load Emitterfollower output stage Sourcedegeneration 1.5 V follower Commonsource stage with gain stage with current mirror to provide load level shift Pushpull output stage Clif Fonstad, 11/03 Lecture 20 Slide 14

15 6.012 Electronic Devices and Circuits Fall 2003 Design Problem Circuit Conceptual schematic Differencemode inputs v in1 = v ic v id /2 vin2 = v ic v id /2 r elldm r ecmdm r oq23 vout = v oc v od Q 9 v id /2 R Q 16 3 Q 6 Q 11 r oq22 Q 14 v od vod = A vd v id Commonmode inputs r ellcm Q 9 r ecmcm r oq23 v ic Q R 16 3 Q 6 Q 11 Q 14 2r oq19 2r oq21 v oc voc = A vc v ic r oq22 Clif Fonstad, 11/03 v out = A vc v ic A vd v id Lecture 20 Slide 15

16 6.012 Electronic Devices and Circuits Lecture 20 Linear Amp. Analysis and Design I Summary Performance metrics specific to diff. amps. Difference and commonmode gains: A vd = v od /v id, A vc = v oc /v ic Commonmode rejection ratio: CMRR = A vd /A vc Input and output resistances Commonmode input voltage swing Nonlinear loads Transistors biased in their constant current regions BJTs in their FAR MOSFETs in saturation Optimum bias point for high gain: MOSFET at low I D, BJT at any I C Active loads Current mirror load Achieves double to singleended conversion without loss of gain Has high resistance for differencemode signals Has low resistance for commonmode signals Lee Load Maintains differential signals Has high resistance for differencemode signals Has low resistance for commonmode signal Clif Fonstad, 11/03 Lecture 20 Slide 16