Analysis and Design of Analog Integrated Circuits Lecture 8. Cascode Techniques

Transcription

1 Analysis and Design of Analog Integrated Circuits Lecture 8 Cascode Techniques Michael H. Perrott February 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved.

2 Review of Large Signal Analysis of Current Mirrors V dd V ds2 > V dsat2 = μ n C ox W 2 L 2 ΔV 2 (V GS2 - ) 2 (1+λ 2 V ds2 ) μ n C W 1 ox (V GS1 - ) 2 (1+λ 1 V ds1 ) L 1 ΔV 1 V ss =0 1 2 But, 1 = 2 ΔV 1 = ΔV 2 in Triode in Saturation W 2 L 1 (1+λ 2 V ds2 ) = W 1 L 2 (1+λ 1 V ds1 ) Current setting based on geometry Mismatch due to V ds difference Note: for accurate ratio, set L 1 = L 2 V ds2 V dsat2 2

3 The Issue of V ds Mismatch in Current Mirrors V dd W 2 (1+λ 2 V ds2 ) = W 1 (1+λ 1 V ds1 ) Current setting based on geometry Mismatch due to V ds difference V ds1 V ds2 Note: we are assuming L 1 = L 2 Issue: Current can vary significantly as a function of the drain voltage of - We often want a tightly controlled current set only by and transistor sizes How do we improve the current mirror matching performance? 3

4 Cascoded Current Source I ref R thd3 R thd3 I bias V bias V bias r o1 Offers increased output resistance - Reduces small signal dependence of output current on the output voltage of the current source - From Lecture 6, we derived: Output resistance boosted by intrinsic gain of, g m3 r o3 But how do we reduce the influence of large signal V ds mismatch between and? 4

5 Match V ds of Current Mirror Devices With Proper Bias V dd V o V ds2 > ΔV V ds1 = Recall: W 1 L 4 (1+λ 1 V ds1 ) = W 4 L 1 (1+λ 4 V ds4 ) Current setting based on geometry Mismatch due to V ds difference V ss =0 Key transistor for determining is - Why is less important? Above biasing approach provides a much closer match between V ds1 and V ds4 = W 1 W 4 1+λV ds1 1+λV ds4 W 1 W 4 5

6 The Drawback of Basic Cascode Bias Approach V dd in saturation in triode and in saturation V o V ds2 > ΔV and in triode V ss =0 V ds1 = V 1 +2ΔV V o calculation of V 1 is nontrivial Output voltage range is reduced - Now V o must be > + 2 V - What will happen to the output impedance of the current source if the output voltage is too low? - Can we improve the voltage range? 6

7 Improved Swing Cascode and in saturation V dd and in triode no wasted voltage region α 2 +3ΔV M 5 +2ΔV +2ΔV V o V ds2 > ΔV V dsat1 +V dsat2 V o V ss =0 M 6 V ds1 = ΔV Key idea: set size of such that V ds1 = V - Assuming strong inversion for and : 7

8 Alternative Implementation of Improved Swing Cascode and in saturation V dd M 5 M 6 M 7 W p /L p W p /L p W p /L p α +2ΔV and in triode V o V ds2 > ΔV 2ΔV no wasted voltage region V o V ds1 = ΔV V ss =0 Set as on previous slide Note: both implementations share a common problem 8

9 The Issue of Current Mismatch V ds4 = +2ΔV V ds1 = ΔV Recall: W 2 (1+λ 2 V ds2 ) = W 1 (1+λ 1 V ds1 ) Mismatch due to V ds difference The improved swing approach causes a systematic mismatch between and - Key issue: V ds1 V ds4 Can we fix this problem? 9

10 Techniques to Reduce Current Mismatch +2ΔV V ds4 = ΔV V ds1 = ΔV Systematic mismatch between and is greatly reduced by using the above circuit (now V ds1 V ds4 ) - Note that gate bias on and may be provided by previously discussed circuits Additional techniques for accurately matching and - Set L 1 = L 4 >> L min Note: set L 2 = L 3 L min for lower area and capacitance - Set W 2 /W 3 = / so that V 2 = V 3 10

11 Another Common Cascode Bias Topology V dd M 5 M 6 M 7 W p /L p W p /L p W p /L p M 8 M 9 +2ΔV V ds4 = ΔV V ds1 = ΔV Key issue: needs two bias current branches 11

12 Utilizing a Simple Resistor to Achieve One Bias Branch M 5 M 7 W p /L p W p /L p +2ΔV ΔV R B V ds4 = ΔV V ds1 = ΔV Issue: poly resistor is large and won t track NMOS devices across temperature and process variations 12

13 Better Approach: Use PMOS Device In Triode Region M 5 M 7 W p /L p W p /L p +2ΔV M 6 W p /L p ΔV V ds4 = ΔV V ds1 = ΔV Much smaller, better tracking with NMOS devices than resistor 13

14 Wilson Current Mirror R thd2 Relies on feedback in its operation Using Hybrid- analysis - Output resistance comparable to cascode current source This circuit is rarely used these days 14

15 Enhanced Cascode Current Source I bias I bias2 I ref Offers output resistance comparable to double cascode current source As with Wilson mirror, analysis is tricky due to source/gate coupling - Using results shown in the following slide: 15

16 Thevenin Resistances for CMOS Transistor Feedback Pair R A D R C R thd R A D R C R thd S R ths v gs4 g m4 v gs4 -g mb4 v s4 r o4 R B r o3 -g mb3 v s3 g m3 v gs3 v gs3 S R ths v s3 =0 v s4 R B 16

17 Basic Cascode Amplifier R D V out R ths2 i s2 d2 R G V in RS α 2 i s2 R thd2 R D v out s2 R G g1 R ths1 i s1 d1 Common Gate v in R thg1 v g1 A v1 v g1 α 1 i s1 R thd1 s1 General Model R S Allows improved frequency response (discussed later) Reduction to two-port will be done in several steps 17

18 Eliminate Middle Sections R D V out R ths2 i s2 d2 R G V in RS α 2 i s2 R thd2 R D v out s2 R G g1 d1 R thg1 v in v g1 G m1 v g1 R thd1 Calculation of G m1 same as for common source amp To reduce further, note that 18

19 Resulting Two-Port Similar to Common Source Amp R D V out d2 R G V in RS G m1 v g1 R thd2 R D v out R G g1 v in R thg1 v g1 Key difference: drain impedance much larger 19

20 Slight Twist to Cascode Amplifier R L V out V dd R L Vout I in V bias I bias 1 g m1 +g mb1 i s1 i s1 r o1 V in i in r o4 r o2 V ss =0 What is the difference between this amplifier and basic cascode amplifier? What are the constraints in setting V bias? What is the maximum output voltage swing? 20

21 Constraints on V bias and Output Range V dd R L V out I bias I in >ΔV 1 V bias 1 V in >ΔV 4 >ΔV 2 V ss =0 To keep and in saturation To keep in saturation 21

22 Calculation of Maximum Output Range V dd R L V out I bias I in >ΔV 1 V bias 1 V in >ΔV 4 >ΔV 2 Minimum V bias allows the maximum output range V ss =0 Resulting output range 22

23 Variation on a Theme: Enhanced Cascode Amplifiers I bias1 I bias2 R 1 V out Input Source I in R s We can turn the enhanced cascode current source into an amplifier - Inject a current input at the source of Key aspects of small signal analysis can be done using Thevenin method - Simply leverage Thevenin resistance formulas shown on Slide 16 23

24 Small-Signal Analysis of Enhanced Cascode Amp I bias1 I bias2 R 1 R 1 R out V out V out Input Source Input Source I in R s 1 R thd1 R in g m2 I in R s From Thevenin resistance calculations on Slide 16: - Input impedance is quite low - Output impedance is probably determined by R 1 This amplifier is useful for extracting a current signal while keeping the source voltage nearly constant 24