Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring 2017
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1 Department of Electrical and Computer Engineering, Cornell University ECE 3150: Microelectronics Spring 017 Final Exam ` May, 017 INSTRUCTIONS: Every problem must be done in the separate booklet Only work done on the exam booklets will be graded do not attach your own sheets to the exam booklets under any circumstances To get partial credit you must show all the relevant work Correct answers with wrong reasoning will not get points All questions do not carry equal points All questions do not have the same level of difficulty TOTAL POINTS: 100 Unless specified otherwise, assume room temperature DO NOT WRITE IN THIS SPACE 1
2 Problem 1 (A CMOS RF Oscillator problem) 5 points Consider the following circuit used to realize an RF oscillator: Assume that the current source is ideal (infinite output resistance) and that: 1 p 0.00 V Also, assume that at the frequencies of interest, all the internal capacitances of the PFET are open. a) Find an equation relating the DC voltage V IN to the bias current I BIAS such that the solution of this equation would let you find V IN. (5 b) Is this oscillator based on positive feedback or negative feedback? Explain how this particular feedback is possible in the above circuit. Points awarded will depend on the quality of the explanation. (5 c) Find and expression for the oscillation frequency of the circuit? Show your work. (10 d) Find the value of the minimum transconductance mp g of the PFET, in terms of the given parameters, which will enable this circuit to oscillate? Show your work. (5.
3 Problem (A semiconductor device problem) 5 points Consider the following silicon structure: Suppose: 17 3 Na Nd 10 cm t 0.5 m Dn Dp 40 cm / s n p A 100 m The center region is pure undoped intrinsic silicon. a) In a nice and clean diagram, indicate where in the structure would one have depletion, inversion, and/or accumulation regions in thermal equilibrium (i.e. when V 0 ) and indicate the type of each region. (.5 b) Find an expression for the built in potential B in the structure in thermal equilibrium. (.5 c) Sketch the electric field in the structure in thermal equilibrium. (5 d) If now a potential V is applied, find the thickness of all the depletion regions in terms of the applied bias V. You may just write down equations whose solutions would give these thicknesses. (5 e) Suppose a snapshot of the structure is taken when V 0 and the following excess carrier density profile is obtained: What is the current I (in Amps) flowing through the device? Need a numerical value. (5 f) Same situation and bias as in part (e) above, but now light is shining only in the middle region such that the electron-hole generation rate due to light in the middle region is 10 4 cm -3 -s -1. What is the total current I (in Amps) flowing through the device? Need a numerical value. (5 3
4 Problem 3 (An amplifier problem) 30 points Consider the following CMOS amplifier: Suppose: kn kp 00 A V IBIAS 00 A VTN VTP 0.5V VDD 10V ID5 00 A n p 0.01 VBIAS 4V Vi1 Vi 5V Also, assume that the current sources shown are ideal (i.e. infinite output resistance). a) Find the DC voltages V5, V 4, and V3. Numerical values are needed. (5 b) Assuming pure common mode small-signal input (i.e. vi1 vi vic) what is the minimum value v ic can have before some FET goes out of the saturation region? A numerical value is needed. (5 c) Assuming pure difference mode small-signal input (i.e. vi1 vi vid ) what is the maximum value v out can have before some FET goes out of the saturation region? A numerical value is needed. (5 d) Assuming pure difference mode small-signal input (i.e. vi1 vi vid ), and assuming the output is shorted to ground, find an expression for the current i out that flows into the ground from the (shorted) output terminal. (5 e) Assuming pure difference mode small-signal input (i.e. vi1 vi vid ) find an expression for the (low frequency) small signal difference mode voltage gain Avd vout vid. (10 4
5 Problem 4 (Misc problems) 0 points These parts are unrelated. a) Consider a PFET with the following specs: kp 00 A V 1 p 0.1 V VTP 0.5V L 0. m The PFET is operated such that VGS VTP 1.0V. As the voltage V DS is increased in magnitude (while being negative, of course) while keeping VGS VTP 1.0V, at a certain value of V DS the PFET will break. 5 Assuming that the breakdown field of Silicon is 3 10 V cm, at what value of VDS will the PFET break? Need a numerical value as an answer. (6 Parts (b) and (c): A NPN BJT is biased as shown below and the carrier concentrations at the bias point are also shown below (not to scale). Area A 100 m D D n p 10 cm 5 cm / s / s KT q 5 mv n i cm 3 b) What is the bias current I BIAS? Need a numerical value. (4 c) What is the collector current I C? Need a numerical value. (4 d) What digital logic functions are implemented by the following circuits? Need a logical expression for X in each case. (6 5
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