Lecture 21 - Multistage Amplifiers (I) Multistage Amplifiers. November 22, 2005

Transcription

1 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 2 Lecture 2 Multistage Amplifiers (I) Multistage Amplifiers November 22, 2005 Contents:. Introduction 2. CMOS multistage voltage amplifier 3. BiCMOS multistage voltage amplifier 4. BiCMOS current buffer 5. Coupling amplifier stages Reading assignment: Howe and Sodini, Ch. 9, 9.9.3

2 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 22 Key questions How can one build a wide range of highperformance amplifiers using the singletransistor stages studied so far? What are the most important considerations when assembling mulstistage amplifiers: regarding interstage loading? regarding interstage biasing?

3 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 23. Introduction Amplifier requirements are often demanding: must adapt to specific kinds of signal source and load, must deliver sufficient gain Singletransistor amplifier stages are very limited in what they can accomplish multistage amplifier. V DD signal source v s R S v R L signal load V S V SS Issues: What amplifying stages should be used and in what order? What devices should be used, BJT or MOSFET? How is biasing to be done?

4 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 24 2 Summary of single stage characteristics: stage A vo,g mo,a io R in R out key function CS G mo = g m r o //r oc transcond. amp. CD A vo g m g m g mb g m g mb voltage buffer CG A io g m g mb r oc //[r o ( g m R S )] current buffer CE G mo g m r π r o //r oc transcond. amp. CC A vo r π β(r o //r oc //R L ) g m R S voltage buffer β CB A io g m r oc //{r o [ g m (r π //R S )]} current buffer 2 Key differences between BJT s and MOSFETs: BJT MOSFET I B = I C β I G =0 g m = qi C kt > g m = 2 W L µc oxi D r o = V A I C > r o = λi D

5 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture CMOS multistage voltage amplifier 2 Goals: high voltage gain high R in low R out 2 Good starting point: CS stage R S r o //r oc vs v in g m (r o //r oc )v in v out R L R in = A vo = g m (r o //r oc ), probably insufficient R out = r o //r oc, too high

6 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 26 2 Add second CS stage to get more gain: R S r o //r oc r o2 //r oc2 vs v in g m (r o //r oc )v in v out =v in2 g m2 (r o2 //r oc2 )v in2 vout2 R L R in = A vo = g m (r o //r oc )g m2 (r o2 //r oc2 ) but R out = r o2 //r oc2, still high 2 Add CD stage at output: R S r o2 r oc2 g m3 g mb3 v s v in A vo v in v in3 v in3 g m3 g m3 g mb3 v out R L CS CS CD R in = A vo = g m (r o //r oc )g m2 (r o2 //r oc2 ) g m3, still high g mb3 R out = g m3 g mb3, now small g m3

7 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture BiCMOS multistage voltage amplifier 2 A vo (CE) > A vo (CS) because r o (BJ T ) > r o (M OSF ET ) and g m (BJ T ) > g m (M OSF ET ) but... CS stage is best first stage, since R in =. 2 Add CE stage following CS stage? R S r o r oc r o2 r oc2 v s v A r in vo v in v π2 A vo2 v in2 vout R in2 L CS CE Trouble is interstage loading degrades gain: R out = r o //r oc R in2 = r π2 Voltage divider between stages: R in2 r π2 r π2 = R out R in2 r o //r oc r π2 r o //r oc Additional gain provided by CE stage more than lost in interstage loading.

8 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 28 2 Use two CS stages, but add CC stage at output: R S r o2 r oc2 g m3 r o2 r oc2 β3 v s v in A vo A vo2 v v in in3 r π3 β 3 (r o3 r oc3 R L ) v in3 v out RL CS CS CC Interstage loading: R out2 = r o2 //r oc2, R in3 = r π3 β 3 (r o3 //r oc3 //R L ) Then, interstage loss: R in3 r π3 β 3 (r o3 //r oc3 //R L ) = R out2 R in3 r o2 //r oc2 r π3 β 3 (r o3 //r oc3 //R L ) better than trying to use a CE stage, but still pretty bad. Benefit is that R out has improved: R out2 r o2 //r oc2 R out = R out3 = = g m3 β 3 g m3 β 3 Since, in general, g m (BJ T ) > g m (M OSF ET ), R out could be better than CD output stage if r o2 //r oc2 is not too large. Otherwise, CD stage output is better.

9 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 29 2 Better voltage buffer: cascade CC and CD output stages. What is best order? Since R in (CD) =, best to place CD first: R r o2 r oc2 g m3 g g S mb3 m4 β 4 (g m3 g mb3 ) vs v in A vo A vo2 v in v in3 v in3 v in4 r π4 β 4 (R L r o4 r oc4 ) v in4 v out CS CS CD CC R L Interstage loading: R in3 = R out2 R in3 R in4 r π4 β 4 (r o4 //r oc4 //R L ) R = out3 R in4 g m3 r g π4 β 4 (r o4 //r oc4 //R L ) mb3 and excellent output resistance: R out3 R out = R out4 = = g m4 β 4 g m4 β 4 (g m3 g mb3 )

10 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture BiCMOS current buffer 2 Goals: Unity current gain very low R in very high R out Start with commonbase stage: i in i out i s R S /g m iin r oc //(βr o ) RL A io = R in = g m R out = r oc //{r o [ g m (r π //R S )]} Note that if R S is not too low, R out r oc //(βr o ). Can we further increase R out by adding a second CB stage?

11 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 2 2 CBCB current buffer: i in i in2 i out i s R S g m i in β r o r oc g m2 i in2 R L CB CB [ g m2 r o2 (r π2 β r o r oc )] r oc2 Now R out = R out2 = r oc2 //{r o2 [ g m2 (r π2 //R out )]} Plugging in R out r oc //(β r o ), R out = r oc2 //{r o2 [ g m2 (r π2 //r oc //β r o )]} But, since r π2 r oc //(β r o ), then R out r oc2 //[r o2 ( g m2 r π2 )] r oc2 //(β 2 r o2 ) Did not improve anything! The base current limits the number of CB stages that improve R out to just one. Since CG stage has no gate current, cascade it behind CB stage.

12 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 22 2 CBCG current buffer: i in i in2 i out i s R S g m i in β r o r oc g m2 i in2 R L CB CG [g m2 r o2 (β r o r oc )] r oc2 R out = R out2 = r oc2 //[r o2 ( g m2 R out )] with R out r oc //(β r o ), R out = r oc2 //[r o2 g m2 (r oc //β r o )] Now R out has improved by about g m2 r o2, but only to the extent that r oc2 is high enough...

13 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture Coupling amplifier stages 2 Capacitive coupling Capacitors of large enough value behave as AC short, so signal goes through but bias is independent for each stage. Example, CDCC voltage buffer: 5.0 V 5.0 V 4.0 V 2.5 V 3.2 V 2.5 V I SUP I SUP2 Assumes V BE = 0.7 V V GS =.5 V Advantages: can select bias point for optimum operation can select bias point close to middle of rails for maximum signal swing Disadvantages: to approximate AC short, need large capacitors that consume significant area

14 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 24 2 Direct coupling: share bias points across stages. Example, CDCC voltage buffer: 5.0 V 5.0 V 4.7 V 3.2 V 2.5 V I SUP I SUP2 Assumes V BE = 0.7 V V GS =.5 V Advantages: no capacitors: compact Disadvantages: bias point shared: constrains design bias shifts from stage to stage and can stray too far from center of range

15 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 25 Solution: use PMOS CD stage: 5.0 V 5.0 V I SUP 3.2 V.7 V 2.5 V I SUP2 Assumes V BE = 0.7 V =.5 V V GS Tradeoff: g m (PMOS)< g m (NMOS) higher R out In BiCMOS voltage amplifier: R out = g m4 β 4 (g m3 g mb3 )

16 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 26 2 Summary of DC shifts through amplifier stages: Amplifier Type Transistor Type NMOS PMOS npn pnp Common Source/ Common Emitter (CS/CE ) V V V V V V V V V V V V Common Gate/ Common Base (CG/CB) Common Drain/ Common Collector (CD/CC ) V V V V V V V V V V V V

17 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 27 Important difference in bias shift between stages in BJT and MOSFET amps: In BJT (for npn): V BE V BE,on rather independent of transistor size and current level. In MOSFET (for nmosfet): 2I D L V GS = V T µ n C ox W Can be engineered through bias current and transistor geometry. 5.0 V 5.0 V 4.7 V 3.2 V 2.5 V I SUP I SUP2 Assumes V BE = 0.7 V V GS =.5 V

18 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 28 Key conclusions To achieve amplifier design goals, several stages often needed. In multistage amplifiers, different stages used to accomplish different goals: voltage gain: commonsource, common emitter voltage buffer: commondrain, common collector current buffer: commongate, common base In multistage amplifiers must pay attention to interstage loading to avoid unnecessary losses. In directcoupled amplifiers, bias is shared between adjoining stages: must select compromise bias, must pay attention to bias shift from stage to stage.