EECS3611 Analog Integrated Circuit Design. Lecture 3. Current Source and Current Mirror

Transcription

1 EECS3611 Analog ntegrated Circuit Design Lecture 3 Current Source and Current Mirror

2 ntroduction Before any device can be used in any application, it has to be properly biased so that small signal AC parameters are well defined and the device is in proper regime of operation usually in saturation in analog applications. Current mirror method is a simple way to replicate well defined DC current sources in several independent circuit branches and is very popularly used in analog circuit design. Current source is also widely used as active load to improve amplifier gain. Current mirror is also a basic building block in current domain signal processing circuits.

3 Types of Current Source Current source provides current to external circuit. Current sink receives current from the external circuit. n this course, we refer both current source and sink as current source. -V plot of an ideal current source is shown. Current is not a function of the voltage across the current source.

4 Realization of Current Source D 0 V GS V D D D Realization of current source by MOSFET in saturation region by providing certain V GS. D is a function of V GS. Due to the channel length modulation effect of the MOSFET, the output resistance of the current is finite. There is a minimum output voltage for the MOSFET current source, V DSsat to keep the transistor in saturation region.

5 Basic Current Source Realization A simple current source circuit uses a MOS transistor biased with a voltage divider. This circuit is sensitive to power supply voltage V DD and the threshold voltage V TH. 1 W = L VDDR µ COX ( VTH (1 + λv R + R D DS 1 Note: (1 the threshold voltage may vary by 50 to 100 mv from wafer to wafer; ( both µ n and V TH exhibit temperature dependence. A good analog design should be insensitive to Process, supply Voltage and Temperature (PVT variation. V DD R 1 R M OUT = D

6 Conceptual Means of Copying Currents Use of a reference to generate various currents. Two identical MOS devices that have equal gate-source voltages and operate in saturation carry equal currents

7 Current Mirror (1 Replace R with a diode-connected transistor. For diode-connected transistor M1, we have: V D1 = V G1, and V TH1 >0. V DD OUT = D V DS1 = V GS1 > V GS1 V TH1 Hence, M1 is always in saturation region. Then: D1 W VDD V = 1 µ COX ( VGS1 VTH 1 (1 + λvgs1 = L R GS1 M1 N R OUT M For given D1, we can solve the cubic equation to find the gate voltage, and find the value of R. f the channel length modulation term is dropped, we can easily calculate the value of R as it is a quadratic equation. D1 W VDD V = 1 µ COX ( VGS1 VTH 1 = L R GS1

8 Current Mirror ( More generally, the input current can be replaced with a constant current source REF. The current mirror copies the current from the reference. The basic idea here is to set V GS of M to a fixed value by diode connected transistor M1. Hence, M now looks like a fixed DC current source and should have a very high resistance looking into the drain terminal, presenting characteristic of a typical current D1 source. M1 Since both transistors share the same V GS, same process and same temperature variations, the PVT effect will be cancelled off. This current source simply utilizes matched devices to cancel PVT effect. This is a usual way in analog circuit designs to deal with PVT. V DD REF OUT = D M

9 Current Mirror Analysis With accurate model that includes channel length modulation, we have: D1 D = 1 1 W L W L µ C ( V Since both transistors are fabricated with the same process steps, they have the same parameter µc OX and V TH. So the current is: OUT N = = D D1 1 = µ C OX OX ( V GS1 GS1 V V TH 1 TH ( W (1 + λv L OUT ( W (1 + λv L 1 N (1 + λv (1 + λv GS1 DS

10 Effect of Channel-Length Modulation Neglecting channel-length modulation, we can write Allows precise copying of the current with no dependence on process and temperature

11 General Concept of Current Mirror Basic current mirror concept: à V à Define current gain: α = Small-signal output resistance R O. OUT Minimum output voltage V Omin. N R O N OUT + V N Current to voltage conversion V GS Voltage to current conversion + - V OUT -

12 Current Mirrors More generally, we can connect more transistors to make several output currents. Every transistor shares the same V GS, hence same V OD. By designing different size of the transistor, we can mirror out different currents from the reference current. Here channel length modulation effect is neglected. ( W L n ( REF W Dn = L 1

13 Current Mirror Specifications Small-signal output resistance R O. Minimum output voltage V Omin. Current gain error definition: E = OUT OUT _ ideal OUT _ ideal Two types of error: systematic error: error caused by circuit structure. Random error: error caused by process variations. These two types of error are commonly seen in many analog circuits. A robust design is to minimize both systematic error and random error.

14 Current Mirror Analysis As V GS1 = V GS and assuming matched V TH1 = V TH OUT N = ( W (1 + λv L OUT ( W (1 + λv The output resistance of current source is the output resistance of M R O = 1 λ D Normally, larger L is used so that λ effect is reduced and the output resistance is higher. The current gain systematic error is: = L 1 1 λ OUT N N = D1 V N M1 OUT _ ideal = ( W L ( W L OUT = D 1 V OUT M N E OUT OUT _ ideal (1 + λvout λ = = 1 = ( VOUT VN λ( V (1 + λv (1 + λv OUT _ ideal N N OUT V N

15 Current Mirror Analysis-Gate Overdrive This current relationship will be true as long as M is in saturation. Clearly, this will happen when V O =V DS > V OD Gates of two transistors are connected: V GS = V GS1 so V GS V TH = V GS1 V TH1 as V TH1 = V TH à V OD1 =V OD Define the minimum output voltage: V Omin > V GS V TH = V OD Hence it is a benefit to have a low gate overdrive to increase the output swing. How much should the gate overdrive be? For same drain current, if the overdrive is small, transistor size will be very large, giving area penalty and speed penalty. Overdrive voltage is a trade-off between speed and minimum output swing. Typically, overdrive is selected between V.

16 Mismatch Matched device means all the devices are designed having matched parameters. Mismatch: parameter differences between matched devices Random statistical fluctuations Process bias Patten shift (Mask misalignment Diffusion interactions

17 Current Mirror Mismatch A current mirror with current ratio of two is designed. Assume V N =V OUT to eliminate the channel length modulation effect. Due to mismatch between M1 and M, the output current is not exactly two times of the input current. N OUT = N 3 ways to implement: A: W =W 1, L =0.5L 1 λ mismatch B: W =W 1, L =L 1 ΔW and ΔL mismatch OUT C: Two transistors in parallel, N = ( W L ( W OUT N L (1 + λ V 1 (1 + λ V 1 OUT N W + ΔW = L + ΔL W + ΔW L + ΔL N M1 M OUT = N W 3 =W =W 1, L 3 =L =L 1 Best solution OUT N = ( W + ΔW L + ΔL W + ΔW L + ΔL = M1 M M3

18 Eliminate the Systematic Error As we have seen, first simple current mirror output current ( OUT = D changes when the drain voltage of M changes. From model parameter λ = 0.05, the change in OUT for a 1V change in V D will be 5%, which is not acceptable in many analog applications. Can we do something about this? OUT OUT _ ideal (1 + λvout E = = 1 λ( V (1 + λv OUT _ ideal The key to eliminate the current gain systematic error is to make V OUT =V N in the simple current mirror. A straightforward way to achieve this would be having an extra MOSFET in series with M and fix the drain voltage of M to V N. This extra transistor is called cascode transistor. N OUT V N

19 Cascode Current Mirror f we choose V B = V GS4 + V X, then V Y = V B V GS4 à V Y = V X. f V X and V Y are the same, the channel length modulation term for both M1 and M will be the same. Hence, the effect is corrected. M4 now shields out from voltage variations at the output node as V Y is fixed by transistor M4 and does not depend on V OUT, eliminating the systematic error: channel length modulation mismatch. The cascode transistor M4 normally has the same size as M. This current mirror is called cascode current mirror. M1 V DD X REF V B OUT = D M4 Y M

20 Cascode Current Mirror How to generate the required V B? One simple way would be to create an exact replica of M4 in the left branch using a diode connected transistor M3 and utilize the gate voltage of M3 as V B. V DD Q REF V B OUT = D M3 X M1 M4 Y M

21 Cascode Current Mirror Transistor M1 and M3 will have the same overdrive V OD. M and M4 have the same overdrive. As mentioned before, M1 and M have the same overdrive. So all 4 transistors have the same overdrive V OD. Note all 4 transistors have the same threshold voltage V TH if body effect is ignored. Hence V X = V Y =V TH + V OD V GS3 = V OD + V TH as M1 and M3 carry the same current. V G3 = V GS3 + V X = V TH + V OD ignoring body effect. Hence V G4 = V TH + V OD This should also be the case with body effect only V TH will become V TH1 + V TH3.

22 Cascode Current Mirror-Output Resistance The output resistance of this current mirror can be found using low frequency small signal equivalent circuit. A small signal is applied at the drain of M4 to find R O. The method as the same in EE005 where a test voltage v t is applied at the point where effective resistance is to be found and then current through the test source, it is calculated so that R O =v t /i t. We will neglect g mb. Only modified result will be given later. G4 D4 i t g m4 v gs4 r o4 v t G S4 g m v gs r o S

23 Cascode Current Mirror-Output Resistance Since the gate voltages of M and M4 are fixed by M1and M3 and there is no variable voltage at M1 and M3, the gates of M and M4 are AC ground. Clearly, v gs =0, v gs4 = - i t r o i t t = v t i (1 + g v r o4 s4 m4 ro = g i m4 t v t r o itr r o4 o G4 G g m4 v gs4 g m v gs D4 r o4 S4 r o i t v t Hence, R O = output resistance of single cascode current mirror S v t R O = = ro 4 ( 1+ gm4ro + ro it

24 Cascode Current Mirror-Output Resistance This type of result is quite generally applicable in the sense that due to presence of M below M4, the output resistance seen at the drain of M4 is magnified by a factor ( 1 + g m4 r o. We will use this result later whenever such a configuration appears. Typically, g m4 r 0 >> 1 and r 0 = r 04 = r 0 as M and M4 carry the same current. f body effect is included: Features of Cascode current mirror: R = m4 o No current gain systematic error. Higher output resistance. Higher minimum output voltage. O g O r R = + ( gm4 gmb ro

25 Triple Cascode Current Mirror A variation of this circuit known as triple Cascode current mirror where a device is added on the left and right is also possible. R O in this case will be { } ( (1 ] (1 [ 1 o m o o m m o o m o o o m o m o O r g r r g g r r g r r r g r g r R = = OUT V DD M M4 X Y Q REF M1 M3 M6 M5 Z

26 Minimum Output Voltage Returning to the 4 MOSFET circuit, if body effect is present, V TH and V TH4 will be different and voltages will alter, but concept still works. For the concept to work, M and M4 both must be in saturation, i.e. V X =V Y =V TH + V OD and M4 must be in saturation region: V DS4 > V OD So V OUT >V T + V OD Hence V OUT needs to be quite high, over 1V, for proper operation. This could be a problem for low voltage design and will certainly reduce output swing. A level shift follower is introduced and this voltage requirement can be reduced to V OD. REF M3 X M1 V B V OUT OUT = D M4 Y M

27 Low Voltage Cascode Current Source 1 n cascode current mirror, V X =V Y and V X =V TH +V OD à V Omin =V TH +V OD f V X V Y à Low output voltage, high swing Adding a voltage shifter V TH, now V Y =V X -V TH =V OD V DD V DD REF REF V B OUT V T OUT M3 M4 M3 + - M4 X M1 Y M X M1 Y M

28 Low Voltage Cascode Current Source 1 All transistors have the same overdrive except M3. V X =V TH +V OD Since W3=1/4W1, REF 1 1 W 4 L = µ COX ( VGS 3 VTH = µ 1 C OX W L V OD V GS3 =V TH +V OD à V G3 =V X +V GS3 =V TH +3V OD V G4 =V TH +V OD à V Y =V OD V DD Q V Omin =V OD REF OUT V TH +3V OD M3 M5 M4 W 3 = 1 / 4 W 1 M1 V X VTH +V OD M6 V Y =V OD M

29 Low Voltage Cascode Current Source 1 The minimum output voltage is now V OD. The output resistance remains the same as the Cascode current mirror. However, since V X =V Y is no longer valid, the current gain systematic error is not zero. E λ( V V Y X = λv TH This drawback can be eliminated by another circuits, i.e. low voltage Cascode current mirror circuit.

30 Low Voltage Cascode Current Source All the transistors have the same overdrive. Set V B =V TH +V OD V DD V X =V Y =V B -(V TH +V OD =V OD Then the minimum output voltage is: REF V B OUT V OUT =V OD And since V X =V Y à no current gain systematic error. Design all transistors overdrive smaller than its V TH. Since V DS3 =V GS1 -V DS1 =V TH >V OD à M3 at saturation region. All transistors are at saturation region. M3 X M1 M4 Y M

31 Low Voltage Cascode Current Source The low voltage cascade current source has: High output resistance Low output voltage: V DD V OUT =V OD No current gain systematic error. How to generate V B =V TH +V OD? Two ways: Assuming same L for all transistors, Since W B =1/4W 1 and same current 1 1 W 1 REF = µ COX ( VB VTH = µ C 4 L OX W L V OD REF W B = 1 / 4 W 1 MB V B V B =V GS1 =V TH +V OD

32 Low Voltage Cascode Current Source Another way to generate V B : All transistor have the same overdrive except M6. V DS6 =V GS6 V GS7 à V GS6 =V DS6 + V GS7 Since V GS7 >V TH, V DS6 <V GS6 V TH à linear region V GS6 V TH =V DS6 + V GS7 V TH =V DS6 + V OD V DD 1 W D6 = µ C 3 L OX 1 W D7 = µ C L OX ( V V GS 6 OD V TH V DS 6 1 V DS 6 + V D6 = D7 and VGS 6 VTH = VDS 6 OD REF M7 W 6 = 1 / 3 W M6 V B Solve the equations: V DS6 =V OD V B =V GS5 +V DS6 =V TH +V OD M5

33 Low Voltage Cascode Current Source V DD V DD V DD V DD REF REF OUT REF REF OUT V B M7 V B M3 M4 W 6 = 1 / 3 W M6 M3 M4 MB W B = 1 / 4 W 1 X M1 Y M M5 X M1 Y M Full schematic of two types of low voltage Cascode current mirror.

34 Wilson Current Mirror Transistor M1 and M have the same overdrive: Use feedback to stabilize the output current. V OUT à OUT à V Y à V X à OUT High output resistance: g m r o OUT N = ( W (1 + λv L Y ( W (1 + λv Minimum output voltage: V TH +V OD Since V X V Y, the current gain systematic error is not zero. L E λ( V Y VX 1 X REF X M1 V DD V OUT OUT M4 Y M

35 Wilson Current Mirror By adding M3, V X =V Y, the current gain systematic error is zero. High output resistance: g m r o Minimum output voltage: V TH +V OD Not good for low-voltage design V DD REF OUT M3 X M1 M4 Y M

36 Current Mirror Summary Basic Current Mirror ncrease output resistance Cascode Feedback Cascode Current Mirror Wilson Current Mirror Reduce minimum output voltage Low Voltage Cascode Current Mirror