Lecture 34: Designing amplifiers, biasing, frequency response. Context

Transcription

1 Lecture 34: Designing amplifiers, biasing, frequency response Prof J. S. Smith Context We will figure out more of the design parameters for the amplifier we looked at in the last lecture, and then we will do a review of the approximate frequency analysis of circuits which have a single dominant pole.

2 Reading Chapter 9, multi-stage amplifiers. The frequency analysis is in the first section of chapter 0, but we won t go farther into chapter 0 for a while. The Lectures on Wednesday and Friday will be given by Joe and Jason, respectively. They will be doing several example problems. Lecture Outline Example : Cascode Amp Design Example 2; CS NMOS->CS PMOS Review of frequency analysis (with a dominant pole) 2

3 Amplifier Schematic Note that the backgate connection for M 2 is not specified: ignore g mb Complete Amplifier Schematic Bias voltages derived from transistors under similar operating conditions to the transistors they supply Goals: g m ms, R out 0 MΩ Cascode current source For high r oc CG output CS input, with low voltage gain 3

4 Current Supply Design High impedance current source means all of the small signal current goes to the load resistance, giving more SS voltage gain Output resistance goal requires large r oc for high gain so we used a cascode current source Totem Pole Voltage Supply DC voltages must be set for the cascode current supply transistors M 3 and M 4, as well as the gate of M 2. M 2B supplies the Bias quiescent voltage For the CG stage 4

5 Miller Capacitance of Input Stage Find the Miller capacitance for C gd C gd Input resistance to common-gate second stage is low gain across C gd is small. Two-Port Model with Capacitors C ( A ) C gd Miller capacitance: M vc gd AvC dg g g m m2 5

6 Schematic Goals: g m ms, R out 0 MΩ Device Sizes M : select (W/L) 200/2 to meet specified g m ms find V BIAS.2 V Cascode current supply devices: select V SG.5 V (W/L) 4 (W/L) 4B (W/L) 3 (W/L) 3B 64/2 6

7 Device Sizes M 2 : select (W/L) 2 50/2 to meet specified R out 0 MΩ find V GS2.4 V Match M 2 with diode-connected device M 2B. Assuming perfect matching and zero input voltage, what is V OUT? Output (Voltage) Swing Maximum V OUT Minimum V OUT 7

8 Two-Port Model Find output resistance R out λ n (/20) V -, λ n (/50) V - at L 2 µm r on (00 µa / 20 V - ) kω, r op 500 kω out g g 2I D2 V V 2(00µ A).4V V m 2 500µ S GS 2 Tn 2( I D3) V + V 2(00µ A).5V V m 3 400µ S SG3 Tp ( + g R ) r ( + g R ) r ( g r ) R r + oc ro 2 m2 S 2 o3 m3 S 3 o2 m2 o Voltage Transfer Curve Open-circuit voltage gain: A v v out / v in - g m R out v OUT , dv dv out in Q v IN 8

9 Multistage Amplifier Design Example Start with basic two-stage transconductance amplifier: Why do this combination? Quiescent level shifts CS NMOS (typical) PMOS (typical) CG CD Source follower (known shift) (known shift) 9

10 CS CS Amplifier Direct DC connection: use NMOS then PMOS Current Supply Design Assume that the reference is a sink set by a resistor Must mirror the reference current and generate a sink for i SUP 2 0

11 Use Basic Current Supplies Complete Amplifier Topology What s missing? The device dimensions, the bias voltage and reference resistor

12 DC Bias: Find Operating Points Find V BIAS such that V OUT 0 V Device parameters: µ 50 µa/v2 µ 25 µa/v 2 n C ox V Tn V pc ox V Tp - V λ n 0.05 V - λ p 0.05 V - Device dimensions (for lecture design): (W/L) n 50/2 (W/L) p 80/2 Finding R REF V + Require I REF - I D3 50 µa M 3 V SG3 V Tp + 2I D3 µ C ( W / L) p ox 3 R REF 2 50µ A 4 V SG 3 ( ) V V 25µ A(80 / 2) 40 V - I A + [ V V ] [ V ] SG3 REF 50µ Rref [ ] [ 2.5] 50µ A Rref 74kΩ R ref 2

13 DC Operating Point I REF 50 µa V BIAS V V 2I D + µ C ( W / L) 00µ A 2 50( µ A/ V )(50 / 2) GS tn + n ox 9 V 7 Small-Signal Device Parameters Transistors M and M 2 g m 350 µs r o 400 kω g m2 35 µs r o2 400 kω Current supplies i SUP and i SUP2 r oc r o4 400 kω r oc2 r o6 400 kω 3

14 Two-Port Model Find G m i out / v in Output Voltage Swing Transistors M 2 and M 6 will limit the output swing 4

15 Limits to Output Voltage M 6 will leave saturation when v OUT drops to: OUT, MIN V v + V DS 6, sat I µ C n ox D6 v OUT,MIN V M 2 will leave saturation when v OUT rises to: OUT, MAX V + v V SD2, sat 2.5 v OUT,MAX V What about M 4? 2( I µ C p ox ( W / L) 6 D2 ) ( W / L) 2 Output Current Swing Load resistor: pick R L 25 kω Output current: i v / R OUT OUT L i OUT i OUT i ( i ) D6 D2 Limits: asymmetrical v OUT M 2 : can increase - i D2 M 6 : can t increase i D6 5

16 Output Current Limits Positive output current (negative v OUT ) ( 0 ) 50 A vout, MIN RL i / v OUT, MAX id6 µ (50µ A)(25kΩ). V (less negative than limit set by saturation of M 6 ) OUT, MIN 25 Negative output current (positive v OUT ) No limit on current from M 2, so voltage swing sets current limit i OUT, MIN v OUT, MAX / R (2.8V / 25kΩ) 87.2µ A L Transfer Curves (for R L 25 kω) Loaded voltage gain v out /v in (g m R out )(g m2 R out R L ) 490 Loaded transconductance i out /v in (-g m R out )(g m2 )(R out /(R out + R L ) -9.5 ms v OUT 2 i OUT [µa] v IN v IN 6

17 Review: Frequency Resp of Multistage Amplifiers We have a systematic technique to study amplifier performance (derive transfer function, study poles/zeros/bode pltos). In most cases, the systematic approach is too cumbersome. We have a good qualitative understanding of circuit performance (e.g., CS suffers from Miller effect, CD andd CG are wideband stages ) Open Circuit Time Constants: Analytical technique is capable of estimating only the dominant (lowest) pole for a restricted class of amplifiers. The Special Case The transfer function can have no zeroes and must have a dominant pole ω << ω 2, ω 3,, ω n H ( jω) H o 2 3 ( + jωb + ( jω) b + ( jω) b...) Factor denominator: H ( jω) H ( + jω / ω )( + jω / ω )...( jω / ω ) o 2 + n 7

18 Approximating the Transfer Function Multiply out denominator: H ( jω) H ( + jω / ω )( + jω / ω )...( jω / ω ) o 2 + H o + jω ω ω2 ωn Since ω << ω 2, ω 3,, ω n n b + ω ω ω n ω How to Find b? See P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits (EE 40) for derivation Result: b is the sum of open-circuit time constants τ i which can be found by considering each capacitor C i in the amplifier separately and finding the Thévenin resistance R Ti of the network from the capacitor s point of view τ i R Ti C i b n R i TiCi ω n i R Ti C i 8

19 Finding the Thévenin Resistance. Open-circuit all capacitors (i.e.; remove them) 2. For capacitor C i, find the resistance R Ti across its terminals with all independent sources removed (voltages shorted, currents opened) might need to apply a test voltage and find the current in some cases. Insight for design: the bandwidth of the amplifier will be limited by the capacitor that contributes the largest τ i R Ti C i not necessarily the largest C i 9