CHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS

Transcription

1 CHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS Chapter Outline 8.1 The CMOS Differential Pair 8. Small-Signal Operations of the MOS Differential Pair 8.3 The BJT Differential Pair 8.4 Other Non-ideal Characteristics of the Differential Amplifier 8.5 The Differential Amplifier with Active Load NTUEE Electronics L.H. Lu 8-1

2 8.1 The MOS Differential Pair The differential pair (differential amplifier) configuration Widely used building block in analog integrated circuit design Performance depends critically on the matching of the devices Utilizes more components than single-ended circuits Well suited for IC fabrication Advantages of using differential pair Less sensitive to noise and interference than single-ended circuits Bias is provided without the need for bypass and coupling capacitors The CMOS differential pair The design philosophy for ICs is different from that of discrete-component circuits Two matched transistors are used Identical device parameters for Q 1 and Q (k n, V t, and even layout) The source terminals are connected together Biased by a constant-current source Resistive loads are used for illustration Differential input at the gate terminals Differential output at the drain terminals NTUEE Electronics L.H. Lu 8-

3 Operation with a common-mode input voltage Circuit analysis Both inputs are connected to a common-mode voltage V CM The differential pair Q 1 and Q are in saturation The current divides equally due to device matching I = 1 k W L (V V ) V = V V = V I k (W/L) V V = I k (W/L) V = V = V I R Output does not respond to V CM V OV is defined at I D1 = I D = I/ Input common-mode range (ICMR): The range of V CM for proper operation Both Q 1 and Q should be in saturation V CM,max = V DD R D I/+V t V CM,min = -V SS +V CS (headroom for current source)+v GS NTUEE Electronics L.H. Lu 8-3

4 Operation with a differential input voltage A difference voltage v id exists between the input terminals The current of Q 1 is different from that of Q as v GS1 v GS The overall current I remains unchanged The value of v id at which the entire bias current I is steered into Q 1 is = V + = V I k (W/L) = V + V, = V The current I can be steered from one transistor to the other by varying v id in the range V < < V Differential pair as a linear amplifier Keep the differential input voltage v id small The currents of the transistor pair become I/ I I is linearly proportional to v id for small-signal operation A differential output voltage is taken between the two drains as IR D NTUEE Electronics L.H. Lu 8-4

5 Large-signal operation = = i k (W/L) i k (W/L) I = i + i Drain currents of the differential pair i = I + i = I I V I V 1 V 1 V Normalized transfer characteristics Nonlinear transfer characteristics The overdrive voltage V OV is calculated as i D1 = i D = I / Small-signal approximation Linear I-V characteristics for small v id i I + I V i I I V Transconductance: G m i D /v id = I/V OV NTUEE Electronics L.H. Lu 8-5

6 Linearity of the differential pair The linearity of the differential pair can be increased by increasing the overdrive voltage V OV Linearity-transconductance trade-off: Smaller aspect ratio (W/L) of Q 1 and Q at fixed bias current I Resulting in smaller transconductance and smaller gain Linearity-power trand-off: Larger bias current I with fixed aspect ratio Resulting in larger transconductance and gain at the cost of higher power dissipation NTUEE Electronics L.H. Lu 8-6

7 8. Small-Signal Operation of the MOS Differential Pair Small-signal analysis technique for differential amplifiers The ac inputs are defined as v g1 and v g at the differential pair based on the small-signal model It can also be treated as superposition of differential (v id ) and common-mode (v icm ) voltages The circuit analysis can be divided into differential and common-mode operations ac equivalent circuit V D + v o1 V D + v o1 v o1 v o1 V CM + v g1 V CM + v g1 v g1 v g Differential gain The differential input signal (v id ) is applied in a complementary (or balanced) manner Single-ended outputs (v o1 and v o ): output taken between one of the drains and ground Differential output (v od ): output taken between the two drains Differential gain is defined as the ratio of v od to v id : A = = = + NTUEE Electronics L.H. Lu 8-7

8 Small-signal circuit analysis (simplified model): i = 1/g + 1/g v = 0 Differential gain: = g = ir = g R = ir = g R A = = g v R Small-signal circuit analysis (with r o and R SS ): i i = v = 0V g g i g g v + v + g r v + v = 0 r v + v + = 0 r R g v = 0 v + v + = 0 r R Differential gain: = = g / 1/r + 1/R A = = g v R r NTUEE Electronics L.H. Lu 8-8 r v R r

9 The differential half-circuit Virtual ground: Differential operation for a symmetrical circuit The voltage at the nodes on the symmetrical axis (the joint source connection) must be zero A signal ground is established at the source terminals without a large bypass capacitor The differential half-circuit analysis: A technique useful to simplify the ac analysis of fully differential circuits All the nodes on symmetric line are considered ac ground The complete circuit can typically be separated into two half-circuits Performance of a symmetrical differential circuit can be evaluated by half-circuit analysis A = g (R r ) g r NTUEE Electronics L.H. Lu 8-9

10 The differential amplifier with current-source load A = g (r r ) A = g (R R g (g r r g r r ) NTUEE Electronics L.H. Lu 8-10

11 Example for differential half-circuit analysis A g = R 1 + g R R NTUEE Electronics L.H. Lu 8-11

12 Common-mode gain of a differential pair A differential pair with ideal current source The output resistance (R SS ) is infinite Drain currents of Q 1 and Q do not change with the input common-mode voltage V CM The single-ended outputs remain unchanged The differential output voltage and common-mode gain are zero A differential pair with a practical current source The output resistance (R SS ) is finite Drain currents of Q 1 and Q change simultaneously with V CM The singled-ended outputs vary with V CM The differential output voltage and common-mode gain are zero The differential pair rejects common-mode signals regardless the value of R SS, resulting in zero differential output voltage = i 1 + ir g i = 1 + R g R R = = v 1 v g + R R = = 0 NTUEE Electronics L.H. Lu 8-1

13 Common-mode half-circuit The common-mode half-circuit analysis: Circuit analysis technique for symmetrical circuit with common-mode operation The symmetrical points are equal potential No current flowing across the symmetrical line and can be treated as open The complete circuit can be typically divided into two half-circuits The performance can be evaluated by common-mode half-circuit to simplify the analysis = = g R v 1 + g R R v R NTUEE Electronics L.H. Lu 8-13

14 Complete small-signal analysis: AC equivalent circuit: Differential operation: Common-mode operation: v g1 v g R SS R SS R SS = = + Overall response: = V _ g R = V _ + g R R R R R = g R = g R A = = g R R R R R A = = 0 NTUEE Electronics L.H. Lu 8-14

15 Device mismatch in the differential pair Mismatch between Q 1 and Q or R D1 and R D leads to non-ideal effects Assume R D1 = R D + R D and R D = R D for resistance mismatch Operation with a differential input voltage v id : = 1 g i + R (i + i ) = 1 g i + R (i + i ) R D + R D Q 1 Q R D i 1 i v id / -v id / i = i = g = = g R 1 + R R i 1 +i A = g R 1 + R R g R The mismatch R /R is generally small in modern integrated circuit technology The differential gain A d does not change significantly due to mismatch Analysis of device mismatch is typically focused on non-ideal effects in common-mode operation NTUEE Electronics L.H. Lu 8-15

16 Effect of resistance mismatch Common-mode gain: = 1 i g + R (i + i ) = 1 i g + R (i + i ) R D + R D R D i = i = 1 g + R = = R 1 g + R R R v icm Q 1 Q i 1 i v icm A R R R R i 1 +i For a current source with finite R SS, mismatch in R D causes a finite common-mode gain A cm Common-mode rejection ratio (CMRR): CMRR is defined as the ratio of differential-mode gain and the common-mode gain A measure of the effectiveness of the differential pair in rejecting common-mode interference Is given by CMRR = A d /A cm and usually expressed in decibels CMRR (db) = 0log A d /A cm CMRR of the differential amplifier with respect to the resistance mismatch CMRR = A A = g R R /R Utilizes a bias current source with a high output resistance High degree of matching between the drain resistance NTUEE Electronics L.H. Lu 8-16

17 Effect of transconductance mismatch Mismatch exists between Q 1 and Q R D R D g = g + g g = g g Common-mode gain: = 1 g i + R i + i = 1 g i + R i + i v icm Q 1 Q i 1 i v icm g R = i R = v 1 + g + g R i 1 +i g R = i R = v 1 + g + g R = = g R 1 + g R A R g R g Common-mode rejection ratio: CMRR A A g R g /g NTUEE Electronics L.H. Lu 8-17

18 Circuit configuration 8.3 The BJT Differential Pair Two identical BJT transistors Q 1 and Q with emitters jointed together Biased with a current source Input common-mode range Allowable range of V CM for Q 1 and Q in active mode V V + 0.5V = V αr I + 0.5V V = V + V + V Common-mode operation Common-mode input voltage V CM for v B1 and v B Single-ended output voltage: = V αr I/ = V αr I/ Differential output voltage: = = 0 Finite output resistance of the current source Single-ended output change with V CM Differential output is still zero NTUEE Electronics L.H. Lu 8-18

19 Large-signal operation Transfer characteristics i i = I α e ( )/ I α e ( )/ = e ( )/ i + i = I Normalized characteristics i = i = The bias current is divided equally for v id = 0 I 1 + exp( /V ) I 1 + exp( /V ) Unequal current through Q 1 and Q for v id 0 A relatively small v id for complete current switching The linearity can be improved by emitter degeneration R e Transconductance and gain decrease due to emitter degeneration NTUEE Electronics L.H. Lu 8-19

20 Small-signal operation Small-signal current Differential pair: i c = g m v id / Differential pair with emitter degeneration : i c = v id /(r e +R e ) g m v id /(1+g m R e ) Input differential resistance Differential pair: R id v id /i b = r Differential pair with emitter degeneration: R id = ( +1)(r e +R e ) [R e +r (1+g m R e )] NTUEE Electronics L.H. Lu 8-0

21 Differential gain Differential pair: A d v od /v id = g m R C Differential pair with emitter degeneration: A d = R C /(r e +R e ) g m R C /(1+g m R e ) The differential amplifier can also be fed in a single-ended fashion Equivalent circuit model NTUEE Electronics L.H. Lu 8-1

22 Common-mode gain and CMRR Differential pair with device matching: = = αr v r + R = = 0 Differential pair with resistance mismatch: = i r + i + i R = i r + (i + i )R i = i = / r + R = αr v r + R = α(r + R ) v r + R = = α R v r + R i e1 R D i e R D + R D A = α R r + R R R R R i e1 i e CMRR = g R R /R High output resistance is desirable for current source Resistance mismatch for the load should be minimized i e1 +i e NTUEE Electronics L.H. Lu 8-

23 8.4 Other Non-ideal Characteristics of the Differential Amplifier Input offset voltage of the MOS differential pair Output dc offset voltage: the finite output voltage with both input grounded Input offset voltage (V OS ): the input referred offset voltage as the output offset divided by gain Output voltage becomes zero if V OS is applied between the inputs Its polarity can not be predetermined Factors contribute to the dc offset voltage: Mismatch in load resistance R D Mismatch in aspect ratio (W/L) Mismatch in threshold voltage V t NTUEE Electronics L.H. Lu 8-3

24 Input offset voltage due to load resistance mismatch R = R + R / R = R R / Input offset voltage due to aspect ratio mismatch W L = W L + 1 W L W L = W L 1 W L Input offset voltage due to threshold voltage mismatch V = V + V V = V V Input offset voltage: V = V = I R = V g R g R The three mismatch factors are uncorrelated V = V R R I = I 1 + (W/L) (W/L) I = I 1 (W/L) (W/L) I = k V V V 1 (V V ) I = k V V V 1 + (V V ) + V (W/L) (W/L) To minimize the input offset voltage Decrease overdrive voltage V OV Minimize the device mismatch ratio + V R R V = R (I I ) g R I 1 V V V I 1 + V V V = V (W/L) (W/L) V = R (I I ) g R = V NTUEE Electronics L.H. Lu 8-4

25 Input offset voltage of the bipolar differential pair Factors contribute to offset voltage Mismatch in load resistance R C Mismatch in junction area A E Mismatch in Input offset voltage due to load resistance mismatch R = R + R / R = R R / Input offset voltage due to emitter area mismatch I = I + I I = I I Input offset voltage: The factors are uncorrelated V = V R R I = I I = I + I I V = α(i/) R g R 1 + I I 1 I I = V R R V = α I I R I = V I g R I The offset voltage can be minimized by reducing the device mismatch ratios The input offset voltage for BJT (proportional to V T ) is typically smaller than its MOS counterpart (proportional to V OV ) NTUEE Electronics L.H. Lu 8-5

26 Input bias current and offset currents of the bipolar differential pair Input bias current: Finite bias currents are required at the input terminals of BJT differential pair The input bias currents are simply the base current of the BJT transistors I = I = Input offset current: Offset in the input bias currents due to device mismatch Mostly from the mismatch in β = β + β β = β β I (β + 1) I = I 1 β β/ I 1 β + 1 I = I 1 β + 1 β/ I 1 β β β 1 + β β Comparison for MOS and bipolar differential pair Bipolar differential pair typically has smaller input offset voltage Bipolar differential pair suffers from input offset current I = I β (β + 1) β = I β β NTUEE Electronics L.H. Lu 8-6

27 8.5 The Differential Amplifier with Active Load Differential to single-ended conversion Differential pair with differential output Improved CMRR: suppress the influence of the common-mode interference Higher voltage gain: gain is increased by a factor or Differential pair with single-ended output Certain applications require single-ended output A resistive load differential pair can simply provide the differential to single-ended conversion The active-loaded MOS differential pair Utilizes a current mirror (Q 3 and Q 4 ) as the active load Provides single-ended output for the differential pair NTUEE Electronics L.H. Lu 8-7

28 Basic circuit operation Quiescent point: Perfect matching case: Bias current is equally divided for Q 1 and Q The current of Q 1 also flows through Q 3 Current of Q 3 is mirrored to Q 4 All currents are identical (I D1 = I D = I D3 = I D4 = I/) The currents of Q and Q 4 balance out Zero output current to the following stage Quiescent output voltage = V DD V SG3 Input common-mode range (ICMR): ICMR max = V DD V SG3 + V tn ICMR min = V SS + V CS + V GS1 Mismatch in the devices: Nonzero net current at the output node The current flows into the output resistances of Q and Q 4 The output voltage deviates from V DD V SG3 Applying differential input voltage: A difference current between Q 1 and Q The net difference current exists at the output NTUEE Electronics L.H. Lu 8-8

29 Voltage gain of the active-loaded MOS differential pair Transconductance: G m = g m1 The transconductance is evaluated by output current with v 0 = 0 V The drain of Q 3 is considered a low-impedance node and the voltage is relatively low v g3 0 V With v g3 v 0 = 0 V, differential half circuit applies for Q 1 and Q and source voltage is 0 V = g 1 r g r g g i = g + g = g G g = g NTUEE Electronics L.H. Lu 8-9 g g + g g

30 Output resistance: R o r o r o4 R = r + R g r = 1 g + 1/g g r 1 g R = R + r + g r R == 1 g + r + r g r i = v R i = i + i + v r = v R + v r R = r r Differential gain: A d = G m R o = g m1 (r o r o4 ) g m r o / Circuit model for MOS differential amplifier with a current-mirror load NTUEE Electronics L.H. Lu 8-30

31 Common-mode gain and CMRR The active-loaded CMOS differential pair has a high CMRR even with a single-ended output Common-mode half-circuit is not applicable as the circuit is not symmetrical Q 1 and Q can be treated as two separated CS transistors with source degeneration NTUEE Electronics L.H. Lu 8-31

32 Common-mode gain: A cm 1/(g m3 R SS ) v = i = Common-mode rejection ratio: CMRR = g m1 (r o r o4 )(g m3 R SS ) R r R r + 1/g R G i = 1 R R = R + r + g r (R ) R = R + r + g r (R ) = G R r 1 g i = g = g = g G R r i = G 1 g R r v = i + i R r = 1 g R R r A v r 1 1 R 1 + g r g R 1 g NTUEE Electronics L.H. Lu 8-3

33 The bipolar differential pair with active load Circuit schematic: Bipolar differential pair Q 1 and Q Bipolar current mirror Q 3 and Q 4 as active load Constant current source for dc bias The bias current is equally divided for Q 1 and Q Input resistance: R id = r 1 Transconductance: G m g m1 Transconductance is evaluated by output current with v o = 0V Collector of Q 3 is low-impedance node with v b3 ov Differential half circuit applies for Q 1 and Q with emitter voltage = 0V = g (r r r r ) g r g = g g r i = g g = g + g g r G i = 1 g + g g r g NTUEE Electronics L.H. Lu 8-33

34 Output resistance (R o ): Differential gain: Common-mode gain: CMRR: R r 1 + g r r r 1 + g r r i = v R = v r i = i + v r = v r + v r R = r r A v = G R = g (r r ) 1 g r i i R = i 1 g r r r v = r g + i A CMRR v = r 1 g R r g r r 1 r R A A /r r g + /r β R = g (r r ) β R r 1 β g R NTUEE Electronics L.H. Lu 8-34

35 Systematic input offset voltage Difference current between Q 3 and Q 4 due to finite Net current at output for both input terminals grounded Input offset voltage to eliminate the output current This offset has nothing to do with device mismatch I 1 = I 1 + /β I/ I = α 1 + /β i = α I /β = α I V = i G = V β /β 1 + /β α I β Improved current mirror can be used to reduce the systematic input offset NTUEE Electronics L.H. Lu 8-35