UNIT-1 Bipolar Junction Transistors. Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press

Transcription

1 UNIT-1 Bipolar Junction Transistors Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press

2 Figure 6.1 A simplified structure of the npn transistor. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.

3 Figure 6.2 A simplified structure of the pnp transistor. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.

4 Figure 6.7 Cross-section of an npn BJT. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.

5 Schematic diagram of integrated-circuit BJT From Muller and Kamins, Device Electronics for Integrated Circuits, 2ed., Wiley Isolation keeps neighboring BJTs from talking to one another. An epitaxial layer is a very pure, crystalline layer of semiconductor that has been added by one of several different deposition techniques. SiO 2 is an insulator; in this case, it serves to protect the surfaces of the semiconductor. The notation p and n refers to the type of semiconductor (dominant carriers are holes (p) or electrons (n)). Superscripts + and - on n or p indicate very heavy doping (high conductivity) or very light doping (low conductivity), respectively.

6 Direction of electron flow during forward-active biasing

7 Figure 6.3 Current flow in an npn transistor biased to operate in the active mode. (Reverse current components due to drift of thermally generated minority carriers are not shown.) Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.

8 Figure 6.10 Current flow in a pnp transistor biased to operate in the active mode. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.

9 Circuit Symbols The arrow is at the emitter, and it points to the n- type region. In the npn, the emitter is n type; in the pnp, the base is n-type. + v CB - + v BE - n p n + v CE -

10 DC (large signal) model for active region Hambley 2ed., Prentice Hall 2000

11 DC (large signal) model for saturation region Hambley 2ed., Prentice Hall 2000

12 DC (large signal) model for cutoff region Hambley 2ed., Prentice Hall 2000

13 BJT Characteristic Curves: along the v CE axis a) For any i B : v CE = 0 means CB junction is in forward bias because v CB = -0.7 V. There is no net current flow, so i C ~ 0. b) An increase in v CE causes the CB junction to be less and less forward biased, and finally reverse-biased. When fully reversebiased, we are in forward-active mode and i C is ~ constant. + v CB - + v BE - n p n + v CE - active mode Figure 5.27 Circuit whose operation is to be analyzed graphically. a) b) v CE = v CB + v BE = v CB V if BE junction is on. saturation cut-off Figure 5.29 Graphical construction for determining the dc collector current I C and the collector-to-emitter voltage V CE in the circuit of Fig

14 BJT Characteristic Curves: along the load line c) active mode v CB - + b) a) saturation cut-off v CE = v CB + v BE Follow the load line, along the direction shown by the arrow... a) V CC is positive, reverse-biasing the BC junction if i C is small. If i B = i C = 0, v CE = V CC cutoff b) Next we put the BE junction in forward bias, so v BE ~ 0.6 V. As i B increases, i C increases, lowering v CE ; we are in active mode: BE junction forward biased and CB junction reverse biased. c) As i B increases further, i C increases and v CE decreases to the point that the BC junction becomes forward biased. Now we are in saturation: BE junction forward bias and CB junction forward bias. In saturation, v CE is typically ~ 0.2 V, which means v CB = -0.4 V (so CB is reverse-biased) if v BE is 0.6 V.

15 If we bias the BJT in the Active Mode, we can use it as an amplifier. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.

16 When used as a switch, the BJT is either in Cutoff (v o high) or Saturation (v o low) Figure 5.32 A simple circuit used to illustrate the different modes of operation of the BJT.

17 To see how amplification works, let s look at the Common Emitter KVL around input loop (dc only): VBB ibrb vbe 0 i B V R BB B v R BE B Figure 5.27 Circuit whose operation is to be analyzed graphically. We can think of either i B or v BE as an input, so the graph shows the input characteristics for this device. Figure 5.28 Graphical construction for the determination of the dc base current in the circuit of Fig

18 We are looking here at i C vs. v CE, because we can think of these as the output current and output voltage. active mode KVL around output loop (dc only): VCC ic RC vce i C V R C C v R CE C 0 saturation cut-off Figure 5.29 Graphical construction for determining the dc collector current I C and the collector-to-emitter voltage V CE in the circuit of Fig

19 7. Bottom Line: Current Gain: i C >> i B 6. and a change in collector current i c. 3. which changes the base current i b. 4. The base current change shows up here 2. changes the BE voltage v be 1. Applying a signal v i 5. with a corresponding change in CE voltage v ce Figure 5.30 Graphical determination of the signal components v be, i b, i c, and v ce when a signal component v i is superimposed on the dc voltage V BB (see Fig. 5.27).

20 Base-Width Narrowing: the Early Effect Robert F. Pierret, Semiconductor Device Fundamentals, Prentice Hall, 1996 The intersection of the i C -v CE curves is known as the Early Voltage after James Early.

21 i c Modeling the Early Effect + v ce - With a resistance in parallel with the current source, i c is the sum of g m v be and v ce /r o, which more accurately predicts the i c - v ce behavior. i c + v ce - Figure 6.47 The hybrid- small-signal model, in its two versions, with the resistance r o included. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.

22 Finding ac model parameters from the characteristic curves Output Resistance r o We have already seen that the slope of the i C v CE curve gives r o. slope = 1/r

23 Current Gain We defined current gain as = I B /I C when we looked at the dc BJT. For ac, gain is = i C / i B.

24 i B slope = 1/r Base Resistance r i b I B If we look at the change in i b with v be (ac component of the graph to the left) we will find the inverse of r. Relationship to dc parameters r v i be b V I T B

25 slope = g m Transconductance g m If we look at the change in i c with v be (ac component of the graph to the left) we will find g m. Relationship to dc parameters g m i v c be I V C T

26 There are three terminals; since we need two for input and two for output, there are three possible combinations, with one common terminal in each case. Pierret, Semiconductor Device Fundamentals, Prentice Hall, 1996

27 Common Emitter Input resistance in Rib B r R R r Output resistance moderate/small Rout RC ro RC large Open Circuit Voltage gain vo gm RC ro large v i Short Circuit Current gain io gmrin large i i Large voltage and current gain but R in and R o not good for voltage amplifier. Figure 5.60 (a) A common-emitter amplifier using the structure of Fig (b) Equivalent circuit obtained by replacing the transistor with its hybrid- model.

28 Common Emitter with R E R e increases R in but reduces open circuit voltage gain. Current gain and output resistance are unchanged. Input resistance Rib 1 re Re Rin RB Rib increased R ib greatly increased by resistance reflection rule (Miller) Open Circuit Voltage gain vo gmrc v 1 g R reduced i m e Voltage gain reduced by ~ (1+g m R e ); R ib increased by this factor. Figure 5.61 (a) A common-emitter amplifier with an emitter resistance R e. (b) Equivalent circuit obtained by replacing the transistor with its T model.

29 Common Base Input resistance Open Circuit Voltage gain Short Circuit Current gain Rin re small vo gmrc large v io i unity ii Output resistance Non-inverting version of R R large common emitter. ou C Figure 5.62 (a) A common-base amplifier using the structure of Fig (b) Equivalent circuit obtained by replacing the transistor with its T model. Good for unity gain current buffer.

30 Common Collector Figure 5.63 (a) An emitter-follower circuit based on the structure of Fig (b) Small-signal equivalent circuit of the emitter follower with the transistor replaced by its T model augmented with r o. (c) The circuit in (b) redrawn to emphasize that r o is in parallel with R L. This simplifies the analysis considerably.

31 Input resistance Rin RB Rib Rib 1 re ro RL large Output resistance Rsig Rout ro re small 1 Open Circuit Voltage gain vo ro RL v R sig sig r r R 1 e o L ~unity Current gain io ro 1 i r R b o L large Voltage gain ~1 so emitter follows base input voltage (emitter follower) Good for amplifier output stage: large R in, small R out.

32 UNIT-2 METAL OXIDE FIELD EFFECT TRANSISTORS

33 Field Effect Transistors IBM/Motorola Power PC620 IBM Power PC 601 Motorola MC68020 EE314

34 Chapter 12: Field Effect Transistors 1.Construction of MOS 2.NMOS and PMOS 3.Types of MOS 4.MOSFET Basic Operation 5.Characteristics

35 The MOS Transistor Polysilicon Aluminum JFET Junction Field Effect Transistor MOSFET - Metal Oxide Semiconductor Field Effect Transistor n-channel MOSFET (nmos) & p-channel MOSFET (pmos)

36 The MOS Transistor Gate Oxide Gate Source n+ Polysilicon Drain n+ Field-Oxide (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor

37 Switch Model of NMOS Transistor V GS Gate Source (of carriers) Drain (of carriers) Open (off) (Gate = 0 ) Closed (on) (Gate = 1 ) R on V GS < V T V GS > V T

38 Switch Model of PMOS Transistor V GS Gate Source (of carriers) Drain (of carriers) Open (off) (Gate = 1 ) Closed (on) (Gate = 0 ) R on V GS > V DD V T V GS < V DD V T

39 MOS transistors Symbols D D G G S NMOS Enhancement NMOS D S Depletion D Channel G G B PMOS S Enhancement S NMOS with Bulk Contact

40 JFET and MOSFET Transistorsor Symbol L = m W = m SiO 2 Thickness = m Device characteristics depend on L,W, Thickness, doping levels

41 MOSFET Transistor Fabrication Steps

42 Building A MOSFET Transistor Using Silicon

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46 It is done. Now, how does it work?

47 n-channel MOSFET Basic Operation Operation in the Cutoff region pn junction: reverse bias i D =0 for v GS <V t0 Schematic When v GS =0 then i D =0 until v GS >V t0 (V t0 threshold voltage)

48 n-channel MOSFET Basic Operation Operation in the Triode Region For v DS <v GS -V t0 and v GS >V t0 the NMOS is operating in the triode region Resistor like characteristic (R between S & D, Used as voltage controlled R) For small v DS, i D is proportional to the excess voltage v GS -V t0

49 n-channel MOSFET Basic Operation Operation in the Triode Region i D K 2 2 vgs Vt0 vds vds K W L KP 2 Device parameter KP for NMOSFET is 50 A/V 2

50 n-channel MOSFET Basic Operation Operation in the Saturation Region (v DS is increased) Tapering of the channel - increments of i D are smaller when v DS is larger When v GD =V t0 then the channel thickness is 0 and i D K v GS V t0 2

51 n-channel MOSFET Basic Operation Example 12.1 An nmos has W=160 m, L=2 m, KP= 50 A/V 2 and V to =2 V. Plot the drain current characteristic vs drain to source voltage for v GS =3 V. i D i D K K 2 2 vgs Vt0 vds vds v GS V t0 2 K W L KP 2

52 n-channel MOSFET Basic Operation Example 12.1 Characteristic Channel length modulation i d depends on v DS in saturation region (approx: i D =const in saturation region) 2 i D Kv DS

53 p-channel MOSFET Basic Operation It is constructed by interchanging the n and p regions of n- channel MOSFET. Symbol Characteristic How does p-channel MOSFET operate? -voltage polarities -i D current -schematic

54 Fig. 5.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross section. Typically L = 1 to 10 m, W = 2 to 500 m, and the thickness of the oxide layer is in the range of 0.02 to 0.1 m.

55 Fig. 5.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.

56 Fig. 5.3 An NMOS transistor with v GS > V t and with a small v DS applied. The device acts as a conductance whose value is determined by v GS. Specifically, the channel conductance is proportional to v GS - V t, and this i D is proportional to (v GS - Vt) v DS. Note that the depletion region is not shown (for simplicity).

57 Fig. 5.5 Operation of the enhancement NMOS transistor as v DS is increased. The induced channel acquires a tapered shape and its resistance increases as v DS is increased. Here, v GS is kept constant at a value > V t.

58 Fig. 5.6 The drain current i D versus the drain-to-source voltage v DS for an enhancement-type NMOS transistor operated with v GS > V t.

59 Fig. 5.8 Derivation of the i D - v DS characteristic of the NMOS transistor.

60 Fig. 5.9 Cross section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well.

61 Fig (a) An n-channel enhancement-type MOSFET with v GS and v DS applied and with the normal directions of current flow indicated. (b) The i D - v DS characteristics for a device with V t = 1 V and k n (W/L) = 0.5 ma/v 2.

62 Fig The i D - v GS characteristic for an enhancement-type NMOS transistor in saturation (V t = 1 V and k n (W/L) = 0.5 ma/v 2 ).

63 Fig Increasing v DS beyond v DSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by L).

64 Fig Effect of v DS on i D in the saturation region. The MOSFET parameter V A is typically in the range of 30 to 200 V.

65 Fig Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance r o. The output resistance models the linear dependence of i D on v DS and is given by r o V A/ I D.

66 Fig The current-voltage characteristics of a depletion-type n-channel MOSFET for which V t = -4 V and k n (W/L) = 2 ma/v 2 : (a) transistor with current and voltage polarities indicated; (b) the i D - v DS characteristics; (c) the i D - v GS characteristic in saturation.

67 Fig Conceptual circuit utilized to study the operation of the MOSFET as an amplifier.

68 Fig Small-signal operation of the enhancement MOSFET amplifier.

69 Fig Total instantaneous voltages v GS and v D for the circuit in Fig

70 Fig Small-signal models for the MOSFET: (a) neglecting the dependence of i D on v DS in saturation (channel-length modulation effect); and (b) including the effect of channel-length modulation modeled by output resistance r o = V A / I D.

71 Fig the T model of the MOSFET augmented with the drain-to-source resistance ro.

72 Fig Basic MOSFET current mirror.

73 Fig Output characteristic of the current source in Fig and the current mirror of Fig for the case Q 2 is matched to Q 1.

74 Fig The CMOS common-source amplifier: (a) circuit; (b) i-v characteristic of the active-load Q 2 ; (c) graphical construction to determine the transfer characteristic; and transfer characteristic.

75 Fig The CMOS common-gate amplifier: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the circuit in (b).

76 Fig The source follower: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the equivalent circuit.

77 Fig (a) NMOS amplifier with enhancement load; (b) graphical determination of the transfer characteristic; (c) transfer characteristic.

78 Fig The NMOS amplifier with depletion load: (a) circuit; (b) graphical construction to determine the transfer characteristic; and (c) transfer characteristic.

79 Fig Small-signal equivalent circuit of the depletion-load amplifier of Fig (a), incorporating the body effect of Q 2.

80 Fig (a) The CMOS inverter. (b) Simplified circuit schematic for the inverter.

81 Fig Operation of the CMOS inverter when v 1 is high: (a) circuit with v 1 = V DD (logic-1 level, or V OH ); (b) graphical construction to determine the operating point; and (c) equivalent circuit.

82 Fig Operation of the CMOS inverter when v 1 is low: (a) circuit with v 1 = 0V (logic-0 level, or V OL ); (b) graphical construction to determine the operating point; and (c) equivalent circuit.

83 Fig The voltage transfer characteristic of the CMOS inverter.

84 Fig Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the operating point as the input goes high and C discharges through the Q N ; (d) equivalent circuit during the capacitor discharge.

85 Fig The CMOS transmission gate.

86 Fig Equivalent circuits for visualizing the operation of the transmission gate in the closed (on) position: (a) v A is positive; (b) v A is negative.

87 Fig (a) High-frequency equivalent circuit model for the MOSFET; (b) the equivalent circuit for the case the source is connected to the substrate (body); (c) the equivalent circuit model of (b) with C db neglected (to simplify analysis).

88 Fig Determining the short-circuit current gain I o /I i.