Microelectronic Devices and Circuits Lecture 22 - Diff-Amp Anal. III: Cascode, µa Outline Announcements DP:

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1 6.012 Microelectronic Devices and Circuits Lecture 22 DiffAmp Anal. III: Cascode, µa741 Outline Announcements DP: Discussion of Q13, Q13' impact. Gain expressions. Review Output Stages DC Offset of an OpAmp Pushpull/totem pole output stages Specialty Stages, cont. more useful transistor pairings The Marvelous Cascode Darlington Connection A Commercial OpAmp Example the µa741 The schematic and chip layout Understanding the circuit Bounding midband starting high frequency issues Review of Midband concept The Method of OpenCircuit Time Constants Clif Fonstad, 12/1/09 Lecture 22 Slide 1

2 DC offset at the output of an Operational Amplifier: DC offset: The node between Q 12 and Q 13 is a high impedance node whose quiescent voltage can only be determined by invoking symmetry.* 1.5 V The voltage symmetry says will be at this node. The voltage on these two nodes is equal if there is no input, i.e. v IN1 = v IN2 = 0, and if the circuit is truly symmetrical/matched. This is the high impedance node. Realworld asymmetries mean the voltage on this node is unpredictable. Q 11 Q V Q 13 ' 0.5 V 0.4 V Q 14 Q V A Q V 0 V Q V 0.6 V 0 V Q Q Q V 0.6 V Q 21 B Q 19 The voltage we need at this node to make V OUT = 0. In any practical Op Amp, a very small differential input, v IN1 v IN2, is require to make the voltage on this node (and V OUT ) zero. Clif Fonstad, 12/1/09 Lecture 22 Slide 2

3 DC offset at the output of an Op Amp, cont: DC offset: The transfer characteristic, vs (v IN1 v IN2 ), will not in general go through the origin, i.e., = A vd (v IN1 v IN2 ) V OFFSET 1V V OUT A vd = 2x µV V IN2 V IN1 V OUT In the example in the figure A vd is 2 x 10 6, and V OFFSET is 0.1 V. R 50nV 0.1V V IN2 V IN1 v IN R Input 1 Input 2 A vd 50! In a practice, an Op Amp will be used in a feedback circuit like the example shown to the left, and the value of with v IN = 0 will be quite small. For this example (in which A vd = 2 x 10 6, and V OFFSET = 0.1 V) is only 0.1 µv. In the D.P. you are asked for this value for your design. Clif Fonstad, 12/1/09 Lecture 22 Slide 3

4 Specialty pairings: Pushpull or Totem Pole Output Pairs A source follower output: Using a single source follower as the output stage must be biased with a relatively large drain current to achieve a large output voltage swing, which in turn dissipates a lot of quiescent power. 1.5 V 1.5 V v IN goes positive v IN Q 28 Load current is supplied through Q 28 as it turns on more strongly I BIAS goes positive R L v IN goes negative v IN As Q turns off I BIAS flows through load. Q Turns off I BIAS Negative swing limited to I BIAS R L R L The Problem 1.5 V 1.5 V Clif Fonstad, 12/1/09 Lecture 22 Slide 4

5 Specialty Pairings: The Pushpull or Totem Pole Output A stacked pair of complementary emitter or sourcefollowers Large input resistance Voltage gain near one Small output resistance Low quiescent power V V npn or nmos follower pnp or pmos follower v in V BEn v in V EBp Q n Q p v out R L v in V GSn v in V SGp Q n Q p v out R L V V Clif Fonstad, 12/1/09 Lecture 22 Slide 5

6 Specialty pairings: Pushpull or Totem Pole in Design Prob. Comments/Observations: The D.P. output stage involves four emitter follower building blocks arranged as two parallel cascades of two emitter follower stages each. Q 20 and Q 21 with joined sources at the output node is called a pushpull, or totem pole pair. v IN 1.5 V I BIAS2 Q Q Q 20 Q 21 50! They determine the output resistance of the amplifier. I BIAS3 Ideally the output stage voltage gain is V Clif Fonstad, 12/1/09 Lecture 22 Slide 6

7 Specialty pairings: Pushpull or Totem Pole in D.P., cont. Operation: The npn follower supplies current when the input goes positive to push the output up, while the pnp follower sinks current when the input goes negative to pull the output down. 1.5 V 1.5 V I BIAS2 Load current supplied through Q 20 v IN increases v IN Q 17 v BE20 v BE20 increases Q 20 increases 50! In parallel v IN decreaes v IN Q 18 v BE21 increases v EB21 I BIAS3 Q 21 decreases 50! Load current drawn out through Q 21 r out r out1 r out2 1.5 V r in r in1 r in2 1.5 V The input resistance, r out, is highest about zero output, and there it is the output resistance of the two follower stages in parallel. r in is lowest at this point, too, and is a parallel combination, also. Clif Fonstad, 12/1/09 (discussed in Lecture 21) Lecture 22 Slide 7

8 Specialty pairings: Pushpull or Totem Pole, cont. Voltage gain: The design problem uses a bipolar totem pole. The gain and linearity of this stage depend on the bias level of the totem pole. The gain is higher for with higher bias, but the power dissipation is also. v in V BE20 v in V EB V Q 20 Q V v out 50! To calculate the large signal transfer characteristic of the bipolar totem pole we begin with : ( ) = R L "i E 20 " i E 21 The emitter currents depend on (v IN ): ( i E 20 = "I E 20 e v IN " ) V t, i E 21 = I E 21 e " ( v IN " ) V t Putting this all together, and using I E21 = I E20, we have: ( v out = R L I E 20 e v in "v out ) V t " e " ( v in "v out ) V ( t ) = 2R L I E 20 sinh( v in " v out ) V t We can do a spreadsheet solution by picking a set of values for (v IN ), using the last equation to calculate the, using this to calculate v IN, and finally plotting vs v IN. The results are seen on the next slide. Clif Fonstad, 12/1/09 Lecture 22 Slide 8

9 Voltage gain, cont.: With a 50 Ω load and for several different bias levels we find: The gain and linearity are improved by increasing the bias current, but the cost is increased power dissipation. The A v is lowest and r out is highest at the bias point (i.e., V IN = V OUT = 0). r in to the stage is also lowest there. Clif Fonstad, 12/1/09 Lecture 22 Slide 9

10 Specialty pairings: Pushpull or Totem Pole in D.P., cont. r t 1.5 V Reviewing the voltage gain of an emitter follower: v t I BIAS Q 25 v out r l i in = i b v in r! "i b r o r obias r l v out = A v v in v out = (" 1)i b ( r l r o r Bias ) v in = i b r # (" 1)i b r l r o r Bias A v = v out v in = 1.5 V ( ) (" 1) ( r l r o r Bias ) ( )( r l r o r Bias ) r # " 1 (" 1)r $ l r # (" 1)r l Note: The voltage gains of the thirdstage emitter followers (Q 25 and Q 26 ) will likely be very close to one, but that of the stagefour followers might be noticeably less than one. Clif Fonstad, 12/1/09 Lecture 22 Slide 10

11 Specialty Pairings: The Cascode Commonsource stage followed by a common gate stage Large output resistance Good high frequency performance V C O Common Gate V GG v out External Load Common Source v in I BIAS C E V Clif Fonstad, 12/1/09 Lecture 22 Slide 11

12 Specialty Pairings: The Cascode, cont. v t TwoPort Analysis r t v in i in G i,cs G m,cs v in G i,cg G o,cs Common Source Common Gate i out v out G o,cg A i,cg i in g el G i,cs = 0, G m,cs = "g m,qcs, G o,cs = g o,qcs Cascode twoport: v in G i,cc G m,cc v in G o,cc v t r t i in G i,cg = g m,qcg, A i,cg =1, G o,cg " g o,qcs Cascode i out G i,cc = 0, G m,cc " #g m,qcs, G o,cc " g o,qcs v out g o,qcg g m,qcg g el g o,qcg g m,qcg Same G i and Gm of CS stage, with the very much larger Go of CG. Clif Fonstad, 12/1/09 Lecture 22 Slide 12

13 Specialty Pairings: The Cascode, cont. Cascode twoport: v in G i,cc G m,cc v in G o,cc v t r t i in Cascode i out v out g el G i,cc = 0, G m,cc " #g m,qcs, G o,cc " g o,qcs g m,qcg g o,qcg The equivalent Cascode transistor: The cascode twoport is that of a single MOSFET with the g m of the first transistor, and the output conductance of common gate. G D Q CC S g v gs v ds g mqcs v gs g oq cs g oq cg /g mqcg s,b d s,b Clif Fonstad, 12/1/09 Lecture 22 Slide 13

14 Specialty Pairings: The Cascode, cont. Cascode current mirrors: alternative connections Large differential output resistance 1.5 V Enhanced swing cascode 1.5 V Classic cascode Q 1 Q 2 Q 1 Q 2 Q 3 Q 4 Q 3 Q V v IN1 V REF2 Q 5 Q 6 v IN2 R L Wilson cascode Q 1 Q 3 Q 2 Q 4 V REF1 Q V The output resistances and load characteristics are identical, but the Wilson load is balanced better in bipolar applications, and the enhanced swing cascode has the largest output voltage swing of any of them. Clif Fonstad, 12/1/09 Lecture 22 Slide 14

15 Specialty pairings: Cascodes in a DPlike amplifier Q V V REF1 Q 2 Comments/Observations: This stage is essentially a normal sourcecoupled pair with a current mirror load, but there are differences.. Q 3 Q 5 V REF2 Q 4 Q 6 The first difference is that two driver transistors are cascode pairs. The second difference is that the current mirror load is also cascoded. v IN1 Q 7 Q V v IN2 The third difference is that the stage is not biased with a current source, but is instead biased by the first gain stage. Clif Fonstad, 12/1/09 Lecture 22 Slide 15

16 Specialty pairings: Cascodes in a DPlike amplifier, cont. 1.5 V 1.5 V Q 1 Q CC1 Q CC2 Q 2 V REF1 = v IN1 Q 3 Q 5 Q 7 Clif Fonstad, 12/1/09 V REF2 Q V Q 4 Q 6 v IN2 v IN1 Q CC1 = Q 1 /Q 3 Q CC2 = Q 2 /Q 4 Q CC3 = Q 7 /Q 5 Q CC4 = Q 8 /Q 6 Common sources Q CC3 Common gates Q CC4 1.5 V g m,cc v IN2 g o,cc Q CC1 g m1 g o1 g o3 gm3 Q CC2 g m2 g o2 g o4 gm4 Q CC3 g m7 g o7 g o5 gm5 Q CC4 g m8 g o8 g o6 gm6 Lecture 22 Slide 16

17 Specialty pairings: The Cascode, cont. The Folded Cascode: another variation 1.5 V Q 1 Q 2 Q 5 Q 3 Q 4 Q 6 Q 7 Q 8 A B Q 9 B Q V Clif Fonstad, 12/1/09 Lecture 22 Slide 17

18 Specialty pairings: The Darlington Connnection A bipolar pair stage used to get a large input resistance V Input resistance r in = 2" r # 2 = 2" 2 g m2 L O A D gload Output resistance r out =1 1.5g o2 g load g in Voltage gain ( ) v in Q 1 Q 2 v out gin A v $ v out v in = % g m17 ( ) 2 1.5g o2 g load g in I BIAS V Clif Fonstad, 12/1/09 Lecture 22 Slide 18

19 Multistage amplifier analysis and design: The µa741 The circuit: a full schematic Clif Fonstad, 12/1/09 Lecture 22 Slide 19 Source unknown. All rights reserved. This content is excluded from our Creative Commons license. For more information, see

20 Multistage amplifier analysis and design: The µa741 Figuring the circuit out: Emitterfollower/ commonbase "cascode" differential gain stage EF CB The full schematic Current mirror load Darlington common emitter gain stage Pushpull output Simplified schematic Another interesting discussion of the µa741: Clif Fonstad, 12/1/09 Lecture 22 Slide 20 Source unknown. All rights reserved. This content is excluded from our Creative Commons license. For more information, see

21 Multistage amplifier analysis and design: The µa741 The chip: a bipolar IC Capacitor Resistors Transistors Bonding pads Clif Fonstad, 12/1/09 Lecture 22 Slide 21 Source unknown. All rights reserved. This content is excluded from our Creative Commons license. For more information, see

22 Midband, cont: The midband range of frequencies In this range of frequencies the gain is a constant, and the phase shift between the input and output is also constant (either 0 or 180 ). log A vd Midband Range! LO! LO *! HI *! HI log!! b! a! d! c! 4! 5! 2! 1! 3 All of the parasitic and intrinsic device capacitances are effectively open circuits All of the biasing and coupling capacitors are effectively short circuits Clif Fonstad, 12/1/09 Lecture 22 Slide 23

23 Bounding midband: frequency range of constant gain and phase Common Source v in I BIAS V V C O v out C E v t Biasing capacitors: typically in mf range (C O, C S, etc.) effectively shorts above ω LO Device capacitors: typically in pf range (C gs, C gd, etc.) effectively open until ω HI Midband frequencies fall between: ω LO < ω < ω HI r t v t r t g v in = v gs g m v gs g o s,b v in g v gs C gs g m v gs g o s,b C gd g ob d s,b C S v out d g l v out LEC for common source stage with all the capacitors Common emitter LEC for in midband range Note: g l = g sl g el What are ω LO and ω HI? Clif Fonstad, 12/1/09 Lecture 22 Slide 24 g sl C O g el

24 Estimating ω HI Open Circuit Time Constants Method Open circuit time constants (OCTC) recipe: 1. Pick one C gd, C gs, C µ, C π, etc. (call it C 1 ) and assume all others are open circuits. 2. Find the resistance in parallel with C 1 and call it R Calculate 1/R 1 C 1 and call it ω Repeat this for each of the N different C gd 's, C gs 's, C µ 's, C π 's, etc., in the circuit finding ω 1, ω 2, ω 3,, ω N. 5. Define ω HI * as the inverse of the sum of the inverses of the N ω i 's: ω HI * = [Σ(ω i ) 1 ] 1 = [ΣR i C i ] 1 6. The true ω HI is similar to, but greater than, ω HI *. Observations: The OCTC method gives a conservative, low estimate for ω HI. The sum of inverses favors the smallest ω i, and thus the capacitor with the largest RC product dominates ω HI *. Clif Fonstad, 12/1/09 Lecture 22 Slide 25

25 Estimating ω LO Short Circuit Time Constants Method Short circuit time constants (SCTC) recipe: 1. Pick one C O, C I, C E, etc. (call it C 1 ) and assume all others are short circuits. 2. Find the resistance in parallel with C 1 and call it R Calculate 1/R 1 C 1 and call it ω Repeat this for each of the M different C I 's, C O 's, C E 's, C S 's, etc., in the circuit finding ω 1, ω 2, ω 3,, ω M. 5. Define ω LO * as the sum of the M ω j 's: ω LO * = [Σ(ω j )] = [Σ(R j C j ) 1 ] 6. The true ω LO is similar to, but less than, ω LO *. Observations: The SCTC method gives a conservative, high estimate for ω LO. The sum of inverses favors the largest ω j, and thus the capacitor with the smallest RC product dominates ω LO *. Clif Fonstad, 12/1/09 Lecture 22 Slide 26

26 log A vd Summary of OCTC and SCTC results Midband Range! LO! LO *! HI *! HI log!! b! a! d! c! 4! 5! 2! 1! 3 OCTC: an estimate for ω HI 1. ω HI * is a weighted sum of ω's associated with device capacitances: (add RC's and invert) 2. Smallest ω (largest RC) dominates ω HI * 3. Provides a lower bound on ω HI SCTC: an estimate for ω LO 1. ω LO * is a weighted sum of w's associated with bias capacitors: (add ω's directly) 2. Largest ω (smallest RC) dominates ω LO * 3. Provides a upper bound on ω LO Clif Fonstad, 12/1/09 Lecture 22 Slide 27

27 6.012 Microelectronic Devices and Circuits Lecture 22 DiffAmp Analysis II Summary Design Problem Issues Q13, Q13'; voltage gains Specialty stages useful pairings Source coupled pairs: MOS Pushpull output: Two followers in vertical chain Very low output resistance Shared duties for positive and negative output swings Cascode: Commonsource/emitter performance Greatly enhanced output resistance Find greatly enhanced high frequency performance also Darlington: Increased input resistance ona bipolar stage µa 741: A workhorse IC showing all of these pairs Bounding midband Open Circuit Time Constant Method: An estimate of ω HI Short Circuit Time Constant Method: An estimate of ω LO Clif Fonstad, 12/1/09 Lecture 22 Slide 28

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