1 Design of High-Speed Op-Amps for Signal Processing R. Jacob (Jake) Baker, PhD, PE Professor and Chair Boise State University 1910 University Dr. Boise, ID Abstract - As CMOS gate lengths scale to tens of nanometers open circuit gains drop and analog circuit design techniques that minimize the need for good matching become critical. This talk presents techniques useful for implementing high-speed CMOS op-amps for signal processing (e.g. analog-to-digital converters, filters, input receivers, etc.) in nanometer size CMOS. Techniques for biasing, device size selection, topologies, and compensation are discussed. Design examples are presented and used in system level building blocks. The emphasis is on practical design where power, speed, and manufacturability are critical.
2 Background and Content This talk assumes a background in CMOS op-amp design Biasing using current mirrors Know basics of op-amp design, e.g., compensating two-stage op-amps Calculation of small-signal gains The content of this talk is from: CMOS Circuit Design, Layout, and Simulation, Second Edition, Wiley-IEEE, (for the book s figures and simulation netlists)
3 Design with nm devices (here we use a 50 nm process) Key points Devices do not follow the square-law equations (so don t use them)! Nanometer CMOS is characterized using: On current Off current VDD Gate oxide capacitance Plots of measured data (note equations can t be used; too complicated for hand calculations).
4 Long Channel IV curves
5 Transition frequency FOM (figure of merit) for CMOS amplifier design Important!!!
6 Biasing for high speed Must use minimum length devices Matching becomes even more important Larger overdrive results in faster circuits Drawback is that the devices enter the triode region earlier For minimum power use mimimum size devices For nm CMOS minimum (drawn) W is, generally, 10 times minimum L Use for NMOS 10/1 and for PMOS, to match drive, 20/1 Concerns Is there enough drive using minimum-size devices? Matching!!!
7 Examples for general design Use 2 to 5 times minimum L (use minimum L for high-speed) Increases open circuit gain (output resistance) Using longer L improves matching Use overdrive voltage that is 5% of VDD Increase for high-speed design (say 10% of VDD) Table on the next page shows typical parameters for general design
9 Bias current (overdrive) and gain
10 Temperature stability Power supply insensitive Good variations with process Biasing Sets the overdrive voltages in the design Need a self-biased reference; a beta multiplier reference (BMR)
11 Problems with BMRs in nm CMOS
12 BMR for nm CMOS
13 Circuit implementation of a BMR in nm CMOS
14 Stability is Critical for this design Removing the capacitors causes the reference to oscillate.
15 Generating Bias Voltages for nm Design
16 Performance of Cascode Current Mirrors
17 Output Buffer with Bias Voltages
18 Two-Stage Op-Amp with Miller Compensation Simple topology using diff-amp and common-source amplifier Can t drive resistive loads Poor PSRR Using Miller compensation Poor PSRR Have that pesky right-half plane zero Slow-speed (unless you use bias with large devices and currents) for a given load C Poor slewing
19 Example of a bad (academic) op-amp design
20 AC Response of this bad design with Rz = 0 and Cc = 2.4 pf
21 Step response of the bad design
22 Making the Op-Amp more Stable Obviously we can increase Rz to move the zero into the LHP Controlling the value of Rz becomes challenging over temperature and process The stability is becoming a problem because the pole associated with the op-amp s output, f 2, is too low. Increase f 2 by increasing the g m of the output stage (g m2 ). Increase widths of the devices so overdrive stays constant (I D goes up)! In general, make sure overdrive voltages are the same in all MOSFETs!
23 Practical Way to Compensate an Op-Amp Never use Miller Compensation Never, ever, connect a compensation capacitor between two highimpedance nodes!!! (unless you want slow speed) The literature is filled with examples of how not to compensate op-amps for high speed operation We ll develop Indirect Feedback Compensation in the next few pages Practical way to compensate an op-amp Feedback a current indirectly to the output of the diff-amp via: MOSFETs laid out in series (one operating in the triode region) A common-gate amplifier A cascode structure Better PSRR Smaller layout area (compensation capacitor reduced 4 to 10 times) Much faster!!!
24 Indirect Feedback Compensation Current through Cc We ll use this. How?
25 Using Triode Operating MOSFETs Triode-operating MOSFETs. 100/2 laid out as two 100/1 High-impedance node
26 Other examples of Indirect Feedback Compensation Using a common-gate amplifier Using a cascode structure
27 Other examples of Indirect Feedback Compensation, cont d Triode-operating MOSFETs. 50/2 laid out as two 50/1 in series. Using NMOS triode-operating diff-pair for good PSRR
28 Equations RHP zero eliminated. A LHP zero is introduced.the LHP zero increases the phase-margin and speed. Equation for the unity gain frequency remains the same. However, the value goes up because Cc can drop by 4 to 10 Cc drops because load C has less effect on f 2
29 Example (next page) Two-Stage Op-Amp Cascode input stage (sometimes called a telescopic input stage) Use a push-pull output stage for rail-to-rail output swing Indirect feedback compensation > 100 MHz gain-bandwidth product while using 250 µa and a VDD of 1 V (excluding the bias circuit power is 250 µw) Excellent PSRR Compact layout area
30 A Practical General Purpose Op-Amp
31 Step Response Previous page
32 Comments We were careful to select overdrive voltages for a specific speed (transition frequency) Important to avoid adding a low-frequency pole in the transfer function and thus having a non-optimized design Fiddling with widths while not keeping the overdrive voltages constant is a path to low-quality designs In general, only vary lengths of MOSFETs in DC circuits To push f 2 to a higher frequency we increase the widths of the output stage (g m2 and current in output stage are increased) Reducing C c causes the gain-bandwidth product, f un, to increase (and move towards f 2 ).
33 Bad Output Stage Design Not controlling current in the output stage leads to: Bad input-referred offset Potential for large power dissipation Not controlling output stages gm (and thus stability) Don t let SPICE fool you into thinking you can actually set the current in an output buffer without using current mirrors (you can t!)
34 Example (bad) Output Stages If M7 mirrors current in M4 then M8 triodes and the gain drops. The gate of M7 will have to drop, with the negative feedback around the op-amp (so M8 operates in saturation). The result is a huge current flowing in the inverter output stage.
35 Bad Output Stage Design Cont d Source follower is used to allow the gate of M8 to drop to a lower voltage so that, hopefully, it can remain in saturation during normal operation. Again, however, we are not controlling the current in the output stage. It may be small, big, or exactly what we want (again, don t let SPICE fool you into thinking this type of design is okay (it s not!)
36 Bad Diff-Amp Biasing Never design a diff-amp where the PMOS current sources fight against NMOS current sources. The outputs will float up or down causing some MOSFETs to triode.
37 Add Control to a Diff-Amp to Set Currents The added control ensures the current sourced by the PMOS equals the current sunk by the NMOS. Controls common-mode output voltage via common-mode feedback (CMFB).
38 Op-Amps in Signal Processing Use fully-differential inputs and outputs Reduces the common-mode noise Need to employ common-mode feedback (CMFB) Our examples here will use switched capacitor CMFB and two stage op-amps (for the lowest power and highest speed) Fully-differential topologies offer the benefit that class AB output buffers can be implemented without floating current sources Don t need the additional bias circuits
39 Basic Fully-Differential Op-amp
40 Need to set output common-mode level
41 Switched-Capacitor CMFB
42 Use of SC-CMFB For the most robust design used SC-CMFB around each stage The outputs of the diff-amp are set to bias the output buffer The outputs of the buffer (the op-amp outputs) are balanced around the common-mode voltage, V CM SC-CMFB provides wide operating range Low power consumption Small loading Robust operation
43 Example: a S/H amplifier
44 Input Diff-Amp
45 Setting the Output CM Level method to get proper biasing with horrible offsets
46 Output Stage
47 Simulating the Op-Amp s Operation No compensation capacitance (unstable in some cases), settling approx. 6 ns Note that these simulation results are directly from Fig in my CMOS book, see
48 Increasing Compensation Cap to 50 ff The settling time is approximately 5 ns. Note the stability is, of course, better. Direct sim of Fig except the rise/fall times of the clock signals was reduced from 2 ns to 200 ps (this slows the simulation time)
49 Increasing Compensation Cap to 150 ff Better stability but longer settling time. What do we do?
50 Increasing speed (decreasing settling time) We need to increase the gain bandwidth product of the op-amp The only ways to do this are to decrease the compensation capacitor and/or increase the diff-amp s transconductance, f un = g m /2πC c The problem with this, as just shown, is stability (the pole, f 2 associated with the output of the op-amp is comparable to f un ) Need to push f 2 to a higher frequency by increasing the output buffers g m We do this by increasing the widths of the devices in the output buffer Note this results in larger current flowing in the output buffers keeping overdrive voltages constant (important) To increase the g m of the diff-pair we increase their widths
51 Increasing Speed Use a 12.5 ff capacitor for C c (1/4 of the 50 ff seen before) Note that we are designing in a 50 nm process Increase g m2 by 4 by increasing the widths in the output buffer by 4 Cost is additional power dissipation in the output buffer Settling time drops to 2 ns (now we re cooking with gas!) Op-amp power is 200 µw quiescent
52 Conclusions: Further Increases in Speed (comments) Why didn t we try to increase speed by increasing the diffpair s g m (by increasing the pair s widths)? This causes the overdrive voltages of the diff-pair to decrease unless we increase the diff-pair bias current (which would require increasing the widths of other devices in order to maintain the overdrive voltages). The drop in the widths of the diff-pair cause (low) parasitic poles in opamp s frequency response. Small increases in diff-pair width are okay. We used a factor of 3 in the sims here, that is, the diff-pair were 30/1 while other NMOS were 10/1. Note, again, that we attempt to design with fixed overdrive voltages to keep the design optimized for speed
53 Conclusions: Further Increases in Speed (comments continued) Looking at these results we might ask, Why not multiple the sizes in the output buffer by 8 and divide the compensation capacitor by 8? We run into a brick wall. The parasitic poles of the devices limit further increases in speed. To obviate this limitation we must increase the device s transition frequency (by increasing the overdrive voltages change the bias circuit) Note we are assuming minimum L devices (absolutely necessary for high-speed design)
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