1 6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott
2 Broadband Communication System Example: high speed data link on a PC board Connector Adjoining pins Controlled Impedance PCB trace package die Driving Source Z 1 Delay = x Characteristic Impedance = Z o Transmission Line On-Chip V in C 2 C 1 L 1 R L V L - We ve now studied how to analyze the transmission line effects and package parasitics - What s next?
3 High Speed, Broadband Amplifiers The first thing that you typically do to the input signal is amplify it package Connector Adjoining pins Controlled Impedance PCB trace die Driving Source On-Chip Z 1 Delay = x Characteristic Impedance = Z o L 1 Amp V out V Transmission Line in C 1 C 2 R L V L Function - Boosts signal levels to acceptable values - Provides reverse isolation Key performance parameters - Gain, bandwidth, noise, linearity
4 Basics of MOS Large Signal Behavior (Qualitative) Triode I D V GS S G D V DS=0 Overall I-V Characteristic C channel = C ox (V GS -V T ) I D Pinch-off I D Pinch-off Saturation V GS S G D V D = V Triode Saturation I D V V DS V GS S G D V D > V
5 Basics of MOS Large Signal Behavior (Quantitative) V GS Triode G S D C channel = C ox (V GS -V T ) I D V DS=0 I D = µ n C ox W L (V GS - V T - V DS /2)V DS I D for V DS << V GS - V T µ n C ox W L (V GS - V T )V DS Pinch-off I D V GS S G D V D = V V = V GS -V T 2I V = D L µ n C ox W Saturation I D V GS S G D V D > V 1 I D = µ n C W ox (V 2 GS -V T ) 2 (1+λV DS ) L (where λ corresponds to channel length modulation)
6 Analysis of Amplifier Behavior Typically focus on small signal behavior - Work with a linearized model such as hybrid-π - Thevenin modeling techniques allow fast and efficient analysis To do small signal analysis: Small Signal Analysis Steps I D R D 1) Solve for bias current I d v in V bias R G R S v out 2) Calculate small signal parameters (such as g m, r o ) 3) Solve for small signal response using transistor hybrid-π small signal model
7 MOS DC Small Signal Model Assume transistor in saturation: I D R D R D R G R G v gs g m v gs -g mb v s r o R S v s R S g m = µ n C ox (W/L)(V GS - V T )(1 + λv DS ) = 2µ n C ox (W/L)I (assuming λv D DS << 1) Thevenin modeling based on the above γg m g mb = where γ = 2 2 Φ p + V SB In practice: g mb = g m /5 to g m /3 r o = 1 λi D 2qε s N A C ox
8 Capacitors For MOS Device In Saturation Top View Side View I D V GS E G S D W C jsb C ov S C gc C cb C ov D C jdb V D > V B L D L L D E E L junction bottom wall cap (per area) junction sidewall cap (per length) source to bulk cap: C jsb = C j (0) C jsw (0) WE V SB Φ B 1 + V SB Φ B (W + 2E) drain to bulk cap: C jsd = C j (0) C jsw (0) WE V DB Φ B 1 + V DB Φ B (W + 2E) overlap cap: C ov = WL D C ox + WC fringe 2 gate to channel cap: C gc = C ox W(L-2L D ) 3 (make 2W for "4 sided" perimeter in some cases) channel to bulk cap: C cb - ignore in this class
9 MOS AC Small Signal Model (Device in Saturation) R D R G R G I D R D v gs C gd C gs g m v gs -g mb v s r o C db C sb R S v s R S 2 C gs = C gc + C ov = C ox W(L-2L D ) + C 3 ov C gd = C ov C sb = C jsb (area + perimeter junction capacitance) C db = C jdb (area + perimeter junction capacitance)
10 Wiring Parasitics Capacitance - Gate: cap from poly to substrate and metal layers - Drain and source: cap from metal routing path to substrate and other metal layers Resistance - Gate: poly gate has resistance (reduced by silicide) - Drain and source: some resistance in diffusion region, and from routing long metal lines Inductance - Gate: poly gate has negligible inductance - Drain and source: becoming an issue for long wires Extract these parasitics from circuit layout
11 Frequency Performance of a CMOS Device Two figures of merit in common use - f t : frequency for which current gain is unity - f max : frequency for which power gain is unity Common intuition about f t - Gain, bandwidth product is conserved - We will see that MOS devices have an f t that shifts with bias This effect strongly impacts high speed amplifier topology selection We will focus on f t - Look at pages of Tom Lee s book for discussion on f max
12 Derivation of f t for MOS Device in Saturation i d R LARGE I D +i d i in v gs C gd C gs g m v gs -g mb v s r o C db V bias i in C sb Assumption is that input is current, output of device is short circuited to a supply voltage - Note that voltage bias is required at gate The calculated value of f t is a function of this bias voltage
13 Derivation of f t for MOS Device in Saturation i d R LARGE I D +i d i in v gs C gd C gs g m v gs -g mb v s r o C db V bias i in C sb
14 Derivation of f t for MOS Device in Saturation i d i in slope = -20 db/dec 1 f t f
15 Why is f t a Function of Voltage Bias? f t is a ratio of g m to gate capacitance - g m is a function of gate bias, while gate cap is not (so long as device remains biased) First order relationship between g m and gate bias: - The larger the gate bias, the higher the value for f t Alternately, f t is a function of current density - So f t maximized at max current density (and minimum L)
16 Speed of NMOS Versus PMOS Devices NMOS devices have much higher mobility than PMOS devices (in current, non-strained, bulk CMOS processes) - Intuition: NMOS devices provide approximately 2.5 x g m for a given amount of capacitance and gate bias voltage - Also: NMOS devices provide approximately 2.5 x I d for a given amount of capacitance and gate bias voltage
17 Assumptions for High Speed Amplifier Analysis Assume that amplifier is loaded by an identical amplifier and by fixed wiring capacitance C tot = C out +C in +C fixed C in C out C in Amp Amp C fixed Intrinsic performance - Defined as the bandwidth achieved for a given gain when C fixed is negligible - Amplifier approaches intrinsic performance as its device sizes (and current) are increased In practice, optimal sizing (and power) of amplifier is roughly where C in +C out = C fixed
18 The Miller Effect Concerns impedances that connect from input to output of an amplifier Z in Z f Z out V in Input impedance: A v Amp V out Z L Output impedance:
19 Example: The Impact of Capacitance in Feedback Consider C gd in the MOS device as C f - Assume gain is negative C f Z in Z out V in A v Amp V out Z L Impact on input capacitance: Output impedance:
20 Amplifier Example CMOS Inverter Assume that we set V bias such that the amplifier nominal output is such that NMOS and PMOS transistors are all in saturation - Note: this topology VERY sensitive to bias errors M 2 M 4 v out v in M 1 C fixed M 3 V bias C tot = C db1 +C db2 + C gs3 +C gs4 + K(C ov3 +C ov4 ) + C fixed (+C ov1 +C ov2 ) Miller multiplication factor
21 Transfer Function of CMOS Inverter v out v in (g m1 +g m2 )(r o1 r o2 ) slope = -20 db/dec Low Bandwidth! 1 1 g m1 +g m2 2πC tot (r o1 r o2 ) 2πC tot f M 2 M 4 v out v in M 1 C fixed M 3 V bias C tot = C db1 +C db2 + C gs3 +C gs4 + K(C ov3 +C ov4 ) + C fixed (+C ov1 +C ov2 ) Miller multiplication factor
22 Add Resistive Feedback v out v in (g m1 +g m2 )(r o1 r o2 ) (g m1 +g m2 )R f slope = -20 db/dec Bandwidth extended and less sensitivity to bias offset 1 f 1 g m1 +g m2 2πC tot (r o1 r o2 ) 1 2πC tot 2πC tot R f Rf M 2 v out M 4 v in M 1 C fixed M 3 V bias C tot = C db1 +C db2 + C gs3 +C gs4 + K(C ov3 +C ov4 ) + C Rf /2 + C fixed (+C ov1 +C ov2 ) Miller multiplication factor
23 We Can Still Do Better We are fundamentally looking for high g m to capacitance ratio to get the highest bandwidth - PMOS degrades this ratio - Gate bias voltage is constrained M 2 M 4 Rf v out v in M 1 C fixed M 3 V bias C tot = C db1 +C db2 + C gs3 +C gs4 + K(C ov3 +C ov4 ) + C Rf /2 + C fixed (+C ov1 +C ov2 ) Miller multiplication factor
24 Take PMOS Out of the Signal Path Ibias V bias2 M 2 R f v out R f v out v in M1 C L v in M 1 C L V bias V bias Advantages - PMOS gate no longer loads the signal - NMOS device can be biased at a higher voltage Issue - PMOS is not an efficient current provider (I d /drain cap) Drain cap close in value to C gs - Signal path is loaded by cap of R f and drain cap of PMOS
25 Shunt-Series Amplifier R s R in I bias R f R out v out R s R in R f R out R L v out v in M 1 R L v in M 1 V bias V bias R 1 R 1 Use resistors to control the bias, gain, and input/output impedances - Improves accuracy over process and temp variations Issues - Degeneration of M 1 lowers slew rate for large signal applications (such as limit amps) - There are better high speed approaches the advantage of this one is simply accuracy
26 Shunt-Series Amplifier Analysis Snapshot From Chapter 8 of Tom Lee s book (see pp ): - Gain v in R s R in v x R f R out R L v out M 1 V bias R 1 - Input resistance - Output resistance Same for R s = R L!
27 NMOS Load Amplifier V dd M 2 v out v in v in 1 g m2 I d v out g m1 g m2 slope = -20 db/dec V bias M1 C fixed M 3 1 g m1 f Ctot = C db1 +C sb2 +C gs2 + C gs3 +KC ov3 + C fixed g m2 2πC tot (+C ov1 ) Miller multiplication factor 2πC tot Gain set by the relative sizing of M 1 and M 2
28 Design of NMOS Load Amplifier V dd C tot = C db1 +C sb2 +C gs2 + C gs3 +KC ov3 + C fixed 1 g m2 M 2 I d v out (+C ov1 ) Miller multiplication factor v in V bias M1 C fixed M 3 Size transistors for gain and speed - Choose minimum L for maximum speed - Choose ratio of W 1 to W 2 to achieve appropriate gain Problem: V T of M 2 lowers the bias voltage of the next stage (thus lowering its achievable f t ) - Severely hampers performance when amplifier is cascaded - One person solved this issue by increasing V dd of NMOS load (see Sackinger et. al., A 3-GHz 32-dB CMOS Limiting Amplifier for SONET OC-48 receivers, JSSC, Dec 2000)
29 Resistor Loaded Amplifier (Unsilicided Poly) V dd R L v out v in v in V bias I d vout C fixed M 1 M 2 C tot = C db1 +C RL /2 + C gs2 +KC ov2 + C fixed (+C ov1 ) Miller multiplication factor g m1 R L 1 1 2πR L C tot slope = -20 db/dec g m1 2πC tot f This is the fastest non-enhanced amplifier I ve found - Unsilicided poly is a pretty efficient current provider (i..e, has a good current to capacitance ratio) - Output swing can go all the way up to V dd Allows following stage to achieve high f t - Linear settling behavior (in contrast to NMOS load)
30 Implementation of Resistor Loaded Amplifier Typically implement using differential pairs V dd R 1 R 2 V o+ V o- I bias /2 V in+ V in- C fixed C fixed αi bias M 1 M 2 M 3 M 4 I bias M 5 M 6 M 7 Benefits - Self-biased - Common-mode rejection Negative - More power than single-ended version
31 The Issue of Velocity Saturation We classically assume that MOS current is calculated as Which is really - V dsat,l corresponds to the saturation voltage at a given length, which we often refer to as V It may be shown that - If V gs -V T approaches LE sat in value, then the top equation is no longer valid We say that the device is in velocity saturation
32 Analytical Device Modeling in Velocity Saturation If L small (as in modern devices), than velocity saturation will impact us for even moderate values of V gs -V T - Current increases linearly with V gs -V T! Transconductance in velocity saturation: - No longer a function of V gs!
33 Example: Current Versus Voltage for 0.18µ Device I d V gs M 1 W L = 1.8µ 0.18µ 1.4 I d versus V gs I d (milliamps) V (Volts) gs
34 Example: G m Versus Voltage for 0.18µ Device I d V gs M 1 W L = 1.8µ 0.18µ 1 g m versus V gs g m (milliamps/volts) V (Volts) gs
35 Example: G m Versus Current Density for 0.18µ Device I d V gs M 1 W L = 1.8µ 0.18µ Transconductance versus Current Density 1 Transconductance (milliamps/volts) Current Density (microamps/micron)
36 How Do We Design the Amplifier? Highly inaccurate to assume square law behavior We will now introduce a numerical procedure based on the simulated g m curve of a transistor - A look at g m assuming square law device: - Observe that if we keep the current density (I d /W) constant, then g m scales directly with W This turns out to be true outside the square-law regime as well - We can therefore relate g m of devices with different widths given that have the same current density
37 A Numerical Design Procedure for Resistor Amp Step 1 V dd R V o- R Vo+ Two key equations - Set gain and swing (singleended) I bias V in+ V in- αi bias M 1 M 2 M 5 M 6 2I bias Equate (1) and (2) through R Can we relate this formula to a g m curve taken from a device of width W o?
38 A Numerical Design Procedure for Resistor Amp Step 2 We now know: Substitute (2) into (1) The above expression allows us to design the resistor loaded amp based on the g m curve of a representative transistor of width W o!
39 Example: Design for Swing of 1 V, Gain of 1 and 2 Transconductance (milliamps/volts) Assume L=0.18µ, use previous g m plot (W o =1.8µ) Transconductance versus Current Density A=2 A=1 g m (w o =1.8µ,I den ) Current Density - I den (microamps/micron) For gain of 1, current density = 250 µa/µm For gain of 2, current density = 115 µa/µm Note that current density reduced as gain increases! - f t effectively decreased
40 Example (Continued) Knowledge of the current density allows us to design the amplifier - Recall - Free parameters are W, I bias, and R (L assumed to be fixed) Given I den = 115 µa/µm (Swing = 1V, Gain = 2) - If we choose I bias = 300 µa Note that we could instead choose W or R, and then calculate the other parameters
41 How Do We Choose I bias For High Bandwidth? C tot = C out +C in +C fixed C in C out C in Amp Amp C fixed As you increase I bias, the size of transistors also increases to keep a constant current density - The size of C in and C out increases relative to C fixed To achieve high bandwidth, want to size the devices (i.e., choose the value for I bias ), such that - C in +C out roughly equal to C fixed