Amplifiers Frequency Response Examples

Transcription

1 ECE 5/45 Analog IC Design We will use the following MOSFET parameters for hand-calculations and the µm CMOS models for corresponding simulations. Table : Long-channel MOSFET parameters. Parameter NMOS PMOS Scale factor (L min ) µm V DD 5 V V T HN and V T HP KP n and KP p 20 µa V 2 40 µa V 2 Bias Current, I D 20µA 20µA g mn and g mp 50 µa 50 µa V V V ov 2I = D gm 250mV 250mV W/L 0/2 30/2 V GS and V SG.05V.5V r on and r op 5MΩ 4MΩ C ox = ɛox.75 ff t ox µm 2 C oxn and C oxp 35 ff 05 ff C gsn and C sgp 23.3 ff 70 ff C gdn and C dgp 2 ff 6 ff f T n and f T p 900 MHz 300 MHz Pole-splitting Equations The pole-splitting equations were derived for a second-order amplifier in class using the circuit model shown in Fig. Figure : Second-order amplifier model used for analyzing pole-splitting. f p = 2πR [C +(+g m2r 2)C c]+r 2(C 2+C c) 2πg m2r 2R C c R(+gm2R2)Cc+RC+R2(Cc+C2) 2πR R 2[C C c+c C 2+C cc 2] 2π(C C c+c C 2+C cc 2) gm2 2πC 2

2 f z = ( g m2 R z ) f un = A v f p = gm Example : Common Source Amplifier Determine the gain, magnitude, and phase shift of the amplifier shown in Figure 2 below. For high-frequency small-signal analysis, the C big R big network exhibits a high-pass frequency Figure 2 response which allows the input signal at frequencies ω in R big C big At DC, or frequencies R big C big to be applied to the amplifier., the capacitor DC blocks the AC input so that the V GS for the NMOS M is set by the current source. This is an example of AC-coupling of the input to the amplifier circuit. Similarly, the output can also be DC-blocked by placing a large capacitor in series with the output node (not shown here). The estimated low-frequency gain of the circuit is A v = g m r o r o2 = 50 µa V (5MΩ 4MΩ)=333, which in db scale is 20log 0 (333) = 50.45dB. Since there are two high-impedance nodes in this circuit, which interact through the Miller capacitance (C gd ), we expect two low-frequency poles. We say low-frequency poles, as eventually all MOSFETs will lead to corresponding poles at higher frequencies due to parasitic capacitances and the resulting f T limitation. As per the model in Fig., we have R = 00Ω, R 2 = r o r o2 = 2.22MΩ. C = C gs = 23.3fF, C C = C gd = 2fF, and C 2 = C dg2 = 6fF. g m = R s = µa 00k = 00 V g m2 = 50 µa V. (Norton equivalent of the Thevenin input source). We will use pole splitting equations to determine the poles and zeros: f p 2πg m2r 2R C c = 2.39MHz 2π(C = 240MHz C c+c C 2+C cc 2) f z = gm2 =.94GHz Compare these calculations with the simulation results in Fig. 3. Here, the phase margin is roughly 35ř. 2

3 Figure 3: (left) schematic for simulation, (right) simulated frequency response. Example 2: Common Source Amplifier with Miller Compensation Determine the frequency response of the amplifier shown in Figure 4 below. Figure 4 This circuit is same as the previous example, except for the additional Miller cap of pf. Again, the low-frequency gain of the circuit is 50.45dB. The second-order amplifier model is modified so that we have C 2 = C C + C dg2 pf. Again, using the pole splitting-equations, we get: f p 2πg m2r 2R C c = 4.78kHz 2π(C = 8MHz C c+c C 2+C cc 2) f z = gm2 = 23.82MHz and f un = gm =.59MHz Compare these calculations with the simulation results in Fig. 5. Here, the phase margin is improved and is roughly 85ř (actually overdamped) and the unity-gain (aka gain-crossover) frequency is f un = 3

4 .59M Hz. We can see that after Miller compensation, the frequency response looks similar to that of a first-order sytem near f un. Figure 5: (left) schematic for simulation, (right) simulated frequency response. Example 3: Two-Stage Amplifier Determine the frequency response of the amplifier shown in Figure 6 below. Since there are two high-impedance nodes in this two-stage amplifier, we expect two low-frequency Figure 6 poles. Note that the input cap of M (i.e. C gs ) will not contribute a pole as the source impedance is zero. As per the model in Fig., we have R = r o r o2 = 2.22MΩ, and R 2 = r o3 r o4 = 2.22MΩ. C = C gd + C dg2 + C gs3 = 2fF + 6fF fF = 3.3fF. Note that these are approximated values, you can get more accurate values from Spectre for a well characterized process. C C = pf + C gd pf, and C 2 = C L + C dg4 = 00fF + 6fF = 06fF. g m = g m2 = 50 µa V. 4

5 The estimated low-frequency gain of the circuit is A v = g m R g m2 R 2 = (50 µa V (5MΩ 4MΩ))2, which is 2 20log 0 (333) = 00.9dB. Using pole splitting equations, we determine the poles and zeros: f p 2πg m2r 2R C c = 25kHz 2π(C = 70MHz C c+c C 2+C cc 2) f z = gm2 = 23.8MHz and f un = gm = 23.82MHz Compare these calculations with the simulation results in Fig. 5. Here, the phase margin is roughly 0ř due to the RHP zero closer to the f un. This can be improved by eliminating the RHP zero by using a zero-nulling resistor (not shown here). Figure 7: (left) schematic for simulation, (right) simulated frequency response. Example 4: Cascode Amplifier Determine the frequency response of the amplifier shown in Figure 8 below. The low-frequency gain of the circuit is A v = g m g mp rop g 2 mn ron 2 = 50 µa V (3.75GΩ 2.4GΩ), which is 20log 0 (29000) = 06.8dB. Here, we have three high-impedance nodes, and C gd will experience Miller-effect due to inverting gain from node A to X. M 2 is a common-gate device and will provide capacitive isolation between nodes A-X and Y (i.e. no Miller cap between X and Y). We can use either Miller approximation or pole-splitting equations to find the poles at nodes A and X. Let s first observe the gain from node A to X, A v,ax. Using the A v = G m R out lemma discussed in class (and in the textbook), we have G m = g m and R out = r o R M2s, where R M2s is the impedance looking up the source of M 2. Recall that we derive R M2s in the class (for common-gate amplifier) as: R R M2s = D (g m2+g mb2 )r o2 + g m2+g mb2. Here, we have R D g m3 r o3 r o4 = g mp rop. 2 Ignoring body-effect, we get 5

6 Figure 8 R M2s = gmpr2 op g mnr on + g mn r op, as we have g mn = g mp and r op r on (not g m2 source of M 2 as a common misconception would suggest!). looking into the This eventually results in R out = r op r on, resulting in A v,ax = g m r op r on = 333. This gain is large and thus can lead to erroneous results if Miller approximation was used (only moderate Miller Killer effect here, unlike in the class notes). Using pole splitting equations, we determine the poles and zeros at nodes A and X (Note that we used Miller approximation in the class notes): R A = 00k, R X = r op r on = 2.22MΩ, C A = C gs 23.3fF, C X = C gd + C gs2 25.3fF, C c = C gd = 2fF g ma = R A, and g mx = g m = 50 µa V f p = 2.4MHz 2πg mx R X R A C c g mx C c 2π(C A C c+c A C X +C cc X ) = 70MHz f z = g mx 2πC C =.93GHz Further, due to capacitive isolation, the pole at Y can be directly determined from the output time-constant (R Y C Y ): R Y = g mp r 2 op g mn r 2 on = 3.75GΩ 2.4GΩ =.46GΩ, C Y = C L + C gd2 + C dg3 = 00fF + 3fF + 6fF = 09fF. f p3 2πR Y C Y = khz Compare these calculations with the simulation results in Fig. 3. Here, the location of f p3, the dominant or low-frequency pole, was accurately estimated. However, the locations of f p and f p2 are slightly off as these two poles are closely interacting with each other and thus test our pole-splitting approximations. Note that a very large (00GΩ) resistor is used for biasing in Fig. 9, otherwise the simulated gain in Fig. 9 will be off from the estimated value. This is a precaution to be used when dealing with very high-impedance nodes in the circuits (R out =.46GΩ) and even GΩ in parallel can reduce 6

7 the expected gain. In practice, however, we use a diffamp for the first stage for easy biasing using a tail current source, or inductor-based biasing networks for bandpass amplifiers at RF/microwave frequencies. Figure 9: (left) schematic for simulation, (right) simulated frequency response. References [] R. J. Baker, CMOS Circuit Design, Layout and Simulation R. J. Baker, 3rd Edition, Wiley- IEEE, 200.[2] 7