EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design

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1 EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design References: Analog Integrated Circuit Design by D. Johns and K. Martin and Design of Analog CMOS Integrated Circuits by B. Razavi All figures in this set of slides are taken from the above books Shahriar Mirabbasi Department of Electrical and Computer Engineering University of British Columbia 1

2 Gain Small-signal bandwidth Large-signal performance Output swing Input common-mode range Linearity Noise/offset Supply rejection General Considerations 2

3 One-Stage Op Amps 3

4 One-Stage Op Amp in Unity Gain Configuration 4

5 Cascode Op Amps 5

6 Unity Gain One Stage Cascode 6

7 Folded Cascode Op Amps 7

8 Folded Cascode Stages 8

9 Folded Cascode (cont.) 9

10 Folded Cascode (cont.) A v g m1 {[(g m 3 + g mb3 )r o3 (r o1 r o5 )] [(g m 7 + g mb 7 )r o7 r o9 ]} 10

11 Telescopic versus Folded Cascode 11

12 Example Folded-Cascode Op Amp 12

13 Single-Ended Output Cascode Op Amps 13

14 Triple Cascode A v app. (g m r o ) 3 /2 Limited Output Swing Complex biasing 14

15 Output Impedance Enhancement R = out A g r r 1 m2 o2 o1 15

16 Gain Boosting in Cascode Stage 16

17 Differential Gain Boosting 17

18 Differential Gain Boosting 18

19 Differential Gain Boosting 19

20 Two-Stage Op Amps 20

21 Single-Ended Output Two-Stage Op Amp 21

22 Two-Stage CMOS Opamp Popular opamp design approach A good example to review many important design concepts Output buffer is typically used to drive resistive loads For capacitive loads (typical case in CMOS) buffer is not required. C c V in A 1 A 2 1 V out Differential input stage Second gain stage Output buffer 22

23 Two-Stage CMOS Opamp Example 23

24 First Stage Differential to single-ended Gain of the Opamp Second Stage Common-source stage Output buffer is not required when driving capacitive loads 24

25 Gain of the Opamp Third Stage Source follower Typical gain: between 0.7 to1 Note: g o =1/r o and G L =1/R L g mb is body-effect conductance (is zero if source can be tied to substrate) 25

26 V bias Q5 300 Frequency Response v in+ v in Q Q2 v 1 C C v 2 A A2 A3 v out 150 Q3 Q4 i = g m1 v in C eq = C C ( 1 + A 2 ) 26

27 Frequency Response Simplifying assumptions: C C dominates Ignore Q 16 for the time being (it is used for lead compensation) Miller effect results in At midband frequencies 27

28 Overall gain (assuming A 3 1) Frequency Response which results in a unity-gain frequency of Note: ω ta is directly proportional to g m1 and inversely proportional to C C. 28

29 First-order model Frequency Response 20log( A 1 A 2 ) Gain 20 db/decade (db) ω ta g m1 C C 0 Freq ω p1 ω ta (log) ω p1 Phase (degrees) 0 Freq 90 ω ta (log)

30 Slew Rate Maximum rate of output change when input signal is large. V bias Q5 300 v in+ v in Q Q2 v 1 C C v i = g m1 v in A2 A3 v out Q3 Q4 All the bias current of Q5 goes either into Q1 or Q2. A

31 Slew Rate 31

32 Slew Rate Normally, the designer has not much control overω ta Slew-rate can be increased by increasing V eff1 This is one of the reasons for using p-channel input stage: higher slew-rate 32

33 Systematic Offset Voltage To ensure inherent (systematic) offset voltage does not exist, nominal current through Q7 should equal to that of Q6 when the differential input is zero. V bias Q5 300 I bias V DD Q6 300 Q1 Q2 V in V in+ Vout Q3 Q4 V SS Q7 33

34 Systematic Offset Voltage Avoid systematic offset by choosing: Found by noting and then setting 34

35 N-Channel versus P-Channel Input Stage Complimentary opamp can be designed with an n-channel input differential pair and p-channel second-stage Overall gain would be roughly the same in both designs P-channel Advantages Higher slew-rate: for fixed bias current, V eff is larger (assuming similar widths used for maximum gain) Higher frequency of operation: higher transconductance of second stage which results in higher unity-gain frequency Lower 1/f noise: holes less likely to be trapped; p-channel transistors have lower 1/f noise N-channel source follower is preferable (less voltage drop and higher g m ) N-channel Advantage Lower thermal noise thermal noise is lowered by high transconductance of first stage 35

36 Feedback and Opamp Compensation Y X ( s) = H ( s) 1+ βh ( s) Feedback systems may oscillate The following two are the oscillation conditions: βh ( jω) = 1 βh ( jω) =

37 Stable and Unstable Systems 37

38 Time-domain response of a feedback system 38

39 One-pole system H ( s) = A0 1+ s ω 0 Y X ( s) = A βa0 s 1+ ω 1+ βa 0 ( ) 0 S p ( β ) = ω 0 1+ A 0 Bode plot of the Loop gain 39

40 Multi-pole system ω > ω 0.1 p2 10 p1 Bode plot of the Loop gain 40

41 Phase Margin Loop Gain -20 db/decade (db) 20log ( LG( jω) ) 0 ω p 1 ω t Freq (log) GM (gain margin) Phase Loop Gain 0 ω p 1 ω t Freq (log) (degrees) PM (phase margin) 41

42 Phase Margin βh( ω 1 ) = 1 e j175 Y X ( s) = 11.5 β Closed loop frequency response 42

43 Phase Margin (Cont.) PM = βh( ωgx ) Phase Margin = 45 43

44 Phase Margin (Cont.) Phase Margin = 45 44

45 Phase Margin (Cont.) At PM = 60 o results in a small overshoot in the step response. If we increase PM, the system will be more stable but the time response slows down. 45

46 Frequency Compensation Push phase crossing point out Push gain crossing point in 46

47 Telescopic Opamp (single-ended) -example 47

48 Compensation (Cont.) Assume we need a phase margin of 45 o (usually inadequate) and other non-dominant poles are at high frequency. 48

49 Compensation of a two-stage opamp Miller Effect C eq = C E + (1+ A v 2 )C C f pe = 1 2πR out [C E + (1+ A v 2 )C C ] 49

50 Compensating Two-Stage Opamps V bias1 Q5 300 V DD Q6 300 Q1 Q2 V in V in+ V out2 V bias2 Q16 Cc Q3 Q4 Q7 50

51 Compensating Two-Stage Opamps v 1 R C C C g v R g v m1 in 1 C 1 m7 1 R 2 C 2 Q16 has V DS16 = 0 therefore it is hard in the triode region. Small signal analysis: without R C, a right-half plane zero occurs and worsens the phase-margin. 51

52 Compensating Two-Stage Opamps Using R C (through Q16) places zero at Zero moved to left-half plane to aid compensation Good practical choice is satisfied by letting 52

53 Design Procedure Design example: Find C C with R C =0 for a 55 o phase margin Arbitrarily choose C C =1pF and set R C =0 Using SPICE, find frequency ω t where a 125 phase shift exists, define gain as A Choose new C C soω t becomes unity-gain frequency of the loop gain, resulting in a 55 o phase margin. Achieved by setting C C =C C A Might need to iterate on C C a couple of times using SPICE 53

54 Next: Choose R C according to Design Procedure Increasingω t by about 20 percent, leaves zero near finalω t Check that gain continues to decrease at frequencies above the newω t Next: If phase margin is not adequate, increase C C while leaving R C constant. 54

55 Next: Replace R C by a transistor Design Procedure SPICE can be used for iteration to fine-tune the device dimensions and optimize the phase margin. 55

56 Process and Temperature Independence Can show non-dominant pole is roughly given by Recall zero given by If R C tracks inverse of g m7 then zero will trackω p2 : 56

57 Process and Temperature Independence Need to ensure V eff16 /V eff7 is independent of process and temperature variations V bias Q11 25 Q6 300 Q12 25 Q13 V a 25 V b Q16 V b C C 300 Q7 First set V eff13 =V eff7 which makes V a =V b 57

58 Process and Temperature Independence 58

59 Stable Transconductance Biasing 59

60 Stable Transconductance Biasing Transconductance of Q 13 (to the first order) is determined by geometric ratios only. Independent of power-supply voltages, process parameters, temperature, etc. For special case (W/L) 15 =4(W/L) 13 g m13 =1/R B Note that high-temperature will decrease mobility and hence increase effective gate-source voltages. Roughly 25% increase for 100 degree increase Requires a start-up circuit (might have all 0 currents) 60

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