EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design


 Elfreda Banks
 1 years ago
 Views:
Transcription
1 EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design References: Analog Integrated Circuit Design by D. Johns and K. Martin and Design of Analog CMOS Integrated Circuits by B. Razavi All figures in this set of slides are taken from the above books Shahriar Mirabbasi Department of Electrical and Computer Engineering University of British Columbia 1
2 Gain Smallsignal bandwidth Largesignal performance Output swing Input commonmode range Linearity Noise/offset Supply rejection General Considerations 2
3 OneStage Op Amps 3
4 OneStage Op Amp in Unity Gain Configuration 4
5 Cascode Op Amps 5
6 Unity Gain One Stage Cascode 6
7 Folded Cascode Op Amps 7
8 Folded Cascode Stages 8
9 Folded Cascode (cont.) 9
10 Folded Cascode (cont.) A v g m1 {[(g m 3 + g mb3 )r o3 (r o1 r o5 )] [(g m 7 + g mb 7 )r o7 r o9 ]} 10
11 Telescopic versus Folded Cascode 11
12 Example FoldedCascode Op Amp 12
13 SingleEnded Output Cascode Op Amps 13
14 Triple Cascode A v app. (g m r o ) 3 /2 Limited Output Swing Complex biasing 14
15 Output Impedance Enhancement R = out A g r r 1 m2 o2 o1 15
16 Gain Boosting in Cascode Stage 16
17 Differential Gain Boosting 17
18 Differential Gain Boosting 18
19 Differential Gain Boosting 19
20 TwoStage Op Amps 20
21 SingleEnded Output TwoStage Op Amp 21
22 TwoStage CMOS Opamp Popular opamp design approach A good example to review many important design concepts Output buffer is typically used to drive resistive loads For capacitive loads (typical case in CMOS) buffer is not required. C c V in A 1 A 2 1 V out Differential input stage Second gain stage Output buffer 22
23 TwoStage CMOS Opamp Example 23
24 First Stage Differential to singleended Gain of the Opamp Second Stage Commonsource stage Output buffer is not required when driving capacitive loads 24
25 Gain of the Opamp Third Stage Source follower Typical gain: between 0.7 to1 Note: g o =1/r o and G L =1/R L g mb is bodyeffect conductance (is zero if source can be tied to substrate) 25
26 V bias Q5 300 Frequency Response v in+ v in Q Q2 v 1 C C v 2 A A2 A3 v out 150 Q3 Q4 i = g m1 v in C eq = C C ( 1 + A 2 ) 26
27 Frequency Response Simplifying assumptions: C C dominates Ignore Q 16 for the time being (it is used for lead compensation) Miller effect results in At midband frequencies 27
28 Overall gain (assuming A 3 1) Frequency Response which results in a unitygain frequency of Note: ω ta is directly proportional to g m1 and inversely proportional to C C. 28
29 Firstorder model Frequency Response 20log( A 1 A 2 ) Gain 20 db/decade (db) ω ta g m1 C C 0 Freq ω p1 ω ta (log) ω p1 Phase (degrees) 0 Freq 90 ω ta (log)
30 Slew Rate Maximum rate of output change when input signal is large. V bias Q5 300 v in+ v in Q Q2 v 1 C C v i = g m1 v in A2 A3 v out Q3 Q4 All the bias current of Q5 goes either into Q1 or Q2. A
31 Slew Rate 31
32 Slew Rate Normally, the designer has not much control overω ta Slewrate can be increased by increasing V eff1 This is one of the reasons for using pchannel input stage: higher slewrate 32
33 Systematic Offset Voltage To ensure inherent (systematic) offset voltage does not exist, nominal current through Q7 should equal to that of Q6 when the differential input is zero. V bias Q5 300 I bias V DD Q6 300 Q1 Q2 V in V in+ Vout Q3 Q4 V SS Q7 33
34 Systematic Offset Voltage Avoid systematic offset by choosing: Found by noting and then setting 34
35 NChannel versus PChannel Input Stage Complimentary opamp can be designed with an nchannel input differential pair and pchannel secondstage Overall gain would be roughly the same in both designs Pchannel Advantages Higher slewrate: for fixed bias current, V eff is larger (assuming similar widths used for maximum gain) Higher frequency of operation: higher transconductance of second stage which results in higher unitygain frequency Lower 1/f noise: holes less likely to be trapped; pchannel transistors have lower 1/f noise Nchannel source follower is preferable (less voltage drop and higher g m ) Nchannel Advantage Lower thermal noise thermal noise is lowered by high transconductance of first stage 35
36 Feedback and Opamp Compensation Y X ( s) = H ( s) 1+ βh ( s) Feedback systems may oscillate The following two are the oscillation conditions: βh ( jω) = 1 βh ( jω) =
37 Stable and Unstable Systems 37
38 Timedomain response of a feedback system 38
39 Onepole system H ( s) = A0 1+ s ω 0 Y X ( s) = A βa0 s 1+ ω 1+ βa 0 ( ) 0 S p ( β ) = ω 0 1+ A 0 Bode plot of the Loop gain 39
40 Multipole system ω > ω 0.1 p2 10 p1 Bode plot of the Loop gain 40
41 Phase Margin Loop Gain 20 db/decade (db) 20log ( LG( jω) ) 0 ω p 1 ω t Freq (log) GM (gain margin) Phase Loop Gain 0 ω p 1 ω t Freq (log) (degrees) PM (phase margin) 41
42 Phase Margin βh( ω 1 ) = 1 e j175 Y X ( s) = 11.5 β Closed loop frequency response 42
43 Phase Margin (Cont.) PM = βh( ωgx ) Phase Margin = 45 43
44 Phase Margin (Cont.) Phase Margin = 45 44
45 Phase Margin (Cont.) At PM = 60 o results in a small overshoot in the step response. If we increase PM, the system will be more stable but the time response slows down. 45
46 Frequency Compensation Push phase crossing point out Push gain crossing point in 46
47 Telescopic Opamp (singleended) example 47
48 Compensation (Cont.) Assume we need a phase margin of 45 o (usually inadequate) and other nondominant poles are at high frequency. 48
49 Compensation of a twostage opamp Miller Effect C eq = C E + (1+ A v 2 )C C f pe = 1 2πR out [C E + (1+ A v 2 )C C ] 49
50 Compensating TwoStage Opamps V bias1 Q5 300 V DD Q6 300 Q1 Q2 V in V in+ V out2 V bias2 Q16 Cc Q3 Q4 Q7 50
51 Compensating TwoStage Opamps v 1 R C C C g v R g v m1 in 1 C 1 m7 1 R 2 C 2 Q16 has V DS16 = 0 therefore it is hard in the triode region. Small signal analysis: without R C, a righthalf plane zero occurs and worsens the phasemargin. 51
52 Compensating TwoStage Opamps Using R C (through Q16) places zero at Zero moved to lefthalf plane to aid compensation Good practical choice is satisfied by letting 52
53 Design Procedure Design example: Find C C with R C =0 for a 55 o phase margin Arbitrarily choose C C =1pF and set R C =0 Using SPICE, find frequency ω t where a 125 phase shift exists, define gain as A Choose new C C soω t becomes unitygain frequency of the loop gain, resulting in a 55 o phase margin. Achieved by setting C C =C C A Might need to iterate on C C a couple of times using SPICE 53
54 Next: Choose R C according to Design Procedure Increasingω t by about 20 percent, leaves zero near finalω t Check that gain continues to decrease at frequencies above the newω t Next: If phase margin is not adequate, increase C C while leaving R C constant. 54
55 Next: Replace R C by a transistor Design Procedure SPICE can be used for iteration to finetune the device dimensions and optimize the phase margin. 55
56 Process and Temperature Independence Can show nondominant pole is roughly given by Recall zero given by If R C tracks inverse of g m7 then zero will trackω p2 : 56
57 Process and Temperature Independence Need to ensure V eff16 /V eff7 is independent of process and temperature variations V bias Q11 25 Q6 300 Q12 25 Q13 V a 25 V b Q16 V b C C 300 Q7 First set V eff13 =V eff7 which makes V a =V b 57
58 Process and Temperature Independence 58
59 Stable Transconductance Biasing 59
60 Stable Transconductance Biasing Transconductance of Q 13 (to the first order) is determined by geometric ratios only. Independent of powersupply voltages, process parameters, temperature, etc. For special case (W/L) 15 =4(W/L) 13 g m13 =1/R B Note that hightemperature will decrease mobility and hence increase effective gatesource voltages. Roughly 25% increase for 100 degree increase Requires a startup circuit (might have all 0 currents) 60
EE 501 Lab 4 Design of two stage op amp with miller compensation
EE 501 Lab 4 Design of two stage op amp with miller compensation Objectives: 1. Design a two stage op amp 2. Investigate how to miller compensate a twostage operational amplifier. Tasks: 1. Build a twostage
More informationAnalysis and Design of Analog Integrated Circuits Lecture 20. Advanced Opamp Topologies (Part II)
Analysis and Design of Analog Integrated Circuits Lecture 20 Advanced Opamp Topologies (Part II) Michael H. Perrott April 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Outline of Lecture
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
Low power OTA 1 TwoStage, Miller Op Amp Operating in Weak Inversion Low frequency response: gm1 gm6 Av 0 g g g g A v 0 ds2 ds4 ds6 ds7 I D m, ds D nvt g g I n GB and SR: GB 1 1 n 1 2 4 6 6 7 g 2 2 m1
More informationChapter 12 Opertational Amplifier Circuits
1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS opamp architectures: the twostage circuit and the singlestage, folded cascode circuit.
More informationYou will be asked to make the following statement and provide your signature on the top of your solutions.
1 EE 435 Name Exam 1 Spring 216 Instructions: The points allocated to each problem are as indicated. Note that the first and last problem are weighted more heavily than the rest of the problems. On those
More informationAnalog Integrated Circuits Fundamental Building Blocks
Analog Integrated Circuits Fundamental Building Blocks Basic OTA/Opamp architectures Faculty of Electronics Telecommunications and Information Technology Gabor Csipkes Bases of Electronics Department Outline
More informationAdvanced Operational Amplifiers
IsLab Analog Integrated Circuit Design OPA247 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA21 Advanced Current Mirrors and Opamps Twostage
More informationDesign of HighSpeed OpAmps for Signal Processing
Design of HighSpeed OpAmps for Signal Processing R. Jacob (Jake) Baker, PhD, PE Professor and Chair Boise State University 1910 University Dr. Boise, ID 837252075 jbaker@ieee.org Abstract  As CMOS
More informationINF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation
INF3410 Fall 2015 Book Chapter 6: Basic Opamp Design and Compensation content Introduction Two Stage Opamps Compensation Slew Rate Systematic Offset Advanced Current Mirrors Operational Transconductance
More informationLecture 300 Low Voltage Op Amps (3/28/10) Page 3001
Lecture 300 Low Voltage Op Amps (3/28/10) Page 3001 LECTURE 300 LOW VOLTAGE OP AMPS LECTURE ORGANIZATION Outline Introduction Low voltage input stages Low voltage gain stages Low voltage bias circuits
More informationA Compact Foldedcascode Operational Amplifier with ClassAB Output Stage
A Compact Foldedcascode Operational Amplifier with ClassAB Output Stage EEE 523 Advanced Analog Integrated Circuits Project Report Fuding Ge You are an engineer who is assigned the project to design
More informationWhat is the typical voltage gain of the basic two stage CMOS opamp we studied? (i) 20dB (ii) 40dB (iii) 80dB (iv) 100dB
Department of Electronic ELEC 5808 (ELG 6388) Signal Processing Electronics Final Examination Dec 14th, 2010 5:30PM  7:30PM R. Mason answer all questions one 8.5 x 11 crib sheets allowed 1. (5 points)
More informationBasic OpAmp Design and Compensation. Chapter 6
Basic OpAmp Design and Compensation Chapter 6 6.1 OpAmp applications Typical applications of OpAmps in analog integrated circuits: (a) Amplification and filtering (b) Biasing and regulation (c) Switchedcapacitor
More informationECEN 474/704 Lab 8: TwoStage Miller Operational Amplifier
ECEN 474/704 Lab 8: TwoStage Miller Operational Amplifier Objective Design, simulate and test a twostage operational amplifier Introduction Operational amplifiers (opamp) are essential components of
More informationIndex. SmallSignal Models, 14 saturation current, 3, 5 Transistor Cutoff Frequency, 18 transconductance, 16, 22 transit time, 10
Index A absolute value, 308 additional pole, 271 analog multiplier, 190 B BiCMOS,107 Bode plot, 266 baseemitter voltage, 16, 50 baseemitter voltages, 296 bias current, 111, 124, 133, 137, 166, 185 bipolar
More informationOperational Amplifiers
CHAPTER 9 Operational Amplifiers Analog IC Analysis and Design 9 ChihCheng Hsieh Outline. General Consideration. OneStage Op Amps / TwoStage Op Amps 3. Gain Boosting 4. CommonMode Feedback 5. Input
More informationMicroelectronic Circuits II. Ch 10 : OperationalAmplifier Circuits
Microelectronic Circuits II Ch 0 : OperationalAmplifier Circuits 0. The Twostage CMOS Op Amp 0.2 The FoldedCascode CMOS Op Amp CNU EE 0. OperationalAmplifier Introduction  Analog ICs : operational
More informationINF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation
INF3410 Fall 2013 Compensation content Introduction Two Stage Opamps Compensation Slew Rate Systematic Offset Advanced Current Mirrors Operational Transconductance Amplifiers Current Mirror Opamps Folded
More informationPURPOSE: NOTE: Be sure to record ALL results in your laboratory notebook.
EE4902 Lab 9 CMOS OPAMP PURPOSE: The purpose of this lab is to measure the closedloop performance of an opamp designed from individual MOSFETs. This opamp, shown in Fig. 91, combines all of the major
More informationIOWA STATE UNIVERSITY. EE501 Project. Fully Differential MultiStage OpAmp Design. Ryan Boesch 11/12/2008
IOWA STATE UNIVERSITY EE501 Project Fully Differential MultiStage OpAmp Design Ryan Boesch 11/12/2008 This report documents the design, simulation, layout, and postlayout simulation of a fully differential
More informationAnalysis and Design of Analog Integrated Circuits Lecture 18. Key Opamp Specifications
Analysis and Design of Analog Integrated Circuits Lecture 8 Key Opamp Specifications Michael H. Perrott April 8, 0 Copyright 0 by Michael H. Perrott All rights reserved. Recall: Key Specifications of Opamps
More informationChapter 10 Feedback ECE 3120 Microelectronics II Dr. Suketu Naik
1 Chapter 10 Feedback Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: ActiveLoaded Differential Pair 4. Ch 10: Feedback 5. Ch 11: Output
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN OPAMP DESIGN AND SIMULATION Vishal Saxena OPAMP DESIGN PROJECT R 2 v out v in /2 R 1 C L v in v out V CM R L V CM C L V CM v in /2 R 1 C L (a) (b) R 2 ECE415/EO
More informationHomework Assignment 10
Homework Assignment 10 Question The amplifier below has infinite input resistance, zero output resistance and an openloop gain. If, find the value of the feedback factor as well as so that the closedloop
More informationDesign of Miller Compensated TwoStage Operational Amplifier for Data Converter Applications
Design of Miller Compensated TwoStage Operational Amplifier for Data Converter Applications Prema Kumar. G Shravan Kudikala Casest, School Of Physics Casest, School Of Physics University Of Hyderabad
More informationLecture 2: NonIdeal Amps and OpAmps
Lecture 2: NonIdeal Amps and OpAmps Prof. Ali M. Niknejad Department of EECS University of California, Berkeley Practical OpAmps Linear Imperfections: Finite openloop gain (A 0 < ) Finite input resistance
More informationTWO AND ONE STAGES OTA
TWO AND ONE STAGES OTA F. Maloberti Department of Electronics Integrated Microsystem Group University of Pavia, 7100 Pavia, Italy franco@ele.unipv.it tel. +393850505; fax. +39038505677 474 EE Department
More informationCurrent Mirrors. Prof. TaiHaur Kuo, EE, NCKU, Tainan City, Taiwan 41
Current Mirrors Prof. TaiHaur Kuo, EE, NCKU, Tainan City, Taiwan 4 郭泰豪, Analog C Design, 08 { Prof. TaiHaur Kuo, EE, NCKU, Tainan City, Taiwan 4 郭泰豪, Analog C Design, 08 { Current Source and Sink Symbol
More informationA 16Ω Audio Amplifier with 93.8 mw Peak loadpower and 1.43 quiscent power consumption
A 16Ω Audio Amplifier with 93.8 mw Peak loadpower and 1.43 quiscent power consumption IEEE Transactions on circuits and systems Vol 59 No:3 March 2012 Abstract A class AB audio amplifier is used to drive
More informationHomework Assignment EE 435 Homework 4 Spring 2014 Due Wednesday Feb 26
Homework Assignment EE 435 Homework 4 Spring 2014 Due Wednesday Feb 26 In the following problems, if reference to a semiconductor process is needed, assume processes with the following characteristics:
More informationDesign for MOSIS Education Program
Design for MOSIS Education Program (Research) T46CAE Project Title Low Voltage Analog Building Block Prepared by: C. Durisety, S. Chen, B. Blalock, S. Islam Institution: Department of Electrical and Computer
More informationRevision History. Contents
Revision History Ver. # Rev. Date Rev. By Comment 0.0 9/15/2012 Initial draft 1.0 9/16/2012 Remove class A part 2.0 9/17/2012 Comments and problem 2 added 3.0 10/3/2012 cmdmprobe resimulation, add supplement
More informationCSE 577 Spring Insoo Kim, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Penn State University
CSE 577 Spring 2011 Basic Amplifiers and Differential Amplifier, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Penn State University Don t let the computer
More informationETIN25 Analogue IC Design. Laboratory Manual Lab 2
Department of Electrical and Information Technology LTH ETIN25 Analogue IC Design Laboratory Manual Lab 2 Jonas Lindstrand Martin Liliebladh Markus Törmänen September 2011 Laboratory 2: Design and Simulation
More informationECEN 474/704 Lab 6: Differential Pairs
ECEN 474/704 Lab 6: Differential Pairs Objective Design, simulate and layout various differential pairs used in different types of differential amplifiers such as operational transconductance amplifiers
More informationSensors & Transducers Published by IFSA Publishing, S. L.,
Sensors & Transducers Published by IFSA Publishing, S. L., 208 http://www.sensorsportal.com Fully Differential Operation Amplifier Using Self Cascode MOSFET Structure for High Slew Rate Applications Kalpraj
More informationBasic OpAmp Design and Compensation. Chapter 6
Basic OpAmp Design and Compensation Chapter 6 6.1 OpAmp applications Typical applications of OpAmps in analog integrated circuits: (a) Amplification and filtering (b) Biasing and regulation (c) Switchedcapacitor
More informationChapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier
Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in doubleended
More informationG m /I D based Three stage Operational Amplifier Design
G m /I D based Three stage Operational Amplifier Design Rishabh Shukla SVNIT, Surat shuklarishabh31081988@gmail.com Abstract A nested GmC compensated three stage Operational Amplifier is reviewed using
More informationSolid State Devices & Circuits. 18. Advanced Techniques
ECE 442 Solid State Devices & Circuits 18. Advanced Techniques Jose E. SchuttAine Electrical l&c Computer Engineering i University of Illinois jschutt@emlab.uiuc.edu 1 Darlington Configuration  Popular
More informationUniversity of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1. A High Speed Operational Amplifier
University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1 A High Speed Operational Amplifier A. Halim ElSaadi, Mohammed ElTanani, University of Michigan Abstract This paper
More information[Kumar, 2(9): September, 2013] ISSN: Impact Factor: 1.852
IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY Design and Performance analysis of Low power CMOS OpAmp Anand Kumar Singh *1, Anuradha 2, Dr. Vijay Nath 3 *1,2 Department of
More informationECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers
ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic
More informationBUCK Converter Control Cookbook
BUCK Converter Control Cookbook Zach Zhang, Alpha & Omega Semiconductor, Inc. A Buck converter consists of the power stage and feedback control circuit. The power stage includes power switch and output
More informationA Unity Gain FullyDifferential 10bit and 40MSps SampleAndHold Amplifier in 0.18μm CMOS
A Unity Gain FullyDifferential 0bit and 40MSps SampleAndHold Amplifier in 0.8μm CMOS Sanaz Haddadian, and Rahele Hedayati Abstract A 0bit, 40 MSps, sample and hold, implemented in 0.8μm CMOS technology
More informationYou will be asked to make the following statement and provide your signature on the top of your solutions.
1 EE 435 Name Exam 1 Spring 2018 Instructions: The points allocated to each problem are as indicated. Note that the first and last problem are weighted more heavily than the rest of the problems. On those
More informationd. Can you find intrinsic gain more easily by examining the equation for current? Explain.
EECS140 Final Spring 2017 Name SID 1. [8] In a vacuum tube, the plate (or anode) current is a function of the plate voltage (output) and the grid voltage (input). I P = k(v P + µv G ) 3/2 where µ is a
More informationLecture 240 Cascode Op Amps (3/28/10) Page 2401
Lecture 240 Cascode Op Amps (3/28/10) Page 2401 LECTURE 240 CASCODE OP AMPS LECTURE ORGANIZATION Outline Lecture Organization Single Stage Cascode Op Amps Two Stage Cascode Op Amps Summary CMOS Analog
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
OTAoutput buffer 1 According to the types of loads, the driving capability of the output stages differs. For switched capacitor circuits which have high impedance capacitive loads, class A output stage
More informationExperiment 1: Amplifier Characterization Spring 2019
Experiment 1: Amplifier Characterization Spring 2019 Objective: The objective of this experiment is to develop methods for characterizing key properties of operational amplifiers Note: We will be using
More informationA new class AB foldedcascode operational amplifier
A new class AB foldedcascode operational amplifier Mohammad Yavari a) Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran a) myavari@aut.ac.ir
More informationECEN 474/704 Lab 7: Operational Transconductance Amplifiers
ECEN 474/704 Lab 7: Operational Transconductance Amplifiers Objective Design, simulate and layout an operational transconductance amplifier. Introduction The operational transconductance amplifier (OTA)
More informationOpAmp Design Project EE 5333 Analog Integrated Circuits Prof. Ramesh Harjani Department of ECE University of Minnesota, Twin Cities Report prepared
OpAmp Design Project EE 5333 Analog Integrated Circuits Prof. Ramesh Harjani Department of ECE University of Minnesota, Twin Cities Report prepared by: Nirav Desai (4280229) 1 Contents: 1. Design Specifications
More informationBasic Circuits. Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair,
Basic Circuits Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair, CCS  Basic Circuits P. Fischer, ZITI, Uni Heidelberg, Seite 1 Reminder: Effect of Transistor Sizes Very crude classification:
More informationHomework Assignment 11
Homework Assignment 11 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =
More informationDESIGN OF A FULLY DIFFERENTIAL HIGHSPEED HIGHPRECISION AMPLIFIER
DESIGN OF A FULLY DIFFERENTIAL HIGHSPEED HIGHPRECISION AMPLIFIER Mayank Gupta mayank@ee.ucla.edu N. V. Girish envy@ee.ucla.edu Design I. Design II. University of California, Los Angeles EE215A Term Project
More informationAnalog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem
Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem A report Submitted to Canopus Systems Inc. Zuhail Sainudeen and Navid Yazdi Arizona State University July 2001 1. Overview
More informationToday s topic: frequency response. Chapter 4
Today s topic: frequency response Chapter 4 1 Smallsignal analysis applies when transistors can be adequately characterized by their operating points and small linear changes about the points. The use
More informationMultimode 2.4 GHz FrontEnd with Tunable g m C Filter. Group 4: Nick Collins Trevor Hunter Joe Parent EECS 522 Winter 2010
Multimode 2.4 GHz FrontEnd with Tunable g m C Filter Group 4: Nick Collins Trevor Hunter Joe Parent EECS 522 Winter 2010 Overview Introduction Complete System LNA Mixer GmC filter Conclusion Introduction
More informationPerformance Evaluation of Different Types of CMOS Operational Transconductance Amplifier
Performance Evaluation of Different Types of CMOS Operational Transconductance Amplifier Kalpesh B. Pandya 1, Kehul A. shah 2 1 Gujarat Technological University, Department of Electronics & Communication,
More informationESE319 Introduction to Microelectronics High Frequency BJT Model & Cascode BJT Amplifier
High Frequency BJT Model & Cascode BJT Amplifier 1 Gain of 10 Amplifier Nonideal Transistor C in R 1 V CC R 2 v s Gain starts dropping at > 1MHz. Why! Because of internal transistor capacitances that
More informationOperational Amplifier (OPAMP)
Operational Amplifier (OPAMP) Analog Cs nclude Operational Amplifier Filters AnalogtoDigital Converter (ADC) DigitaltoAnalog Converter (DAC) Analog Modulator PhaseLocked Loop Analog Multiplier Others
More informationVoltage Feedback Op Amp (VFOpAmp)
Data Sheet Voltage Feedback Op Amp (VFOpAmp) Features 55 db dc gain 30 ma current drive Less than 1 V head/floor room 300 V/µs slew rate Capacitive load stable 40 kω input impedance 300 MHz unity gain
More informationCMOS OperationalAmplifier
CMOS OperationalAmplifier 1 What will we learn in this course How to design a good OP Amp. Basic building blocks Biasing and Loading Swings and Bandwidth CH2(8) Operational Amplifier as A Black Box Copyright
More informationPerformance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design
RESEARCH ARTICLE OPEN ACCESS Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design Ankush S. Patharkar*, Dr. Shirish M. Deshmukh** *(Department of Electronics and Telecommunication,
More informationCMOS OperationalAmplifier
CMOS OperationalAmplifier 1 What will we learn in this course How to design a good OP Amp. Basic building blocks Biasing and Loading Swings and Bandwidth CH2(8) Operational Amplifier as A Black Box Copyright
More informationLECTURE 19 DIFFERENTIAL AMPLIFIER
Lecture 19 Differential Amplifier (6/4/14) Page 191 LECTURE 19 DIFFERENTIAL AMPLIFIER LECTURE ORGANIZATION Outline Characterization of a differential amplifier Differential amplifier with a current mirror
More informationDesign Analysis and Performance Comparison of Low Power High Gain 2nd Stage Differential Amplifier Along with 1st Stage
Design Analysis and Performance Comparison of Low Power High Gain 2nd Stage Differential Amplifier Along with 1st Stage Sadeque Reza Khan Department of Electronic and Communication Engineering, National
More informationHOME ASSIGNMENT. Figure.Q3
HOME ASSIGNMENT 1. For the differential amplifier circuit shown below in figure.q1, let I=1 ma, V CC =5V, v CM = 2V, R C =3kΩ and β=100. Assume that the BJTs have v BE =0.7 V at i C =1 ma. Find the voltage
More informationAnalog Integrated Circuits. Lecture 7: OpampDesign
Analog Integrated Circuits Lecture 7: OpampDesign ELC 601 Fall 2013 Dr. Ahmed Nader Dr. Mohamed M. Aboudina anader@ieee.org maboudina@gmail.com Department of Electronics and Communications Engineering
More informationAdvanced OPAMP Design
Advanced OPAMP Design Two Stage OPAMP with Cascoding To increase the gain, the idea of cascoding can be combined with the idea of cascading. A two stage amplifier with one stage being cascode is possible.
More information250 MHz CMOS RailtoRail IO OpAmp: Structural Design Approach. Texas Instruments Inc. Tucson (former BurrBrown Inc.)
250 MHz CMOS RailtoRail IO OpAmp: Structural Design Approach Vadim Ivanov Shilong Zhang Texas Instruments Inc. Tucson (former BurrBrown Inc.) Overview Basics of the structural design approach Amplifiers
More informationANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS
ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,
More informationLecture 110 Intro. and Characterization of the Op Amp (1/28/02) Page 1101
Lecture 110 Intro. and Characterization of the Op Amp (1/28/02) Page 1101 LECTURE 110 INTRODUCTION AND CHARACTERIZATION OF THE OP AMP (READING: GHLM 404424, AH 243249) Objective The objective of this presentation
More informationComparative Analysis of Compensation Techniques for improving PSRR of an OPAMP
Comparative Analysis of Compensation Techniques for improving PSRR of an OPAMP 1 Pathak Jay, 2 Sanjay Kumar M.Tech VLSI and Embedded System Design, Department of School of Electronics, KIIT University,
More informationCHAPTER 4 ULTRA WIDE BAND LOW NOISE AMPLIFIER DESIGN
93 CHAPTER 4 ULTRA WIDE BAND LOW NOISE AMPLIFIER DESIGN 4.1 INTRODUCTION Ultra Wide Band (UWB) system is capable of transmitting data over a wide spectrum of frequency bands with low power and high data
More informationAnalog Design Kevin Aylward B.Sc. Operational Amplifier Design Miller And Cascode Compensation
Analog Design Kevin Aylward B.Sc. Operational Amplifier Design Miller And Cascode Compensation Back to Contents Overview This paper presents an operational amplifier design example which forms a rebuttal
More informationA CMOS LowVoltage, HighGain OpAmp
A CMOS LowVoltage, HighGain OpAmp G N Lu and G Sou LEAM, Université Pierre et Marie Curie Case 203, 4 place Jussieu, 75252 Paris Cedex 05, France Telephone: (33 1) 44 27 75 11 Fax: (33 1) 44 27 48 37
More information6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers
6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott Broadband Communication
More informationDesign of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching
RESEARCH ARTICLE OPEN ACCESS Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching Annu Saini, Prity Yadav (M.Tech. Student, Department
More informationDESIGN HIGH SPEED, LOW NOISE, LOW POWER TWO STAGE CMOS OPERATIONAL AMPLIFIER. Himanshu Shekhar* 1, Amit Rajput 1
ISSN 22772685 IJESR/June 2014/ Vol4/Issue6/319323 Himanshu Shekhar et al./ International Journal of Engineering & Science Research DESIGN HIGH SPEED, LOW NOISE, LOW POWER TWO STAGE CMOS OPERATIONAL
More informationAnalysis and Design of Analog Integrated Circuits Lecture 8. Cascode Techniques
Analysis and Design of Analog Integrated Circuits Lecture 8 Cascode Techniques Michael H. Perrott February 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Review of Large Signal Analysis
More informationDesigning CMOS foldedcascode operational amplifier with flicker noise minimisation
Microelectronics Journal 32 (200) 69 73 Short Communication Designing CMOS foldedcascode operational amplifier with flicker noise minimisation P.K. Chan*, L.S. Ng, L. Siek, K.T. Lau Microelectronics Journal
More informationRail to Rail Input Amplifier with constant G M and High Unity Gain Frequency. Arun Ramamurthy, Amit M. Jain, Anuj Gupta
1 Rail to Rail Input Amplifier with constant G M and High Frequency Arun Ramamurthy, Amit M. Jain, Anuj Gupta Abstract A rail to rail input, 2.5V CMOS input amplifier is designed that amplifies uniformly
More informationECEN 5008: Analog IC Design. Final Exam
ECEN 5008 Initials: 1/10 ECEN 5008: Analog IC Design Final Exam Spring 2004 Instructions: 1. Exam Policy: Timelimited, 150minute exam. When the time is called, all work must stop. Put your initials on
More informationFinal Exam. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.1 μs. Estimate the 3 db bandwidth of the amplifier.
Final Exam Name: Score /100 Question 1 Short Takes 1 point each unless noted otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.1 μs. Estimate the 3 db bandwidth
More informationTechnologyIndependent CMOS Op Amp in Minimum Channel Length
TechnologyIndependent CMOS Op Amp in Minimum Channel Length A Thesis Presented to The Academic Faculty by Susanta Sengupta In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
More information6.776 High Speed Communication Circuits Lecture 7 High Freqeuncy, Broadband Amplifiers
6.776 High Speed Communication Circuits Lecture 7 High Freqeuncy, Broadband Amplifiers Massachusetts Institute of Technology February 24, 2005 Copyright 2005 by HaeSeung Lee and Michael H. Perrott High
More informationDesign of Low Voltage Low Power CMOS OPAMP
RESEARCH ARTICLE OPEN ACCESS Design of Low Voltage Low Power CMOS OPAMP Shahid Khan, Prof. Sampath kumar V. Electronics & Communication department, JSSATE ABSTRACT Operational amplifiers are an integral
More informationA NOVEL MDAC SUITABLE FOR A 14B, 120MS/S ADC, USING A NEW FOLDED CASCODE OPAMP
A NOVEL MDAC SUITABLE FOR A 14B, 120MS/S ADC, USING A NEW FOLDED CASCODE OPAMP Noushin Ghaderi 1, Khayrollah Hadidi 2 and Bahar Barani 3 1 Faculty of Engineering, Shahrekord University, Shahrekord, Iran
More informationDesign of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits Behzad Razavi Professor of Electrical Engineering University of California, Los Angeles H Boston Burr Ridge, IL Dubuque, IA Madison, WI New York San Francisco
More informationPractical Testing Techniques For Modern Control Loops
VENABLE TECHNICAL PAPER # 16 Practical Testing Techniques For Modern Control Loops Abstract: New power supply designs are becoming harder to measure for gain margin and phase margin. This measurement is
More informationMicroelectronics Part 2: Basic analog CMOS circuits
GBM830 Dispositifs Médicaux Intelligents Microelectronics Part : Basic analog CMOS circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim!! http://www.cours.polymtl.ca/gbm830/! mohamad.sawan@polymtl.ca!
More informationDesign and Layout of Two Stage High Bandwidth Operational Amplifier
Design and Layout of Two Stage High Bandwidth Operational Amplifier Yasir Mahmood Qureshi Abstract This paper presents the design and layout of a two stage, high speed operational amplifiers using standard
More informationSystem on a Chip. Prof. Dr. Michael Kraft
System on a Chip Prof. Dr. Michael Kraft Lecture 4: Filters Filters General Theory Continuous Time Filters Background Filters are used to separate signals in the frequency domain, e.g. remove noise, tune
More informationTopology Selection: Input
Project #2: Design of an Operational Amplifier By: Adrian Ildefonso Nedeljko Karaulac I have neither given nor received any unauthorized assistance on this project. Process: Baker s 50nm CAD Tool: Cadence
More informationDesign of High Gain Two stage OpAmp using 90nm Technology
Design of High Gain Two stage OpAmp using 90nm Technology Shaik Aqeel 1, P. Krishna Deva 2, C. Mahesh Babu 3 and R.Ganesh 4 1 CVR College of Engineering/UG Student, Hyderabad, India 2 CVR College of Engineering/UG
More informationANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS
ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,
More informationPractical Testing Techniques For Modern Control Loops
Keywords Venable, frequency response analyzer, impedance, injection transformer, oscillator, feedback loop, Bode Plot, power supply design, gain margin, phase margin, step load testing, PWM chip APPLICATION
More informationDesign of a low voltage,low dropout (LDO) voltage cmos regulator
Design of a low,low dropout (LDO) cmos regulator Chaithra T S Ashwini Abstract In this paper a low, low dropout (LDO) regulator design procedure is proposed and implemented using 0.25 micron CMOS process.
More information