Operational Amplifier (OPAMP)

Transcription

1 Operational Amplifier (OPAMP) Analog Cs nclude Operational Amplifier Filters Analog-to-Digital Converter (ADC) Digital-to-Analog Converter (DAC) Analog Modulator Phase-Locked Loop Analog Multiplier Others Basic Building Blocks of Analog Cs Single-Stage Amplifier Differential Pairs Current Mirrors MOS Switches Others Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-

2 OPAMP design Operational Amplifier (Cont.) CMOS OPAMPs are adequate for LS implementation. Main stream Two-stage and folded-cascode OPAMPs will be introduced. Bipolar OPAMPs Can achieve better performance than CMOS OPAMPs. Less popular 74 OPAMP will be introduced. BiCMOS OPAMPs combine the advantages of bipolar and CMOS devices. Less popular First published by H. C. Lin in 960 s. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-2

3 CMOS Operational Amplifier (OPAMP) Two-stage guess, it is suitable for 50% of applications with OPAMPs. Folded-cascode guess, it is good for 20% applications. Others Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-3

4 Stability and Compensation of OPAMP Operational amplifier with negative feedback i β out in β A out A (s) in in out A vf i β out Av(s) (s) in out (s) i (s) A (s) v βa v (s) for A vf A v is closed loop gain is open loop gain βa v is loop gain Open-loop : always stable (no internal feedback) Closed-loop : stability depends on βa(s) Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-4

5 Stability and Compensation of OPAMP (Cont.) For stable system, the real part of all poles must be negative. Gain margin = 20 log βa v jω80 Unity-gain frequency ω u Phase Margin = βav(jωu ) 80 At least 45 o ~ 60 o (or larger) margin is preferred. This will also give a desirable (i.e., small or no ringing) step response for the closed-loop amplifier. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-5

6 CMOS Differential Stage with Active Load Used in CMOS technology Performs as a combination of differential gain stage and differential to single-ended converter Self-biased active load Model of A CM g r m,q out A A dm cm,g r CM ds2 g m,q2 // r m m3,g r A ds4 ds2 2 r ds0 2g r ds0 m,q3 // r g m3,g ds4 2g m,q4 // r ds // r ds3 r ds 2 r // r g r 0 dm m ds2 ds4 m3 ds Acm Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan v r 0-6 g // rds // rds3 ds0 m3 in v Q 3 Q 4 A Q Q 2 C r ds0 v o B v r ds0 GND DD out v in2

7 CMOS Differential Stage with Active Load (Cont.) With external bias bias load line ( large r O ) GND Why not? Quiescent point can t be determined Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-7

8 A0 A( s) ( s )( s A g P 0 m 0g m6 02 r Uncompensated Two-Stage CMOS OPAMP gm 2μCox(W L) M // r 0 ds2 ds4 02 rds 6//rds 7 P 0C P 2 02 C L v id P2 g m6 2μCox(W L) M6 ) 2 gm v id M 8 0 ref M M3 C M5 v A M4 M2 gm 6 v A C 02 DD M7 M6 GND 2 C L C L out out P & P2 are dominant poles since 0 and 02 are normally large. The effects of other poles are usually negligible. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-8

9 Uncompensated Two-Stage CMOS OPAMP (Cont.) For low frequency, For high frequency, A A jω A(0) g jω ω m m6 2 CC L Hence, for high frequency, the amplifier inverts the input voltage. f feedback is used, then positive feedback occurs. g i β out in β A out A (s) in Two dominant poles phase margin is not large enough pole-splitting technique to solve this problem Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-9

10 Offset oltage of Two-Stage CMOS OPAMPs nput voltage needed to restore the output to zero Two components Systematic offset andom offset M 5 bias To avoid systematic offset, design must follow the rule (W/L) (W/L) 2 M 3 M 5 (W/L) (W/L) M 6 M 7 (W/L) (W/L) M 4 M 5 CM (DC 0, AC=0) To minimize random offset L=L2, W=W2, L3=L4, W3=W4, L3=L6 and L5=L7 to minimize the offsets of channel length and channel width variations Large L and W such that L/L and W/W can be ignored M M 2 / 2 / 2 DD (DC 0, AC=0) 7 CM (DC 0, AC=0) 6 M 7 g M 3 M 4 M 6 CM (DC 0, AC=0) DC GND (DC=0, AC=0) Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-0

11 nput Common-Mode ange and Output Swing of Two-Stage CMOS OPAM nput common-mode range, CM Minimum CM To keep M and M2 in saturation, gd,2 < tn. Hence, CM CM O 3 DD tn SS - tp tn Maximum CM O 5 O 3 CM tp tp DD O where ov is effective or overdrive voltage To keep M5 and in saturation, ds5 > ov5. Hence, tp O O 5 Output swing, o To keep M6 and M7 in saturation O 6 v o DD O 7 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-

12 v Pole-Splitting of Two-Stage CMOS OPAMP reduce P and increase P 2 M M3 id M5 M4 M2 C C C C C includes Cgd 6 Cgd2 Cdb2 Cgd4 Cdb4 Cgs6 L Cdb6 Cdb7 Cgd 7 Cload gm v id GND 0 M7 C c M6 2 C C L v A0( s Z ) A( s) ( s )( s P A g P 0 m 0g m6 02 g m 2μCox(W L) M g m6 2μCox(W L) M rds2 // rds4 02 rds6//rds7 g m6 ωz f gm6 02 CC gm ωp ( gm602)cc0 A0C f CC & CL gm6cc g ωp2 C C C C C C C Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-2 DD A C C gm 6 v A L L 02 ight plane zero causes slower gain drop but quick phase drop out C C L C 2 ) L out C C m6

13 Pole-Splitting of Two-Stage CMOS OPAMP (Cont.) Unity-gain frequency f t (or f u ) f t A 0 P 2 2 g C m C 20 log A (db) 20 log A v To achieve a uniform -20dB/dec 0 gain rolloff down to 0dB, the following two conditions must be satisfied g Φ m g m6. f t f P2 0 CC C f º t f Z g m g m6-80 where G m =g m and G m2 =g º m6 f P Phase margin f t f P2 f Z f (log scale) f (log scale) At unity-gain frequency f t Φ total =tan - (f t /f P )+tan - (f t /f P2 )+tan - (f t /f z ), where tan - (f t /f P ) 90 Phase margin = 80 -Φ total =90 -tan - (f t /f P2 )-tan - (f t /f z ) Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-3 Electronics(3), 20

14 ight-plane Zero Causes slower gain drop but quick phase drop Usually moved away if phase margin is not large enough m e ω P2 g C m6 L ω P g AC m C ω Z g C m6 C gain, db Phase P Z P 2 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-4

15 ight-plane Zero (Cont.) The zero is due to the existence of two path through which the signal can propagate from node A to node B C C g m A g m6 B O C O 2 CL. through C C 2. through the controlled source g m6 A To eliminate zero ω z. Method- 2. Method-2 C C unity gain buffer CC Z A A 2 A A 2 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-5

16 Eliminating ight-plane Zero Method-: Using unity-gain buffer Zero moves to infinity or C C unity gain buffer A A 2 P2 P Zero moves to infinity Z A( s) s ( P A0 s )( P2 ) where ω P g A C 0 m C, ω P2 g C m6 L Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-6

17 Eliminating ight Plane Zero (Cont.) Method-2: Using instead of buffer a. eliminating zero, let b. pole-zero cancellation, let Z g m6 Z P2 CC Z P 2 gm A0C C gm6 CL ( C P P3 Z Z [ Z C ( g C m6 )] C C C L ) A P2 P A 2 Zero moves toward the left plane Z Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-7

18 Pole Separation vs. Phase Margin and Speed ω 2 nωu nβa0ω where ωu βa0ω n=2 phase margin=63 O fast (step response) n=3 phase margin=7 O n=4 phase margin=76 O βa 0 critically damped (step response) u 2 For n 2 For n 4 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-8

19 Slew ate Discussed in chapter 2 of the textbook by Smith A unity-gain follower Schematic - v t + + v - o 0 t Model i D4 0 0 Cc + v o O O Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan v g o S S (t) m C C C 2 πf C GS t t where th ω t O M 5

20 Power-Supply ejection atio (PS) Mixed-signal circuits combine analog and digital circuits Switching activity in digital portion results in supply ripple Add large capacitors between supply rails and ground not practical in C design High-PS analog circuits Definition PS PS For a two-stage op amp A A A ro7 vo vgnd ro6 ro7 vo A vgnd r Ad PS A d d o6 ro7 r g, where o7 m A A t s insensitive to DD PS + is very high [ef.] [ef.] P.. Gray, P. J. Hurst, A. H. Lewis, and. G. Meyer, Analysis and Design of Analog ntegrated Circuits, 5 th ed., New York: John Wiley & Sons, pp Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-20 Electronics(3), 20 v v v v ro2//ro4 g m6ro6 o dd o gnd M M3 M5 M4 M2 C GND M7 Cc M6 2 CL DD out

21 Design Trade-offs To increase the differential gain, CM, and PS for a two-stage op amp Enlarge the length L for the channel of each MOSFET Lower the O at which each MOSFET is operated The transition frequency of the MOSFETs can be increased by using a shorter channel and/or a larger O f T 2 g.5 m O ; where 2 C C 2L gs gd : carrier mobility O : overdrive voltage L : channel length n conclusion, it s a trade-off between low-frequency performance parameters and high-frequency ones For analog circuits in submicron process operated at ~.5 supplies, 0.~0.3 of O is typically used, and the typical channel lengths are at least.5~2 times the L min Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-2 Electronics(3), 20

22 Cascode CMOS and BiCMOS OPAMPs Cascaded two-stage CMOS OPAMP most popular and works well with low capacitive load problems limited slew rate due to large C c limited bandwidth with large C L PS is reduced by pole-splitting f. low output resistance is not required, 2. high open-loop gain is required, and 3. large phase margin can be maintained with large C L, then cascode configuration can provide attractive solutions for the above problems. Cascode CMOS OPAMP Gain of two-stage OPAMP can be increased by adding gain stage in cascade. phase shift is increased (i.e. PM) Cascode configurations can be used to increase gain in the existing stage. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-22

23 Cascode CMOS OPAMP DD Output resistance(o) is increased (g r ) rds 8 O6 O 4 O (g O 4 m6 m4 r ds4 // ds6 O 6 ) r ds2 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-23 Q 7 Q 5 Q 8 Q 6 bias oltage gain A gmo Gain is increased. Q Common-mode range is lowered and more transistors are stacked between the two power supplies. Folded-cascode has large common-mode range Q3 4 Q Q 2 Cascode and folded-cascode OPAMPs are also named as transconductance OPAMP or operational transconductance amplifier (OTA) O6 O4

24 Folded-Cascode CMOS OPAMP Q 3 ~ Q 8 are folded and connected to SS Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-24

25 Folded-Cascode CMOS OPAMP (Cont.) Q 9 ~ Q form externally-biased current sources Q 6 and Q 7 form self-biased current sources Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-25

26 Folded-Cascode CMOS OPAMP nput common-mode range Common-mode range is increased (compared with cascode OPAMPs). However, it is small compared with 2-stage OPAMPs O O tn CM DD O 9 Output voltage swing SS O 7 O 5 tn o DD O0 O 4 oltage gain A = G m o = g m o o = o4 // o6 = [g m4 r ds4 (r ds2 //r ds0 )]//(g m6 r ds6 r ds8 ) v tn Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-26

27 Frequency response Bode plot p t Folded-Cascode CMOS OPAMP g C 0 C L m L gain A larger C L The only high-impedance point is the output node. Dominant pole is generated at the output node The resistance of all other node at level of /gm Nondominant poles occur at all other nodes. The 2nd pole is usually at the source of M 3 and M 4. Nondominant poles are usually at frequencies beyond t f C L is increased, then phase margin is increased. f C L is not large enough, it can be augmented. No frequency compensation is required wide bandwidth f B, slew rate S = /C L = 2 πf ω Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-27 t ω p O smaller C L t t O frequency nondominant poles

28 Folded-Cascode CMOS OPAMP(Cont.) Folded-cascode OPAMPs have high open-loop output resistance t has been given the name operational transconductance amplifier (OTA) ts high output resistance (in the order of g m r o2 ) is far from that for an ideal OPAMP (which has zero output resistance) To alleviate this concern somewhat, let us find the closed-loop output resistance of of a unity-gain follower (β = ) formed by connecting the output terminal back to the negative input terminal o o o of of A A A G A general result applying to any OTA with 00% voltage feedback. For folded-cascode OPAMPs, G m g m of g m g m is in the order of ma/, and of will be of the order kω Although this is not very small it s reasonable in view of the simplicity of the OPAMP circuit as well as the fact that this type of OPAMP (OTA) is not usually intended to drive low-valued resistive load. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-28 Electronics(3), 20 m

29 Folded-Cascode with ail-to-ail nput Operation ncreased input common-mode range, rail-to-rail or even larger oltage gain, if g m =g m3 =G m A = (g m +g m3 ) o = 2G m o for middle CM A = g m o for high CM A = g m3 o for low CM Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-29

30 Folded-Cascode with Wide-Swing Current Mirror ncreased output voltage range v Omin O O3 tn v Omin O O3 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-30

31 Folded-Cascode with Wide-Swing Current Mirror (Cont.) Design example eff ( eff 2 3 D2 Since μ n Cox 2 w W L ox A common choice n w L c 2 D 2 2 eff ) eff w / L w L bias bias W L ( n ) w L w n n n L L eff eff n 4 eff G G G (n ) eff 5 4 th DS DS G GS G (neff th) (n ) out eff eff2 eff Q 5 n, out 2 eff 2 in W/L W /L 2 n Q 4 Q 3 4 eff out W/L Q out = in W /L 2 n Q 2 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-3

32 Folded-Cascode BiCMOS OPAMP Configuration DD Q3 Q 4 bias Q 5 2 Q3C Q 4C Q Q2 QC Q2C O C L bias2 B Q6 Q7 B bias3 SS Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-32

33 Folded-Cascode BiCMOS OPAMP (Cont.) The largest nondominant pole is usually generated at the emitter nodes of Q C and Q 2C ω p 2 C C p g C mc p where C ec //r O(Q6) //r O(Q) ec g mc The transconductance of BJT can be much larger than that of CMOS P2 can be increased u can be increased while enough phase margin is maintained wider bandwidth than that of CMOS foldedcascode OPAMP Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-33

34 74 OPAMP uses a large number of transistors but relatively few resistors and only one capacitor and C occupy large silicon area. C need more fabrication steps High-quality &C are not easy to fabricate. Circuit Diagram in the next page. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-34

35 74 OPAMP (Cont.) CC 5 Q2 Q 9 Q 8 Q3A Q4 Q3B Q 5 6 Q k n Q Q2 Q3 Q 4 n C C 30pF 0 40k Q 8 Q 23 Q Q 20 Q 6 Q EE Q k Q 7 Q5 Q6 k 3 50k 2 k Q k Q Q 24 50k Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-35

36 Bias circuit Basic Parts of 74 OPAMP ref is generated by Q,Q 2,Q 0, 4,Q 8,Q 9,Q 3 double-collector PNP Q 3 Current mirror CC AB A B n p p ( E) p ( B ) ( C B ) ( C A ) Q x X Q y Y y x A A E(Q E(Q y x ) ) where A E is emitter area Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-36

37 Basic Parts of 74 OPAMP(Cont.) Short-circuit protection circuitry 6 7 Q 5 Q 2,Q 24 Q OPAMP consists of 3 stages input differential stage single-ended high-gain stage output-buffering stage nput stage Q ~Q 7, ~ 3 biased by Q 8 ~Q 0 to provide high input impedance. Q 3 &Q 4 are lateral PNP (low ) higher emitter-base junction breakdown than NPNs protect input transistors Q &Q 2 when they are accidentally shorted to supply voltages. Q 5 ~Q 7, ~ 3 provide high-resistance load and singleended output. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-37

38 Basic Parts of 74 OPAMP(Cont.) Second stage Q 6,Q 7,Q 3, 8, 9 Q 6 acts as an emitter follower, thus giving high input resistance low base current if 9 is large, hence low loading of the first stage. Q 7 : common emitter configuration Q 3B : active load Cc: Miller capacitor for pole-splitting compensation 30pF area occupied is about 3 times that of a standard NPN transistor. Output stage provide low output resistance class AB Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-38

39 DC Analysis of 74 OPAMP Device parameters Standard transistors NPN: S = 0-4 A, = 200, A = 25 PNP: S = 0-4 A, = 50, A = 50 Nonstandard transistors Q 3,Q 4,Q 20. Q 3 = Q 3A + Q 3B Q 3A : SA = 0.25 x 0-4 A Q 3B : SB = 0.75 x 0-4 A 2. Q 4 & Q 20 S = 3 x 0-4 A eference bias current CC EB2 BE ( EE ) EF 5 For CC = - EE = 5 BE = BE2 0.7 EF 0.73mA Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-39

40 Widlar current sources Bipolar BE BE0 C04 EF T ln C04 C0 Trial and error to determine 9μA C0 MOSFET O assume D0 D0 O0 D K 2 D0 K 4 ' 2 O nput Stage Bias 4 4 K 2 ' K 4 ' EF 2K 4 EF K EF ' K ' C0 4 EF Q - EE Q0 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-40 K ' D0 0 K EF D0 2 4 ' EF M - EE C0 4 D0 M0 4

41 nput Stage Bias(Cont.) nput differential circuitry Let C = C2 = E3 = E4 B3 C9 B4 2 2 β β C0 2 = 9.5A C = C2 C4 = 9.5A P P β P Q9 Q8 X 2 2 β p 2 β P 2 Q Q 2 β p β p Q3 Q4 Q ~Q 4,Q 8,Q 9 form a negative feedback loop The feedback stabilize the value of (i.e. is kept unchanged and only controlled by C0 ) Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-4

42 nput Stage Bias(Cont.) Active load C5 C6 C7 E7 C7 S BE 6 2 BE6 T ln 57m 2 N 0.5A 3 Q 5 C3 0 β N Q 7 β N 3 Q 6 2 Q 6 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-42

43 Gain stage with resistor load (Cont.) esistor Load A g m gm C α T //r 0 in 0 out Large Small For High gain High c o High c o means large voltage drop on o Large power supply High reduces speed Use active loads to overcome the above problems. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-43

44 Gain Stage with Active Load Transistor can provide large resistance if properly biased. Example A g m r0//r g m ( r0 ) 2 Cr0 α 2 T 02 - curve & load line in Q2 Q3 Q out load line ( large r O ) Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-44

45 nput bias nput current B B2 β N nput bias 9.5μA na very small Offset current and offset voltage are introduced in chapter 6 nput common-mode range n this range, the input stage remains in the linear active mode This range is determined at the upper end by saturation of Q and Q 2, and at the lower end by saturation of Q 3 and Q 4. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-45

46 Second Stage Bias C3 =0.75 C EF 550A C7 C3B =550A C7 BE7 Tln 68m S E7 8 C6 E6 B7 9 BE7 6.2μA Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-46

47 Output Stage Bias f short-circuit protection circuitry is omitted Q 3A CC C3A B23 C EF 80A A 50 BE8 E A ( BE8 = 0.6 is assumed) 40k Q EF Q EF Q 23 Q 4 Q 20 0 BE8 588m (This is close to the value assumed) EE Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-47

48 Output Stage Bias(Cont.) C9 BE9 BE8 Tln Tln E9 C4 S4 C4 S4 BE9 588m 530 m.8 Tln C20 S20 B8 Tln C9 S 530 m C20 S μA.8 BE μA C4 = C20 = 54uA Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-48

49 Small-Signal Analysis of 74 nput Stage Simplified ac schematic For differential mode input, biases of Q 3 and Q 4 are at ac ground. i d Q Q2 d 2 2 d r π gm v Q3 Q 4 ic2 ic4 Small- signal equvilant half - circuit gm 3 v r π3 Transconductance id 3 2 gm( ) 3g m3 ( 3 ) i C3 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-49

50 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-50 Small-Signal Analysis of 74 nput Stage(Cont.) k. c g i Gm g i i g g... g g T m id out id m c c id m id m m m id i 4 i 4 i () 4 50, 200, g g, c c since out 3 c4 3 c3 id 3 3 m3 m

51 Small-Signal Analysis of 74 nput Stage (Cont.) nput esistance id From( ), id i id i where r e id / r T C 3 π id 4 4r π 25m 9. 5μA 4 β r 2. 63KΩ gm e 2. MΩ Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-5

52 Small-Signal Analysis of 74 nput Stage (Cont.) Output resistance O -simplified circuit O6 re (of Q2) Q 6 Q 4 2 O4 efer to chapter 6 o4 = r o(q4) {+gm 4 (r e // r 4 )} 0.5M o6 = r o(q6) {+gm 6 ( 2 // r 6 )} 8.2M where r o = A / o = o4 // o6 6.7M Two-port equivalent circuit of input stage id 2.M 6.7M id 5.26k Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-52

53 Small-Signal Analysis of the 74 Second Stage Simplified circuit Q 3B i Q 6 + i2 9 i C7 8 small-signal equivalent circuit i2 - i2 Gm2i2 O2 i2 i7 nput resistance i2 i7 = ( 7 +)(r e7 + 8 ) = ( i2 6 +)(r e6 +( 9 // i7 )) 4M Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-53

54 Small-Signal Analysis of the 74 Second Stage(Cont.) Transconductance Gm 2 voltage gain of the emitter follower Q 6 is nearly unity. i b7 i2 + - r π 7 gm 7v = βi b7 8 i2 G i i b7 C7 m2 r 7 gm ic 7 i2 ( i 7 b7 g g i m7 C7 m7 7 ) i C7 i 7 C7 r 6.5mA/ 7 g g i C7 m7 m7 ( 8 7 ) 8 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-54

55 Small-Signal Analysis of the 74 Second Stage(Cont.) Output esistance o2 = o7 // o3b o3b = r o(q3b) o7 r o(q7) [+gm 7 ( 8 // r 7 )] o2 = o7 // o3b 787k//90.9k 8k O7 r e6 9 8 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-55

56 74 Output Stage Output voltage limits omax = CC - CE3A(sat) - BE4 omin = - EE + CE7(sat) + EB23 + EB20 Class AB stage Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-56

57 Small-Signal Analysis of the 74 Output Stage Simplified circuit for positive o, BE4 > EB20 CC i4 eq4 r O3A r O3A Q4 Q4 Q 9 Q 4 O 0 r d9 r d8 L 2k r d9 r d8 O4 Q 8 L eq3 Q 23 Q 20 i3 Q 23 O23 O2 8K Q 23 - EE (a) (b) (c) Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-57

58 Small-Signal Analysis of the 74 Output Stage(Cont.) nput esistance i3 For positive o with Q 20 neglected (Q 4 conducts more current) i4 = r 4 +(+ 4 ) L + eq3 = r d8 +r d9 +(r o(q3a) // i4 ) where r d8 +r d9 is very small. + i3 = r 23 +(+ 23 )+ eq3 For negative o with Q 4 neglected (Q 20 conducts more current) i20 = r 20 +(+ 20 ) L - eq3 = r d8 +r d9 +r o(q3a) where r d8 +r d9 - i3 = r 23 +(- eq3 // i20 ) is very small. Actual i3 is between + i3 and - i3 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-58

59 Small-Signal Analysis of the 74 Output Stage(Cont.) Output esistance out For positive o with Q 20 neglected out o4 eq4 o4 r r o( Q3A) e4 // r eq4 β 4 d9 r d8 r e23 β o2 23 For negative o with Q 4 neglected out O23 O20 r r O20 e23 e20 O2 β23 eq3 / / β Actual out is between + out and - out 20 O23 0 O2 Q 9 Q 3,4 A Q 8 Q 23 eq3 O23 Q 20 O20 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-59

60 Small-Signal Analysis of the 74 Output Stage(Cont.) Small-signal equivalent circuit model O O2 B23 + i3 - i3 + - out G vo 3vo2 + - O Out L μ i3 i3 O Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-60

61 Gain and Frequency esponse of the 74OPAMP Equivalent circuit of the 74 OPAMP O2 out + i - id Gm i O i2 - +i i3 - i3 + - G vo v 3 o2 + O - L Gain o i i 2 i G // G 07.7dB o2 i2 o o2 m( o i2 m2 o2 out L L O2 Gm2O2i2 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-6

62 Gain and Frequency esponse of 74 OPAMP (Cont.) Frequency esponse 74 is an internally compensated OPAMP Miller Compensation C C C i A 2 C A i 2 C C ( A Gm 2 2 O2 ) Miller theorem ( O i3 2 i3 ) Ci 30 pf( CC) ( 55 ) 5,480 pf 55 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-62

63 Gain and Frequency esponse of 74 OPAMP (Cont.) Neglecting the parasitic capacitance at the base of Q 6 Total resistance at this node t =( O // i2 ) Dominant pole f p = 2π tc 4.Hz Bode plot (Neglecting nondominant poles) A,dB A dB 20dB/decade i 0 f3db 4.Hz f t A 0 f 3dB MHz f 3dB bandwidth f 3dB = f p = 4.Hz unity-gain bandwidth f t = A 0 f 3dB = MHz Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-63

64 Gain and Frequency esponse of 74 OPAMP (Cont.) Simplified model model the 2nd stage as an integrator C C + i _ id 0 Gmi + O _ O( s) Gm A( s) A( i( s) scc Gm A( jt) t CC For Gm and C 5.26k C j) Gm jc 30PF, t MHz 2 ( equal to the value calculated before) Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-64 f C t

65 Slew ate Large signal behavior Output voltage slew limitation d dt f t G max m G 2C m c C 2 slew rate slew rate slew rate T (as 4 G c m T f 8 f t 2 C t c shown previously) 2 C C A 2 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-65

66 Effect of Slew ate (Cont.) Effect of slew rate on an unity-gain follower voltage v v O without slew rate limitation v O v with no slew rate o i msinωi do ωmcosωt dt Let m DD, then limitation ; f slewing do max ωm dt slew rate is 2π DD v O with slew rate limitation called time full- power bandwidth. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-66

67 Effect of Slew ate (Cont.) for small-amplitude sinusoidal signal voltage v O dv O dt slew rate limitation t for large-amplitude sinusoidal signal voltage v O without slew rate limitation v O with slew rate limitation t Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-67

68 Two-Stage CMOS OPAMP Topology DD Q8 Q5 Q Q Q2 CC ref Q3 Q4 Q6 oltage gain SS Frequency response ( 以上參考之前授課内容 ) Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-68

69 Two-Stage CMOS OPAMP(Cont.) Slew rate 2 Gm 2 S ; ωt Cc Cc (GS t )Cc S = ( GS - t ) t for CMOS OPAMP (S = 4 T t for BJT OPAMP) ( GS - t ) is usually larger than 4 T For the same t, CMOS OPAMPs exhibit higher slew rate than BJT OPAMPs ( i.e. for the same slew rate, t(bjt) t(cmos) ) G m reduction method SBJT 4T ωt ωt Gm SCMOS (GS t )ωt ωt Gm For a given ω t, a higher S can be obtained by making G m smaller while bias current is kept constant. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-69

70 Modern Techniques for the BJT Op Amps easons for single-supply operation with much lower CC Meet modern small-feature-size fabrication technologies Be compatible with other low-power-supply systems Minimize the power dissipation, P = DD DD, especially for battery-operated systems For a low-voltage single-supply system, rail-to-rail input common-mode range may be required because of its inherent low supply voltages Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-70

71 ail-to-ail nput Common-Mode OPAMP 9 CC 0 4b 3b Q 4b Q 3b Bias Q 5 Bias3 Q9 Q0 Q b 2b Q 2b - Q 3 Q ++ 4 Q Q - 2 v o v o2 Q B 7 Q 6 Bias2 Q CMF Bias circuit nput stage Cascode stage with Common-Mode Feedback (CMF) Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-7

72 Bias Design Widlar current source BE BE2 T ln S T ln S2 BE T 2b BE2 ln S2 S T ln S2 S 2b CC 4b Q 4b Q b 3b Q 3b Q 2b bias bias2 2b is independent of CC is directly PTAT, proportional to absolute temperature. Mirrored transistors are independent of temperature. g m T Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-72

73 with active load EC with passive load 0 6 nput Stage Design if is selected to 0.2 ~ 0.3 will be -0.4 ~ -0.3 Differential gain is degraded CM min ECsat C CM min. C CM min A g CM max m,2 C C CC CC T 2 C BE3 ECsat EB T C 0. CC BAS Q C Q 5 v o CC Q 2 BAS Q 3 C Q Q 5 CC Q 2 Q 4 v o Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-73

74 Assume that nput Stage Design (cont.) C 0. 3 For pnp differential-pair (previous page) CM CC For npn differential-pair (right figure) CM CC Connecting the two circuits in parallel A rail-to-rail CM range CM CC Q 3 Q 4 BAS Q 6 CC C v o For the overlap region 0. 8 CM CC08., both pnp and npn circuits are active higher effective trans-conductance (X2) higher gain Adding a folded-cascode stage can also increase gain C Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-74

75 Common-Mode Feedback (CMF) Without CMF two mismatched BJT-pairs, i.e. (Q 9 -Q 0 ) and (Q 7 -Q 8 ) an increment Δ will be multiplied by large out large changes at v o & v o2 one set of BJT-pair saturates 9 CC 0 With CMF t ensures Q 7,8 remain active CM is regulated if CM B 7,8 CM 3 4 Bias3 Q 9 Q 0 Q 7 v o 2 B v o2 Q 8 CMF 7 8 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-75

76 CMF Circuit Configuration v v Q CM o o E D : ~Q B 4 CM (v CM CM CM o oltage v d 2 v d 2 act as emitter followers E v D drop o2 of )/ 2 EB,2 CM EB3,4 0.4 v o B Schottky barrier diode v o3 Q D Q 3 Q 4 Q 2 D E Q 5 BAS v o2 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 0-76