Analog Integrated Circuits Fundamental Building Blocks

 Bernard Sherman
 5 months ago
 Views:
Transcription
1 Analog Integrated Circuits Fundamental Building Blocks Basic OTA/Opamp architectures Faculty of Electronics Telecommunications and Information Technology Gabor Csipkes Bases of Electronics Department
2 Outline definition of the OTA/opamp cascade of amplifier stages the general opamp architecture the uncompensated Miller opamp small signal model at low and high frequencies step response of a second order system with unity feedback the two stage opamp with Miller compensation models and parameters sizing algorithm for the two stage Miller opamp the telescopic opamp voltage budget, models and parameters sizing algorithm of the telescopic opamp the folded cascode opamp small signal low and high frequency model sizing algorithm for the folded cascode opamp Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 2
3 The ideal opamp  definitions ideal opamp = a differential input, voltage controlled voltage source with very large open loop gain the ideal gain is frequency independent, but real gain can be modeled with a set of poles and zeros typically low pass behavior very large input resistance and near zero output resistance opamps with strictly capacitive loads can have large output resistance Operational Transconductance Amplifiers (OTA) often also called opamp the output may be single ended (referenced to ground) or differential single or symmetrical supply voltages out V a V V Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 3
4 The opamp a cascade of elementary stages the typical opamp architecture a differential amplifier followed by a high gain inverting stage and a voltage follower for low output impedance the voltage follower may be missing if the load is known to be strictly capacitive frequency compensation for closed loop stability probably required (more on this later) elementary amplifier stages subsequent VI and IV conversions most simple form the two stage opamp VI IV IV cascade of elementary stages VI Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 4
5 The two stage or Miller opamp Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 5
6 The two stage opamp the small signal low frequency model with two equivalent stages no capacitive effects low frequency or DC voltage gain each stage can be analyzed individually G m and R out specific to each configuration V G m 1 g m 1,2 R r r Gm 2 gm6 R r r out1 DS 2 DS 4 out 2 DS 6 DS 7 a0 Gm 1Rout1 Gm2R out 2 a a 1 2 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 6
7 The two stage opamp the small signal high frequency model consider load and parasitic capacitances V C1 C2 CGD 1,2 C C C C C C4 CGD 4 C5 CGS 6 CDB2 CDB4 C6 CGD6 C7 CL CDB6 CDB7 CL 3 GS 3 GS 4 DB1 DB3 a( s) a 1 sr C 1 sr C 0 out1 5 out 2 7 The frequency response is dominated by C 5 and C 7 due to the large R out1 and R out2! Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 7
8 The two stage opamp with negative feedback the closed loop model of an opamp with negative feedback A( s) a a( s) a( s) 0 s s 1 a( s) r 1 1 p1 p2 The closed loop gain: A( s) 0 p1 p2 0 a( s) 1 a0r 2 1 ( ) 1 a p1 p2 p1 p2 0 1 a r a s r s s a r The standard form of a second order transfer function: (DC gain A 0, resonant frequency ω n and damping factor ξ ) A n A ( s ) s 2 0 n 2 2 2n s n A a 1 ; 1 a r ; a r r a r 0 p1 p2 0 n p1 p p1 p2 1 0 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 8
9 Frequency response of a second order system the effect of the feedback transmittance r on the magnitude response A 0 1 r A 0 decreases with r Overshoot of the frequency response at ω n complex poles under damped step response worst case stability for unity gain (r=1 and A 0 =1) lowest ξ for given a 0, ω p1 and ω p2 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 9
10 Step response for unity gain feedback the time domain step response is calculated as damping of the oscillation amplitude depends on ξ V out ( t) 1 A( s) L s typically, if poles ω p1 and ω p2 are close to each other ξ<1 under damped system with fading oscillations of the step response n t 2 e 2 1 Vout ( t) 1 sin 1 arctan 2 n t 1 fading exponential oscillations with the period envelope depending on ω n and ξ since the sin function varies between 1 and 1 time domain overshoot around the unit step the overshoot and number of cycles until settling increases with a smaller ξ Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 10
11 Step response for unity gain feedback step response of the two stage opamp in unity gain feedback configuration optimal response the circuit is unusable as amplifier for small ξ due to the very long settling time the response stability depends on the phase margin (m φ ) optimal response for m φ =65 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 11
12 closed loop gain for unity feedback: A( s) Stability and phase margin a( s) 1 a( s) What if denominator is 0??? a( s) 1 the closed loop gain approaches even for no input any perturbation is amplified with under damped transients sustained oscillations occur, feedback turns positive and system becomes unstable a( j) 1 Barkhausen's stability criteria: a( j) 180 a j 1 j p 1 p2 solve for ω f 0dB m 180 a j odb 180 arctan arctan 0dB 0dB p1 p2 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 12
13 Pole locations and phase margin the relation between pole frequencies and f 0dB defines m φ and the stability of the step response This is what we need! f f p2 0dB m 45 f f p2 0dB m 45 f f p2 0dB m 45 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 13
14 Frequency compensation need f p2 >f 0dB so that m φ >45 impossible to achieve by simply cascading a differential amplifier and a common source inverting amplifier f p 1 f p2 1 2 R C 1 2 R out1 5 C out 2 7 Typically: R C R out1 out 2 C 7 5 f p1 and f p2 are close to each other!!! We need to manipulate pole locations to separate f p1 and f p2 frequency compensation Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 14
15 Miller frequency compensation idea 1: push p 1 to lower frequencies by increasing C 5 must have very large values for a satisfactory m φ not practical for the integrated opamp idea 2: use the Miller effect to virtually increase C 5 practical solution since the gain of the second stage is usually large connect C M that emphasizes the capacitive shunt around the inverting second stage V Gm 1V in sc5v scm V Vout Rout1 Vout Gm2V sclvout scm V Vout Rout 2 0 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 15
16 Miller frequency compensation capacitances C 1,C 2, C 3,C 4 and C 6 considered small and neglected for simplicity the frequency dependent gain a(s) results: C M Gm 1 Gm2 Rout1 Rout 2 1 s G m2 a( s) dominant terms 2 k2s k1s 1 k2 Rout1Rout 2 C5CL C5CM CLCM k1 Rout1C5 Rout 2CL Rout1 Rout 2 CM Gm2Rout1Rout 2CM use the dominant pole approximation to find pole and zero locations a( s) C M Gm 1Gm 2Rout1Rout 2 1 s G m2 2 out1 out 2 L M m2 out1 out 2 M R R C C s G R R C s 1 a( s) s a0 1 zp s s 1 1 p1 p2 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 16
17 Miller compensation frequency response One dominant pole, one high frequency pole and one right half plane zero: a0 Gm 1Gm 2Rout1Rout 2 1 f p1( d ) 2 G R R C f f p2 zp G 2 C m2 G 2C m 2 L M m2 out 2 out1 M GBW a f 0 p1( d ) G 2C m1 M m GBW GBW 90 arctan arctan f f p2 zp Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 17
18 Miller compensation step response assume unity gain negative feedback and apply an input step to the follower 1 A( s) step response calculated as Vout ( t) L s V Slew Rate (SR) variation rate of the output voltage SR tt Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 18
19 The two stage compensated opamp slew rate the total capacitance of every node must be charged and discharged in each cycle charging rate depends on the largest supplied current every node limits the variation rate of V out the slew rate is imposed by the most stringent limitation Vout SR min SR, SR t I5 I7 SR1 ; SR2 CM CL 1 2 Typically I 5 <<I 7, while C M and C L are comparable SR I C 5 M Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 19
20 The two stage opamp design algorithm specifications given (others are also possible) the low frequency open loop gain a 0 larger than a critical value slew rate (SR) unitygain bandwidth (GBW) the right half plane zero frequency relative to GBW (ratio k imposed by the designer!) the typical load capacitance C L supply voltages phase margin m φ chosen according to the application (often unconditional stability!) typical transistor V DSat voltages (unless resulting from design constraints! ) Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 20
21 The two stage opamp design algorithm Step 1 calculate the required compensation capacitor C M relative to C L Gm 1 GBW 2 CM Gm2 f zp k GBW 2CM GBW f p2 G 2 C Gm2 2C L m1 M G G m1 m2 1 k GBW G C C f G C kc m1 L L p2 m2 M M GBW 1 m f GBW, f p2, f zp tan 90 m arctan f p2 k C M k C L 1 tan 90 m arctan k Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 21
22 The two stage opamp design algorithm Step 2 calculate the differential stage bias current for a given SR and C M SR I C 5 M I SR C 5 M Step 3 calculate the transconductances G m1 and G m2 GBW G m1 Gm 1 2 GBW CM Gm2 k Gm 1 2CM Step 4 find V DSat and the geometry of the input transistors G 2I I D 1,2 I5 g m V I V 5 DSat1,2 W DSat1,2 VDSat1,2 G L m1 1 m1 1,2 W W Step 5 choose V DSat for M 3, M 4 and M 5 ; L 3,4 L 5 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 22
23 The two stage opamp design algorithm Step 6 balance the M 3 M 4 current mirror by choosing V DSat3 =V DSat4 =V DSat6 and find the geometry of M 6 G m2 2I 2I V V D6 7 DSat 6 DSat 6 1 I G V 2 7 m2 DSat6 W L 6 Step 7 choose V DSat7 =V DSat5 and determine the geometry of M 7 W L 7 Further ideas: remember the body effect and the parasitic capacitances G m s will always be smaller than expected while capacitances will always be larger oversize try to set all currents to be integer multiples of a given bias current use a current mirror based biasing scheme instead of voltages iteratively simulate and optimize the design until all specifications have been met Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 23
24 The folded cascode opamp Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 24
25 The folded cascode opamp another typical opamp architecture a differential amplifier followed by a current buffer and a cascode output stage for large R out an additional output voltage follower may be used if the load is not strictly capacitive no need for frequency compensation (more on this later) elementary amplifier stages a single VI and IV conversion pair II IV cascade of elementary stages (transconductance, common gate and transimpedance) VI Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 25
26 the small signal low frequency model with two equivalent stages no capacitive effects low frequency or DC voltage gain The folded cascode opamp the current buffer a subsequent IV and VI conversion pair with R p and G mp adjusted to provide a unity current gain V p1 V p2 Gm gm 1,2 1 1 Rp a Gmp g m6,7 R g r r g r r out m9 DS 9 DS11 m7 DS 7 DS 5 G R 0 m out Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 26
27 The folded cascode opamp the small signal high frequency model consider the load and the dominant parasitic capacitances C p1 C p2 CDB 1 CDB4 CGD 4 CSB6 CGS 6 C p1 C p2 CC p 2 2 a( s) a 1 sroutcl 1 srpc p 0 Since R out >>R p and C L >>C p, the poles are always separated and the phase margin will be typically large (m φ >70 ), even if mirror singularities are considered No need for frequency compensation the circuit typically works at larger frequencies than the stable two stage opamp Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 27
28 The folded cascode opamp frequency response One dominant pole and one high frequency pole (mirror singularities neglected): a0 GmRout 1 f p1( d ) 2 RoutCL 1 Gmp f p2 2 R C 2 C p p p GBW a f 0 p1( d ) Gm 2C L m GBW 90 arctan f p2 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 28
29 The folded cascode opamp step response assume unity gain negative feedback and apply an input step to the follower 1 step response calculated as A( s) Vout ( t) L s V Slew Rate (SR) variation rate of the output voltage SR tt large phase margin no overshoot Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 29
30 The folded cascode opamp slew rate the total capacitance of every node must be charged and discharged in each cycle charging rate depends on the largest current supplied to the node capacitances the folding node is charged rapidly SR limited by the output node SR I C B L Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 30
31 The folded cascode opamp design algorithm Step 1 calculate the required input stage transconductance GBW Gm 1 2C L G g GBW C m1 m1,2 2 L Step 2 calculate the required input stage bias current I I SR C C B 3 3 L L L I SR C Step 3 calculate the V DSat1,2 voltage and the differential transistor pair geometry g m1,2 2I D 1,2 I3 V VDSat g V 1,2 m I 1,2 3 DSat1,2 DSat1,2 W L 1,2 W Step 4 choose V DSat3 and calculate the geometry of M 3 L 3 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 31
32 The folded cascode opamp design algorithm Step 5 choose I D6,7 =I D8,9 =I D10,11 =( ) I D1,2 to avoid completely turning off the cascode stage when the opamp is slew rate limited (all I 3 flows through M 1 or M 2 ) I D6,7 D1,2 I I I I I D4,5 D1,2 D6,7 D1,2 Step 7 choose V DSat for all transistors (except M 1, M 2 and M 3 ) and determine the geometries Further ideas: remember the body effect and the parasitic capacitances G m s will always be smaller than expected while capacitances will always be larger oversize try to set all currents to be integer multiples of a given bias current use a current mirror based biasing scheme instead of voltages iteratively simulate and optimize the design until all specifications have been met Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 32
33 Bibliography P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, Oxford University Press, 2002 B. Razavi, Design of Analog CMOS Integrated Circuits, McGrawHill, 2002 D. Johns, K. Martin, Analog Integrated Circuit Design, Wiley, 1996 P.R.Gray, P.J.Hurst, S.H.Lewis, R.G, Meyer, Analysis and Design of Analog Integrated Circuits, Wiley,2009 R.J. Baker, CMOS Circuit Design, Layout and Simulation, 3 rd edition, IEEE Press, 2010 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 33
Today s topic: frequency response. Chapter 4
Today s topic: frequency response Chapter 4 1 Smallsignal analysis applies when transistors can be adequately characterized by their operating points and small linear changes about the points. The use
More informationEECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design
EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design References: Analog Integrated Circuit Design by D. Johns and K. Martin and Design of Analog CMOS Integrated Circuits by B. Razavi All figures
More informationECEN 474/704 Lab 8: TwoStage Miller Operational Amplifier
ECEN 474/704 Lab 8: TwoStage Miller Operational Amplifier Objective Design, simulate and test a twostage operational amplifier Introduction Operational amplifiers (opamp) are essential components of
More informationAnalysis and Design of Analog Integrated Circuits Lecture 20. Advanced Opamp Topologies (Part II)
Analysis and Design of Analog Integrated Circuits Lecture 20 Advanced Opamp Topologies (Part II) Michael H. Perrott April 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Outline of Lecture
More informationChapter 12 Opertational Amplifier Circuits
1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS opamp architectures: the twostage circuit and the singlestage, folded cascode circuit.
More informationDesign of HighSpeed OpAmps for Signal Processing
Design of HighSpeed OpAmps for Signal Processing R. Jacob (Jake) Baker, PhD, PE Professor and Chair Boise State University 1910 University Dr. Boise, ID 837252075 jbaker@ieee.org Abstract  As CMOS
More informationEE 501 Lab 4 Design of two stage op amp with miller compensation
EE 501 Lab 4 Design of two stage op amp with miller compensation Objectives: 1. Design a two stage op amp 2. Investigate how to miller compensate a twostage operational amplifier. Tasks: 1. Build a twostage
More informationA Unity Gain FullyDifferential 10bit and 40MSps SampleAndHold Amplifier in 0.18μm CMOS
A Unity Gain FullyDifferential 0bit and 40MSps SampleAndHold Amplifier in 0.8μm CMOS Sanaz Haddadian, and Rahele Hedayati Abstract A 0bit, 40 MSps, sample and hold, implemented in 0.8μm CMOS technology
More informationECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers
ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic
More informationUniversity of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1. A High Speed Operational Amplifier
University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1 A High Speed Operational Amplifier A. Halim ElSaadi, Mohammed ElTanani, University of Michigan Abstract This paper
More informationA Compact Foldedcascode Operational Amplifier with ClassAB Output Stage
A Compact Foldedcascode Operational Amplifier with ClassAB Output Stage EEE 523 Advanced Analog Integrated Circuits Project Report Fuding Ge You are an engineer who is assigned the project to design
More informationPURPOSE: NOTE: Be sure to record ALL results in your laboratory notebook.
EE4902 Lab 9 CMOS OPAMP PURPOSE: The purpose of this lab is to measure the closedloop performance of an opamp designed from individual MOSFETs. This opamp, shown in Fig. 91, combines all of the major
More informationEE Analog and Nonlinear Integrated Circuit Design
University of Southern California Viterbi School of Engineering Ming Hsieh Department of Electrical Engineering EE 479  Analog and Nonlinear Integrated Circuit Design Instructor: Ali Zadeh Email: prof.zadeh@yahoo.com
More informationBasic OpAmp Design and Compensation. Chapter 6
Basic OpAmp Design and Compensation Chapter 6 6.1 OpAmp applications Typical applications of OpAmps in analog integrated circuits: (a) Amplification and filtering (b) Biasing and regulation (c) Switchedcapacitor
More informationDesign of Low Voltage Low Power CMOS OPAMP
RESEARCH ARTICLE OPEN ACCESS Design of Low Voltage Low Power CMOS OPAMP Shahid Khan, Prof. Sampath kumar V. Electronics & Communication department, JSSATE ABSTRACT Operational amplifiers are an integral
More informationDESIGN OF A FULLY DIFFERENTIAL HIGHSPEED HIGHPRECISION AMPLIFIER
DESIGN OF A FULLY DIFFERENTIAL HIGHSPEED HIGHPRECISION AMPLIFIER Mayank Gupta mayank@ee.ucla.edu N. V. Girish envy@ee.ucla.edu Design I. Design II. University of California, Los Angeles EE215A Term Project
More informationRailToRail Output OpAmp Design with Negative Miller Capacitance Compensation
RailToRail OpAmp Design with Negative Miller Capacitance Compensation Muhaned Zaidi, Ian Grout, Abu Khari bin A ain Abstract In this paper, a twostage opamp design is considered using both Miller
More informationBasic OpAmp Design and Compensation. Chapter 6
Basic OpAmp Design and Compensation Chapter 6 6.1 OpAmp applications Typical applications of OpAmps in analog integrated circuits: (a) Amplification and filtering (b) Biasing and regulation (c) Switchedcapacitor
More informationLecture 240 Cascode Op Amps (3/28/10) Page 2401
Lecture 240 Cascode Op Amps (3/28/10) Page 2401 LECTURE 240 CASCODE OP AMPS LECTURE ORGANIZATION Outline Lecture Organization Single Stage Cascode Op Amps Two Stage Cascode Op Amps Summary CMOS Analog
More informationA Review Paper on Frequency Compensation of Transconductance Operational Amplifier (OTA)
A Review Paper on Frequency Compensation of Transconductance Operational Amplifier (OTA) Raghavendra Gupta 1, Prof. Sunny Jain 2 Scholar in M.Tech in LNCT, RGPV University, Bhopal M.P. India 1 Asst. Professor
More informationCHAPTER 9 FEEDBACK. NTUEE Electronics L.H. Lu 91
CHAPTER 9 FEEDBACK Chapter Outline 9.1 The General Feedback Structure 9.2 Some Properties of Negative Feedback 9.3 The Four Basic Feedback Topologies 9.4 The Feedback Voltage Amplifier (SeriesShunt) 9.5
More informationIN RECENT years, lowdropout linear regulators (LDOs) are
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 52, NO. 9, SEPTEMBER 2005 563 Design of LowPower Analog Drivers Based on SlewRate Enhancement Circuits for CMOS LowDropout Regulators
More information856 Feedback Networks: Theory and Circuit Applications. Butterworth MFM response, 767 Butterworth response, 767
Index I/O transfer admittance, 448 N stage cascade, 732, 734 Sparameter characterization, 226 ω max, 204 πtype, 148 πtype network model, 137 cparameter, 151, 153 cparameter matrix, 154 gparameter
More informationCSE 577 Spring Insoo Kim, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Penn State University
CSE 577 Spring 2011 Basic Amplifiers and Differential Amplifier, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Penn State University Don t let the computer
More informationA Novel Design of Low Voltage,Wilson Current Mirror based Wideband Operational Transconductance Amplifier
A Novel Design of Low Voltage,Wilson Current Mirror based Wideband Operational Transconductance Amplifier Kehul A. Shah 1, N.M.Devashrayee 2 1(Associative Prof., Department of Electronics and Communication,
More informationLecture 300 Low Voltage Op Amps (3/28/10) Page 3001
Lecture 300 Low Voltage Op Amps (3/28/10) Page 3001 LECTURE 300 LOW VOLTAGE OP AMPS LECTURE ORGANIZATION Outline Introduction Low voltage input stages Low voltage gain stages Low voltage bias circuits
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
OTAoutput buffer 1 According to the types of loads, the driving capability of the output stages differs. For switched capacitor circuits which have high impedance capacitive loads, class A output stage
More informationA PSEUDOCLASSAB TELESCOPICCASCODE OPERATIONAL AMPLIFIER
A PSEUDOCLASSAB TELESCOPICCASCODE OPERATIONAL AMPLIFIER M. TaherzadehSani, R. Lotfi, and O. Shoaei ABSTRACT A novel classab architecture for singlestage operational amplifiers is presented. The structure
More informationVoltage Feedback Op Amp (VFOpAmp)
Data Sheet Voltage Feedback Op Amp (VFOpAmp) Features 55 db dc gain 30 ma current drive Less than 1 V head/floor room 300 V/µs slew rate Capacitive load stable 40 kω input impedance 300 MHz unity gain
More informationSystem on a Chip. Prof. Dr. Michael Kraft
System on a Chip Prof. Dr. Michael Kraft Lecture 4: Filters Filters General Theory Continuous Time Filters Background Filters are used to separate signals in the frequency domain, e.g. remove noise, tune
More informationDesign and Layout of Two Stage High Bandwidth Operational Amplifier
Design and Layout of Two Stage High Bandwidth Operational Amplifier Yasir Mahmood Qureshi Abstract This paper presents the design and layout of a two stage, high speed operational amplifiers using standard
More informationLow Dropout Voltage Regulator Operation and Performance Review
Low Drop Voltage Regulator peration and Performance Review Eric Chen & Alex Leng ntroduction n today s power management systems, high power efficiency becomes necessary to maximize the lifetime of the
More informationINF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation
INF3410 Fall 2013 Compensation content Introduction Two Stage Opamps Compensation Slew Rate Systematic Offset Advanced Current Mirrors Operational Transconductance Amplifiers Current Mirror Opamps Folded
More informationHigh bandwidth low power operational amplifier design and compensation techniques
Graduate Theses and Dissertations Graduate College 2009 High bandwidth low power operational amplifier design and compensation techniques Vaibhav Kumar Iowa State University Follow this and additional
More informationHigh PSRR Low Dropout Voltage Regulator (LDO)
High PSRR Low Dropout Voltage Regulator (LDO) Pedro Fernandes Instituto Superior Técnico Electrical Engineering Department Technical University of Lisbon Lisbon, Portugal Email: pf@b52.ist.utl.pt Julio
More informationLowNoise Amplifiers
007/Oct 4, 31 1 General Considerations Noise Figure LowNoise Amplifiers Table 6.1 Typical LNA characteristics in heterodyne systems. NF IIP 3 db 10 dbm Gain 15 db Input and Output Impedance 50 Ω Input
More informationOperational Amplifier Bandwidth Extension Using Negative Capacitance Generation
Brigham Young University BYU ScholarsArchive All Theses and Dissertations 20060706 Operational Amplifier Bandwidth Extension Using Negative Capacitance Generation Adrian P. Genz Brigham Young University
More informationEFFICIENT DRIVER DESIGN FOR AMOLED DISPLAYS
EFFICIENT DRIVER DESIGN FOR AMOLED DISPLAYS CH. Ganesh and S. Satheesh Kumar Department of SENSE (VLSI Design), VIT University, Vellore India EMail: chokkakulaganesh@gmail.com ABSTRACT The conventional
More informationDesign and Simulation of Low Dropout Regulator
Design and Simulation of Low Dropout Regulator Chaitra S Kumar 1, K Sujatha 2 1 MTech Student, Department of Electronics, BMSCE, Bangalore, India 2 Assistant Professor, Department of Electronics, BMSCE,
More informationELECTRICAL CIRCUITS 6. OPERATIONAL AMPLIFIERS PART III DYNAMIC RESPONSE
77 ELECTRICAL CIRCUITS 6. PERATAL AMPLIIERS PART III DYNAMIC RESPNSE Introduction In the first 2 handouts on opamps the focus was on DC for the ideal and nonideal opamp. The perfect opamp assumptions
More informationHigh Gain Low Power Operational Amplifier Design and Compensation Techniques
Brigham Young University BYU ScholarsArchive All Theses and Dissertations 20070214 High Gain Low Power Operational Amplifier Design and Compensation Techniques Lisha Li Brigham Young University  Provo
More informationMicroelectronic Circuits  Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Feedback 1 Figure 8.1 General structure of the feedback amplifier. This is a signalflow diagram, and the quantities x represent either voltage or current signals. 2 Figure E8.1 3 Figure 8.2 Illustrating
More informationANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS
ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,
More informationChapter 10 Feedback ECE 3120 Microelectronics II Dr. Suketu Naik
1 Chapter 10 Feedback Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: ActiveLoaded Differential Pair 4. Ch 10: Feedback 5. Ch 11: Output
More information2. Single Stage OpAmps
/74 2. Single Stage OpAmps Francesc Serra Graells francesc.serra.graells@uab.cat Departament de Microelectrònica i Sistemes Electrònics Universitat Autònoma de Barcelona paco.serra@imbcnm.csic.es Integrated
More informationGechstudentszone.wordpress.com
8.1 Operational Amplifier (OpAmp) UNIT 8: Operational Amplifier An operational amplifier ("opamp") is a DCcoupled highgain electronic voltage amplifier with a differential input and, usually, a singleended
More informationDESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT
DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT PRADEEP G CHAGASHETTI Mr. H.V. RAVISH ARADHYA Department of E&C Department of E&C R.V.COLLEGE of ENGINEERING R.V.COLLEGE of ENGINEERING Bangalore
More informationDesign and Simulation of an Operational Amplifier with High Gain and Bandwidth for Switched Capacitor Filters
IOSR Journal of Electrical and Electronics Engineering (IOSRJEEE) eissn: 22781676,pISSN: 23203331, Volume 11, Issue 1 Ver. II (Jan. Feb. 2016), PP 4753 www.iosrjournals.org Design and Simulation
More informationLow Power and Fast Transient High Swing CMOS Telescopic Operational Amplifier
RESEARCH ARTICLE OPEN ACCESS Low Power and Fast Transient High Swing CMOS Telescopic Operational Amplifier Akshay Kumar Kansal 1, Asst Prof. Gayatri Sakya 2 Electronics and Communication Department, 1,2
More informationDesign of Twostage High Gain Operational Amplifier Using Current Buffer Compensation for Low Power Applications
Design of Twostage High Gain Operational Amplifier Using Current Buffer Compensation for Low Power Applications Thesis submitted in partial fulfillment of the requirement for the award of degree of Master
More informationSelfBiased PLL/DLL. ECG minute Final Project Presentation. Wenlan Wu Electrical and Computer Engineering University of Nevada Las Vegas
SelfBiased PLL/DLL ECG721 60minute Final Project Presentation Wenlan Wu Electrical and Computer Engineering University of Nevada Las Vegas Outline Motivation SelfBiasing Technique Differential Buffer
More informationAtypical op amp consists of a differential input stage,
IEEE JOURNAL OF SOLIDSTATE CIRCUITS, VOL. 33, NO. 6, JUNE 1998 915 LowVoltage Class Buffers with Quiescent Current Control Fan You, S. H. K. Embabi, and Edgar SánchezSinencio Abstract This paper presents
More informationA LOW DROPOUT VOLTAGE REGULATOR WITH ENHANCED TRANSCONDUCTANCE ERROR AMPLIFIER AND SMALL OUTPUT VOLTAGE VARIATIONS
ISSN 13137069 (print) ISSN 13133551 (online) Trakia Journal of Sciences, No 4, pp 441448, 2014 Copyright 2014 Trakia University Available online at: http://www.unisz.bg doi:10.15547/tjs.2014.04.015
More informationDESIGN HIGH SPEED, LOW NOISE, LOW POWER TWO STAGE CMOS OPERATIONAL AMPLIFIER. Himanshu Shekhar* 1, Amit Rajput 1
ISSN 22772685 IJESR/June 2014/ Vol4/Issue6/319323 Himanshu Shekhar et al./ International Journal of Engineering & Science Research DESIGN HIGH SPEED, LOW NOISE, LOW POWER TWO STAGE CMOS OPERATIONAL
More informationDesign and implementation of two stage operational amplifier
Design and implementation of two stage operational amplifier Priyanka T 1, Dr. H S Aravind 2, Yatheesh Hg 3 1M.Tech student, Dept, of ECE JSSATE Bengaluru 2Professor and HOD, Dept, of ECE JSSATE Bengaluru
More informationA LowVoltage, LowPower, TwoStage Amplifier for SwitchedCapacitor Applications in 90 nm CMOS Process
A LowVoltage, LowPower, TwoStage Amplifier for SwitchedCapacitor Applications in 90 nm CMOS Process S. H. Mirhosseini* and A. Ayatollahi* Downloaded from ijeee.iust.ac.ir at 16:45 IRDT on Tuesday April
More informationChapter 13: Introduction to Switched Capacitor Circuits
Chapter 13: Introduction to Switched Capacitor Circuits 13.1 General Considerations 13.2 Sampling Switches 13.3 SwitchedCapacitor Amplifiers 13.4 SwitchedCapacitor Integrator 13.5 SwitchedCapacitor
More informationLecture 200 Cascode Op Amps  II (2/18/02) Page 2001
Lecture 200 Cascode Op Amps II (2/18/02) Page 2001 LECTURE 200 CASCODE OP AMPS II (READING: GHLM 443453, AH 293309) Objective The objective of this presentation is: 1.) Develop cascode op amp architectures
More informationDesign of a Folded Cascode Operational Amplifier in a 1.2 Micron SiliconCarbide CMOS Process
University of Arkansas, Fayetteville ScholarWorks@UARK Electrical Engineering Undergraduate Honors Theses Electrical Engineering 52017 Design of a Folded Cascode Operational Amplifier in a 1.2 Micron
More informationSingle Supply, Rail to Rail Low Power FETInput Op Amp AD820
a FEATURES True Single Supply Operation Output Swings RailtoRail Input Voltage Range Extends Below Ground Single Supply Capability from + V to + V Dual Supply Capability from. V to 8 V Excellent Load
More informationDesign of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching
RESEARCH ARTICLE OPEN ACCESS Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching Annu Saini, Prity Yadav (M.Tech. Student, Department
More informationLowoutputimpedance BiCMOS voltage buffer
Lowoutputimpedance BiCMOS voltage buffer Johan Bauwelinck, a) Wei Chen, Dieter Verhulst, Yves Martens, Peter Ossieur, XingZhi Qiu, and Jan Vandewege Ghent University, INTEC/IMEC, Gent, 9000, Belgium
More informationChapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier
Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in doubleended
More informationLow Cost, General Purpose High Speed JFET Amplifier AD825
a FEATURES High Speed 41 MHz, 3 db Bandwidth 125 V/ s Slew Rate 8 ns Settling Time Input Bias Current of 2 pa and Noise Current of 1 fa/ Hz Input Voltage Noise of 12 nv/ Hz Fully Specified Power Supplies:
More informationLecture 030 ECE4430 Review III (1/9/04) Page 0301
Lecture 030 ECE4430 Review III (1/9/04) Page 0301 LECTURE 030 ECE 4430 REVIEW III (READING: GHLM Chaps. 3 and 4) Objective The objective of this presentation is: 1.) Identify the prerequisite material
More informationSingle Supply, Rail to Rail Low Power FETInput Op Amp AD820
a FEATURES True Single Supply Operation Output Swings RailtoRail Input Voltage Range Extends Below Ground Single Supply Capability from V to V Dual Supply Capability from. V to 8 V Excellent Load Drive
More informationI1 19u 5V R11 1MEG IDC Q7 Q2N3904 Q2N3904. Figure 3.1 A scaled down 741 op amp used in this lab
Lab 3: 74 Op amp Purpose: The purpose of this laboratory is to become familiar with a two stage operational amplifier (op amp). Students will analyze the circuit manually and compare the results with SPICE.
More informationAnalysis and Design of Analog Integrated Circuits Lecture 18. Key Opamp Specifications
Analysis and Design of Analog Integrated Circuits Lecture 8 Key Opamp Specifications Michael H. Perrott April 8, 0 Copyright 0 by Michael H. Perrott All rights reserved. Recall: Key Specifications of Opamps
More informationGATE: Electronics MCQs (Practice Test 1 of 13)
GATE: Electronics MCQs (Practice Test 1 of 13) 1. Removing bypass capacitor across the emitter leg resistor in a CE amplifier causes a. increase in current gain b. decrease in current gain c. increase
More information2.996/6.971 Biomedical Devices Design Laboratory Lecture 7: OpAmps
2.996/6.971 Biomedical Devices Design Laboratory Lecture 7: OpAmps Instructor: Dr. Hong Ma Oct. 3, 2007 Fundamental Circuit: Source and Load Sources Power supply Signal Generator Sensor Amplifier output
More informationCurrent Supply Topology. CMOS Cascode Transconductance Amplifier. Basic topology. pchannel cascode current supply is an obvious solution
CMOS Cascode Transconductance Amplifier Basic topology. Current Supply Topology pchannel cascode current supply is an obvious solution Current supply must have a very high source resistance r oc since
More information20129th International MultiConference on Systems, Signals and Devices An Enhanced Fully Differential Recyclic Folded Cascade OTA
2012 9th International MultiConference on Systems, Signals and Devices An Enhanced Fully Differential Recyclic Folded Cascade OTA Pravanjan Patra, S.Kumaravel Research scholar, ECE Tiruchirappalli, INDIA
More informationChapter 9: Operational Amplifiers
Chapter 9: Operational Amplifiers The Operational Amplifier (or opamp) is the ideal, simple amplifier. It is an integrated circuit (IC). An IC contains many discrete components (resistors, capacitors,
More informationLM6361/LM6364/LM6365 Fast VIP Op Amps Offer High Speed at Low Power Consumption
LM6361/LM6364/LM6365 Fast VIP Op Amps Offer High Speed at Low Power Consumption The LM6361/LM6364/LM6365 family of op amps are widebandwidth monolithic amplifiers which offer improved speed and stability
More informationBJT Circuits (MCQs of Moderate Complexity)
BJT Circuits (MCQs of Moderate Complexity) 1. The current ib through base of a silicon npn transistor is 1+0.1 cos (1000πt) ma. At 300K, the rπ in the small signal model of the transistor is i b B C r
More informationULTRA HIGH SPEED SINGLE OPERATIONAL AMPLIFIER
ULTRA HIGH SPEED SINGLE OPERATIONAL AMPLIFIER GENERAL DESCRIPTION The NJM711 is an ultra high speed single operational amplifier. It can swings 6V/µs high slew rate and 1GHz gain band width product(1mhz
More informationLDO Regulator Stability Using Ceramic Output Capacitors
LDO Regulator Stability Using Ceramic Output Capacitors Introduction Ultralow ESR capacitors such as ceramics are highly desirable because they can support fastchanging load transients and also bypass
More informationUniversity of Southern California School Of Engineering Department Of Electrical Engineering
University of Southern California School Of Engineering Department Of Electrical Engineering EE 448: Homework Assignment #02 Fall, 2001 ( Assigned 09/10/01; Due 09/19/01) Choma Problem #05: n an attempt
More informationDAT175: Topics in Electronic System Design
DAT175: Topics in Electronic System Design Analog Readout Circuitry for Hearing Aid in STM90nm 21 February 2010 Remzi Yagiz Mungan v1.10 1. Introduction In this project, the aim is to design an adjustable
More informationA 6 th Order Ladder SwitchedCapacitor Bandpass Filter with a center frequency of 10 MHz and a Q of 20
A 6 th Order Ladder SwitchedCapacitor Bandpass Filter with a center frequency of 10 MHz and a Q of 20 Joseph Adut,Chaitanya Krishna Chava, José SilvaMartínez March 27, 2002 Texas A&M University Analog
More informationA low voltage railtorail operational amplifier with constant operation and improved process robustness
Graduate Theses and Dissertations Graduate College 2009 A low voltage railtorail operational amplifier with constant operation and improved process robustness Rien Lerone Beal Iowa State University Follow
More informationFULL ONCHIP CMOS LOW DROPOUT VOLTAGE REGULATOR WITH 41 db AT 1 MHZ FOR WIRELESS APPLICATIONS
FULL ONCHIP CMOS LOW DROPOUT VOLTAGE REGULATOR WITH 41 db AT 1 MHZ FOR WIRELESS APPLICATIONS 1 ZARED KAMAL, 2 QJIDAA HASSAN, 3 ZOUAK MOHCINE 1, 3 Faculty of Sciences and Technology, Electrical Engineering
More informationA Low Dropout Voltage Regulator with Enhanced Transconductance Error Amplifier and Small Output Voltage Variations
A Low Dropout Voltage Regulator with Enhanced Transconductance Error Amplifier and Small Output Voltage Variations Ebrahim Abiri*, Mohammad Reza Salehi**, and Sara Mohammadalinejadi*** Department of Electrical
More informationIJSRD  International Journal for Scientific Research & Development Vol. 4, Issue 02, 2016 ISSN (online):
IJSRD  International Journal for Scientific Research & Development Vol. 4, Issue 02, 2016 ISSN (online): 23210613 Design & Analysis of CMOS Telescopic Operational Transconductance Amplifier (OTA) with
More informationISSN:
468 Modeling and Design of a CMOS Low Dropout (LDO) Voltage Regulator PRIYADARSHINI JAINAPUR 1, CHIRAG SHARMA 2 1 Department of E&CE, Nitte Meenakshi Institute of Technology, Yelahanka, Bangalore560064,
More informationCMOS Digital Integrated Circuits Analysis and Design
CMOS Digital Integrated Circuits Analysis and Design Chapter 8 Sequential MOS Logic Circuits 1 Introduction Combinational logic circuit Lack the capability of storing any previous events Nonregenerative
More informationUMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency
UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency Jamie E. Reinhold December 15, 2011 Abstract The design, simulation and layout of a UMAINE ECE Morse code Read Only Memory and transmitter
More informationOperational Amplifiers
Monolithic Amplifier Circuits: Operational Amplifiers Chapter Jón Tómas Guðmundsson tumi@hi.is. Week Fall 200 Operational amplifiers (op amps) are an integral part of many analog and mixedsignal systems
More informationPHYS 536 The Golden Rules of Op Amps. Characteristics of an Ideal Op Amp
PHYS 536 The Golden Rules of Op Amps Introduction The purpose of this experiment is to illustrate the golden rules of negative feedback for a variety of circuits. These concepts permit you to create and
More informationLecture 3 SwitchedCapacitor Circuits Trevor Caldwell
Advanced Analog Circuits Lecture 3 SwitchedCapacitor Circuits Trevor Caldwell trevor.caldwell@analog.com Lecture Plan Date Lecture (Wednesday 24pm) Reference Homework 20170111 1 MOD1 & MOD2 ST 2, 3,
More informationV CC OUT MAX9945 IN+ V EE
194398; Rev 1; 12/ 38V, LowNoise, MOSInput, General Description The operational amplifier features an excellent combination of low operating power and low input voltage noise. In addition, MOS inputs
More informationDual FETInput, Low Distortion OPERATIONAL AMPLIFIER
Dual FETInput, Low Distortion OPERATIONAL AMPLIFIER FEATURES LOW DISTORTION:.3% at khz LOW NOISE: nv/ Hz HIGH SLEW RATE: 2V/µs WIDE GAINBANDWIDTH: 2MHz UNITYGAIN STABLE WIDE SUPPLY RANGE: V S = ±4.
More information250 MHz, General Purpose Voltage Feedback Op Amps AD8047/AD8048
5 MHz, General Purpose Voltage Feedback Op Amps AD8/AD88 FEATURES Wide Bandwidth AD8, G = + AD88, G = + Small Signal 5 MHz 6 MHz Large Signal ( V pp) MHz 6 MHz 5.8 ma Typical Supply Current Low Distortion,
More informationDEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS 02139
DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS 019.101 Introductory Analog Electronics Laboratory Laboratory No. READING ASSIGNMENT
More information6.776 High Speed Communication Circuits and Systems Lecture 14 Voltage Controlled Oscillators
6.776 High Speed Communication Circuits and Systems Lecture 14 Voltage Controlled Oscillators Massachusetts Institute of Technology March 29, 2005 Copyright 2005 by Michael H. Perrott VCO Design for Narrowband
More information800 MHz, 4:1 Analog Multiplexer ADV3221/ADV3222
8 MHz, : Analog Multiplexer ADV/ADV FEATURES Excellent ac performance db bandwidth 8 MHz ( mv pp) 7 MHz ( V pp) Slew rate: V/μs Low power: 7 mw, VS = ± V Excellent video performance MHz,. db gain flatness.%
More informationChapter.8: Oscillators
Chapter.8: Oscillators Objectives: To understand The basic operation of an Oscillator the working of low frequency oscillators RC phase shift oscillator Wien bridge Oscillator the working of tuned oscillator
More informationThe Miller Approximation. CE Frequency Response. The exact analysis is worked out on pp of H&S.
CE Frequency Response The exact analysis is worked out on pp. 63964 of H&S. The Miller Approximation Therefore, we consider the effect of C µ on the input node only V  out V s = r g π m 
More informationLow Power OpAmp Based on Weak Inversion with MillerCascoded Frequency Compensation
Low Power OpAmp Based on Weak Inversion with MillerCascoded Frequency Compensation Maryam Borhani, Farhad Razaghian Abstract A design for a railtorail input and output operational amplifier is introduced.
More informationDesign of a Low Noise Amplifier using 0.18µm CMOS technology
The International Journal Of Engineering And Science (IJES) Volume 4 Issue 6 Pages PP.1116 June  2015 ISSN (e): 2319 1813 ISSN (p): 2319 1805 Design of a Low Noise Amplifier using 0.18µm CMOS technology
More information