Analog Integrated Circuits Fundamental Building Blocks


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1 Analog Integrated Circuits Fundamental Building Blocks Basic OTA/Opamp architectures Faculty of Electronics Telecommunications and Information Technology Gabor Csipkes Bases of Electronics Department
2 Outline definition of the OTA/opamp cascade of amplifier stages the general opamp architecture the uncompensated Miller opamp small signal model at low and high frequencies step response of a second order system with unity feedback the two stage opamp with Miller compensation models and parameters sizing algorithm for the two stage Miller opamp the telescopic opamp voltage budget, models and parameters sizing algorithm of the telescopic opamp the folded cascode opamp small signal low and high frequency model sizing algorithm for the folded cascode opamp Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 2
3 The ideal opamp  definitions ideal opamp = a differential input, voltage controlled voltage source with very large open loop gain the ideal gain is frequency independent, but real gain can be modeled with a set of poles and zeros typically low pass behavior very large input resistance and near zero output resistance opamps with strictly capacitive loads can have large output resistance Operational Transconductance Amplifiers (OTA) often also called opamp the output may be single ended (referenced to ground) or differential single or symmetrical supply voltages out V a V V Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 3
4 The opamp a cascade of elementary stages the typical opamp architecture a differential amplifier followed by a high gain inverting stage and a voltage follower for low output impedance the voltage follower may be missing if the load is known to be strictly capacitive frequency compensation for closed loop stability probably required (more on this later) elementary amplifier stages subsequent VI and IV conversions most simple form the two stage opamp VI IV IV cascade of elementary stages VI Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 4
5 The two stage or Miller opamp Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 5
6 The two stage opamp the small signal low frequency model with two equivalent stages no capacitive effects low frequency or DC voltage gain each stage can be analyzed individually G m and R out specific to each configuration V G m 1 g m 1,2 R r r Gm 2 gm6 R r r out1 DS 2 DS 4 out 2 DS 6 DS 7 a0 Gm 1Rout1 Gm2R out 2 a a 1 2 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 6
7 The two stage opamp the small signal high frequency model consider load and parasitic capacitances V C1 C2 CGD 1,2 C C C C C C4 CGD 4 C5 CGS 6 CDB2 CDB4 C6 CGD6 C7 CL CDB6 CDB7 CL 3 GS 3 GS 4 DB1 DB3 a( s) a 1 sr C 1 sr C 0 out1 5 out 2 7 The frequency response is dominated by C 5 and C 7 due to the large R out1 and R out2! Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 7
8 The two stage opamp with negative feedback the closed loop model of an opamp with negative feedback A( s) a a( s) a( s) 0 s s 1 a( s) r 1 1 p1 p2 The closed loop gain: A( s) 0 p1 p2 0 a( s) 1 a0r 2 1 ( ) 1 a p1 p2 p1 p2 0 1 a r a s r s s a r The standard form of a second order transfer function: (DC gain A 0, resonant frequency ω n and damping factor ξ ) A n A ( s ) s 2 0 n 2 2 2n s n A a 1 ; 1 a r ; a r r a r 0 p1 p2 0 n p1 p p1 p2 1 0 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 8
9 Frequency response of a second order system the effect of the feedback transmittance r on the magnitude response A 0 1 r A 0 decreases with r Overshoot of the frequency response at ω n complex poles under damped step response worst case stability for unity gain (r=1 and A 0 =1) lowest ξ for given a 0, ω p1 and ω p2 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 9
10 Step response for unity gain feedback the time domain step response is calculated as damping of the oscillation amplitude depends on ξ V out ( t) 1 A( s) L s typically, if poles ω p1 and ω p2 are close to each other ξ<1 under damped system with fading oscillations of the step response n t 2 e 2 1 Vout ( t) 1 sin 1 arctan 2 n t 1 fading exponential oscillations with the period envelope depending on ω n and ξ since the sin function varies between 1 and 1 time domain overshoot around the unit step the overshoot and number of cycles until settling increases with a smaller ξ Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 10
11 Step response for unity gain feedback step response of the two stage opamp in unity gain feedback configuration optimal response the circuit is unusable as amplifier for small ξ due to the very long settling time the response stability depends on the phase margin (m φ ) optimal response for m φ =65 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 11
12 closed loop gain for unity feedback: A( s) Stability and phase margin a( s) 1 a( s) What if denominator is 0??? a( s) 1 the closed loop gain approaches even for no input any perturbation is amplified with under damped transients sustained oscillations occur, feedback turns positive and system becomes unstable a( j) 1 Barkhausen's stability criteria: a( j) 180 a j 1 j p 1 p2 solve for ω f 0dB m 180 a j odb 180 arctan arctan 0dB 0dB p1 p2 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 12
13 Pole locations and phase margin the relation between pole frequencies and f 0dB defines m φ and the stability of the step response This is what we need! f f p2 0dB m 45 f f p2 0dB m 45 f f p2 0dB m 45 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 13
14 Frequency compensation need f p2 >f 0dB so that m φ >45 impossible to achieve by simply cascading a differential amplifier and a common source inverting amplifier f p 1 f p2 1 2 R C 1 2 R out1 5 C out 2 7 Typically: R C R out1 out 2 C 7 5 f p1 and f p2 are close to each other!!! We need to manipulate pole locations to separate f p1 and f p2 frequency compensation Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 14
15 Miller frequency compensation idea 1: push p 1 to lower frequencies by increasing C 5 must have very large values for a satisfactory m φ not practical for the integrated opamp idea 2: use the Miller effect to virtually increase C 5 practical solution since the gain of the second stage is usually large connect C M that emphasizes the capacitive shunt around the inverting second stage V Gm 1V in sc5v scm V Vout Rout1 Vout Gm2V sclvout scm V Vout Rout 2 0 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 15
16 Miller frequency compensation capacitances C 1,C 2, C 3,C 4 and C 6 considered small and neglected for simplicity the frequency dependent gain a(s) results: C M Gm 1 Gm2 Rout1 Rout 2 1 s G m2 a( s) dominant terms 2 k2s k1s 1 k2 Rout1Rout 2 C5CL C5CM CLCM k1 Rout1C5 Rout 2CL Rout1 Rout 2 CM Gm2Rout1Rout 2CM use the dominant pole approximation to find pole and zero locations a( s) C M Gm 1Gm 2Rout1Rout 2 1 s G m2 2 out1 out 2 L M m2 out1 out 2 M R R C C s G R R C s 1 a( s) s a0 1 zp s s 1 1 p1 p2 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 16
17 Miller compensation frequency response One dominant pole, one high frequency pole and one right half plane zero: a0 Gm 1Gm 2Rout1Rout 2 1 f p1( d ) 2 G R R C f f p2 zp G 2 C m2 G 2C m 2 L M m2 out 2 out1 M GBW a f 0 p1( d ) G 2C m1 M m GBW GBW 90 arctan arctan f f p2 zp Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 17
18 Miller compensation step response assume unity gain negative feedback and apply an input step to the follower 1 A( s) step response calculated as Vout ( t) L s V Slew Rate (SR) variation rate of the output voltage SR tt Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 18
19 The two stage compensated opamp slew rate the total capacitance of every node must be charged and discharged in each cycle charging rate depends on the largest supplied current every node limits the variation rate of V out the slew rate is imposed by the most stringent limitation Vout SR min SR, SR t I5 I7 SR1 ; SR2 CM CL 1 2 Typically I 5 <<I 7, while C M and C L are comparable SR I C 5 M Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 19
20 The two stage opamp design algorithm specifications given (others are also possible) the low frequency open loop gain a 0 larger than a critical value slew rate (SR) unitygain bandwidth (GBW) the right half plane zero frequency relative to GBW (ratio k imposed by the designer!) the typical load capacitance C L supply voltages phase margin m φ chosen according to the application (often unconditional stability!) typical transistor V DSat voltages (unless resulting from design constraints! ) Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 20
21 The two stage opamp design algorithm Step 1 calculate the required compensation capacitor C M relative to C L Gm 1 GBW 2 CM Gm2 f zp k GBW 2CM GBW f p2 G 2 C Gm2 2C L m1 M G G m1 m2 1 k GBW G C C f G C kc m1 L L p2 m2 M M GBW 1 m f GBW, f p2, f zp tan 90 m arctan f p2 k C M k C L 1 tan 90 m arctan k Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 21
22 The two stage opamp design algorithm Step 2 calculate the differential stage bias current for a given SR and C M SR I C 5 M I SR C 5 M Step 3 calculate the transconductances G m1 and G m2 GBW G m1 Gm 1 2 GBW CM Gm2 k Gm 1 2CM Step 4 find V DSat and the geometry of the input transistors G 2I I D 1,2 I5 g m V I V 5 DSat1,2 W DSat1,2 VDSat1,2 G L m1 1 m1 1,2 W W Step 5 choose V DSat for M 3, M 4 and M 5 ; L 3,4 L 5 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 22
23 The two stage opamp design algorithm Step 6 balance the M 3 M 4 current mirror by choosing V DSat3 =V DSat4 =V DSat6 and find the geometry of M 6 G m2 2I 2I V V D6 7 DSat 6 DSat 6 1 I G V 2 7 m2 DSat6 W L 6 Step 7 choose V DSat7 =V DSat5 and determine the geometry of M 7 W L 7 Further ideas: remember the body effect and the parasitic capacitances G m s will always be smaller than expected while capacitances will always be larger oversize try to set all currents to be integer multiples of a given bias current use a current mirror based biasing scheme instead of voltages iteratively simulate and optimize the design until all specifications have been met Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 23
24 The folded cascode opamp Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 24
25 The folded cascode opamp another typical opamp architecture a differential amplifier followed by a current buffer and a cascode output stage for large R out an additional output voltage follower may be used if the load is not strictly capacitive no need for frequency compensation (more on this later) elementary amplifier stages a single VI and IV conversion pair II IV cascade of elementary stages (transconductance, common gate and transimpedance) VI Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 25
26 the small signal low frequency model with two equivalent stages no capacitive effects low frequency or DC voltage gain The folded cascode opamp the current buffer a subsequent IV and VI conversion pair with R p and G mp adjusted to provide a unity current gain V p1 V p2 Gm gm 1,2 1 1 Rp a Gmp g m6,7 R g r r g r r out m9 DS 9 DS11 m7 DS 7 DS 5 G R 0 m out Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 26
27 The folded cascode opamp the small signal high frequency model consider the load and the dominant parasitic capacitances C p1 C p2 CDB 1 CDB4 CGD 4 CSB6 CGS 6 C p1 C p2 CC p 2 2 a( s) a 1 sroutcl 1 srpc p 0 Since R out >>R p and C L >>C p, the poles are always separated and the phase margin will be typically large (m φ >70 ), even if mirror singularities are considered No need for frequency compensation the circuit typically works at larger frequencies than the stable two stage opamp Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 27
28 The folded cascode opamp frequency response One dominant pole and one high frequency pole (mirror singularities neglected): a0 GmRout 1 f p1( d ) 2 RoutCL 1 Gmp f p2 2 R C 2 C p p p GBW a f 0 p1( d ) Gm 2C L m GBW 90 arctan f p2 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 28
29 The folded cascode opamp step response assume unity gain negative feedback and apply an input step to the follower 1 step response calculated as A( s) Vout ( t) L s V Slew Rate (SR) variation rate of the output voltage SR tt large phase margin no overshoot Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 29
30 The folded cascode opamp slew rate the total capacitance of every node must be charged and discharged in each cycle charging rate depends on the largest current supplied to the node capacitances the folding node is charged rapidly SR limited by the output node SR I C B L Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 30
31 The folded cascode opamp design algorithm Step 1 calculate the required input stage transconductance GBW Gm 1 2C L G g GBW C m1 m1,2 2 L Step 2 calculate the required input stage bias current I I SR C C B 3 3 L L L I SR C Step 3 calculate the V DSat1,2 voltage and the differential transistor pair geometry g m1,2 2I D 1,2 I3 V VDSat g V 1,2 m I 1,2 3 DSat1,2 DSat1,2 W L 1,2 W Step 4 choose V DSat3 and calculate the geometry of M 3 L 3 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 31
32 The folded cascode opamp design algorithm Step 5 choose I D6,7 =I D8,9 =I D10,11 =( ) I D1,2 to avoid completely turning off the cascode stage when the opamp is slew rate limited (all I 3 flows through M 1 or M 2 ) I D6,7 D1,2 I I I I I D4,5 D1,2 D6,7 D1,2 Step 7 choose V DSat for all transistors (except M 1, M 2 and M 3 ) and determine the geometries Further ideas: remember the body effect and the parasitic capacitances G m s will always be smaller than expected while capacitances will always be larger oversize try to set all currents to be integer multiples of a given bias current use a current mirror based biasing scheme instead of voltages iteratively simulate and optimize the design until all specifications have been met Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 32
33 Bibliography P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, Oxford University Press, 2002 B. Razavi, Design of Analog CMOS Integrated Circuits, McGrawHill, 2002 D. Johns, K. Martin, Analog Integrated Circuit Design, Wiley, 1996 P.R.Gray, P.J.Hurst, S.H.Lewis, R.G, Meyer, Analysis and Design of Analog Integrated Circuits, Wiley,2009 R.J. Baker, CMOS Circuit Design, Layout and Simulation, 3 rd edition, IEEE Press, 2010 Analog Integrated Circuits Fundamental building blocks Basic OTA/Opamp architectures 33
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