ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN

Transcription

1 ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN OPAMP DESIGN AND SIMULATION Vishal Saxena

2 OPAMP DESIGN PROJECT R 2 v out v in /2 R 1 C L v in v out V CM R L V CM C L V CM -v in /2 R 1 C L (a) (b) R 2 ECE415/EO ECE515

3 DESIGN SPECIFICATIONS

4 TWO-STAGE OPAMP

5 TWO-STAGE OPAMP: MILLER COMPENSATION

6 MILLER COMPENSATION EQUATIONS

7 TWO-STAGE OPAMP: ZERO-NULLING R

8 VOLTAGE BUFFER COMPENSATION

9 COMMON-GATE COMPENSATION

10 CLASS-A STAGE: SLEWING

11 CLASS-AB STAGE: FLOATING MIRROR

12 TELESCOPIC+CLASS-AB STAGE V bias2 V bias5 Note that in this schematic, Indirect compensation is used. Cc is connected between v out and an internal lowimpedance node For Miller compensation, connect Cc between nodes 1 and 2. V bias5 is generated using a replica bias circuit

13 FOLDED-CASCODE STAGE

14 FOLDED-CASCODE WITH CLASS-AB OUTPUT Note that in this schematic, Indirect compensation is used. Cc is connected between v out and an internal lowimpedance node For Miller compensation, connect Cc between nodes 1 and 2.

15 FC+CLASS-AB+RAIL-TO-RAIL INPUT

16 GAIN ENHANCEMENT Note that in this schematic, Indirect compensation is used. Cc is connected between v out and an internal lowimpedance node For Miller compensation, connect Cc between nodes 1 and 2.

17 CADENCE SPECTRE STB ANALYSIS

18 SPECTRE STB ANALYSIS The STB analysis linearizes the circuit about the DC operating point and computes the loop-gain, gain and phase margins (if the sweep variable is frequency), for a feedback loop or a gain device [1]. Refer to the Spectre Simulation Refrence [1] and [2] for details.

19 EXAMPLE SINGLE-ENDED OPAMP SCHEMATIC

20 STB ANALYSIS TEST BENCH Pay attention to the iprobe component (from analoglib) Acts as a short for DC, but breaks the loop in stb analysis Place the probe at a point where it completely breaks (all) the loop(s).

21 DC ANNOTATION Annotating the node voltages and DC operating points of the devices helps debug the design Check device gds to see if its in triode or saturation regions

22 SIMULATION SETUP

23 BODE PLOT SETUP Results->Direct Plot-> Main Form

24 OPEN-LOOP RESPONSE (BODE PLOTS) Here, f un =152.5 MHz, PM=41.8 Best to use the stb analysis with circuit is in the desired feedback configuration Break the loop with realistic DC operation points

25 SMALL STEP RESPONSE 10mV Observe the ringing (PM was 41 ) Compensate more ( Cc and/or g m2 )

26 LARGE STEP RESPONSE 500mV Note the slewing in the output Class-A: I 2 /C L Class-AB: I SS /C C

27 XF ANALYSIS (FOR CMRR, PSRR) For CMRR and PSRR plots, you can use xf analysis. Set up your testbench sources for the supplies (of course), but also a source representing the common mode voltage. Then run an xf analysis and tell it where the output of the circuit. You can then plot the transfer function from every source to the differential output of the circuit.

28 XF ANALYSIS XF analysis simultaneously computes individual transfer functions from every independent source to a single output.

29 TWO-STAGE OPAMP COMPENSATION TECHNIQUES

30 MILLER COMPENSATION VDD M3 v m v i p C fb M1 M2 v out M6TL M6BL V bias3 V bias4 Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2. VDD M4 M6TR M6BR 1 750Ω i C ff C C M8T M8B VDD M7 10pF x10 220/ /2 100/2 C L 30pF Compensation capacitor (C c ) between the output of the gain stages causes pole-splitting and achieves dominant pole compensation. An RHP zero exists at Due to feed-forward component of the compensation current (i C ). The second pole is located at The unity-gain frequency is A benign undershoot in step-response due to the RHP zero All the op-amps presented have been designed in AMI C5N 0.5μm CMOS process with scale=0.3 μm and L min =2. The op-amps drive a 30pF off-chip load offered by the test-setup.

31 DRAWBACKS OF MILLER COMPENSATION VDD M3 v m v p vout M6TL M6BL M1 V bias3 V bias4 Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2. VDD M2 M4 M6TR M6BR 1 C C 10pF M8T M8B VDD M7 x10 220/ /2 100/2 C L 30pF The RHP zero decreases phase margin Requires large C C for compensation (10pF here for a 30pF load!). Slow-speed for a given load, C L. Poor PSRR Supply noise feeds to the output through C C. Large layout size.

32 v m v p INDIRECT (AHUJA) COMPENSATION VDD M3 M6TL M6BL M1 V bias3 V bias4 M6TR M6BR Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2. VDD M2 M4 M10T M10B M CG VDD M9 A i c 1 C c M8T M8B VDD x10 M7 220/ /2 100/2 An indirect-compensated op-amp using a common-gate stage. v out C L 30pF The RHP zero can be eliminated by blocking the feed-forward compensation current component by using A common gate stage, A voltage buffer, Common gate embedded in the cascode diffamp, or A current mirror buffer. Now, the compensation current is fed-back from the output to node-1 indirectly through a low-z node-a. Since node-1 is not loaded by C C, this results in higher unity-gain frequency (f un ).

33 INDIRECT (CASCODE) COMPENSATION VDD M3T M3B M4B V bias2 v m v p vout M6TL M6BL M1 V bias3 V bias4 M4T Unlabeled NMOS are 10/2. Unlabeled PMOS are 44/2. VDD M2 A 1 M6TR M6BR i c C C M7 1.5pF M8T M8B VDD 110/2 2 50/2 50/2 C L 30pF Indirect-compensation using cascoded current mirror load. VDD M3 M1T v out A v m v p 1.5pF 2 M1B M2B V bias3 M5T V bias4 M5B V bias5 30/2 30/2 Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2. VDD 1 M4 M2T i c C C M7 M8T M8B VDD 220/2 100/2 100/2 C L 30pF Indirect-compensation using cascoded diff-pair. Employing the common gate device embedded in the cascode structure for indirect compensation avoids a separate buffer stage. Lower power consumption. Also voltage buffer reduces the swing which is avoided here.

34 Small signal analytical model INDIRECT COMPENSATION: MODELING C c + - v in R c A A 1 A 2 Differential Amplifier i c 1 2 Gain Stage Block Diagram v out v i out c 1 sc c R 1 c 2 g m1 v s R 1 C 1 g m2 v 1 R 2 C 2 v out C c R c The compensation current (i C ) is indirectly fed-back to node R C is the resistance attached to node-a.

35 Resistance r oc is assumed to be large. g mc >>r oc -1, R A -1, C C >>C A The small-signal model for a common gate indirect compensated opamp topology is approximated to the simplified model seen in the last slide.

36 INDIRECT COMPENSATION: EQUATIONS j un p 3 p 2 z 1 p 1 LHP zero Pole p 2 is much farther away from f un. Can use smaller g m2 =>less power! LHP zero improves phase margin. Much faster op-amp with lower power and smaller C C. Better slew rate as C C is smaller.

37 Amplitude Phase (deg) Magnitude (db) EFFECT OF LHP ZERO ON SETTLING In certain cases with indirect compensation, the LHP-zero (ω z,lhp ) shows up near f un. Causes gain flattening and degrades PM Hard to push out due to topology restrictions Ringing in closed-loop step response Used to be a benign undershoot with the RHP zero, here it can be pesky Is this settling behavior acceptable? Watch out for the ω z,lhp for clean settling behavior! When using indirect compensation be aware of the LHP-zero induced transient settling issues Bode Diagram Frequency (Hz) Closed Loop Step Response Time (sec) Small step-input settling in follower configuration x 10-7

38 REFERENCES 1. The Designer s Guide to SPICE and Spectre: 2. Spectre User Simulation Guide, pages : 3. M. Tian, V. Viswanathan, J. Hangtan, K. Kundert, Striving for Small-Signal Stability: Loop-based and Device-based Algorithms for Stability Analysis of Linear Analog Circuits in the Frequency Domain, Circuits and Devices, Jan Saxena V, Baker R.J., Indirect feedback compensation of CMOS op-amps, IEEE WMED 2006.

39 REFERENCES 6. Saxena V, Baker R.J., Indirect compensation techniques for three-stage CMOS op-amps, IEEE MWSCAS Saxena V., Baker R.J., Indirect compensation techniques for three-stage fully-differential op-amps, IEEE MWSCAS Saxena V. Indirect Feedback Compensation Technique for Multi-Stage Operational Amplifiers, MS Thesis, Boise State University, 2007.