Current Mirrors. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-1
|
|
- Elaine Gregory
- 5 years ago
- Views:
Transcription
1 Current Mirrors Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08
2 { Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08 { Current Source and Sink Symbol of current source + o deal current source Output resistance - o Practical - characteristics Current sink P Circuit + o N - o N Slope=/ o P MN Current source P + - N Circuit o o N Slope=(-/ o ) MN P P -
3 Simple Current Mirrors BJT out in Q + - out MN min CE(sat) MOSFET out = CE in + out min GS - T MN = DS Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-3 郭泰豪, Analog C Design, 08
4 ncrease Output esistance of Current Mirrors Using Cascode Structures in out + in out + Q M 4 M Q M 3 M Output impedance BJT: o = r o [+(g m +g o )(r //r o )] r o (+g m r ) MOSFET: o = r ds [+(g m +g mb+ g ds )r ds ] r ds g m r ds Minimum output voltage DC gain of M BJT: min = CE + CE(sat) BE(on) + CE(sat) MOSFET (assume the same size of M -4 same eff ): g4 = gs3 + gs4 = eff + T ; DS = g4 gs = eff + T min = DS(sat) + DS = eff + ( eff + T ) = eff + T Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-4 郭泰豪, Analog C Design, 08
5 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-5 郭泰豪, Analog C Design, 08 r ds =/λ and L λ For shorter channel lengths, L r ds OPAMP gain Cascode current mirrors can be used to increase output impedance. However, their signal swings are reduced. Wide-swing cascode current mirrors are needed. Example The basic idea is to bias the drain-source voltages of transistors Q and Q 3 to be close to the minimum possible without them going into the triode region. Wide-Swing Current Mirrors bias W / L ( n ) bias Q 5 Q and Q 3 must be biased right at the edge of the triode region. DD in W / L W / L n Q 4 W / L n Q Q 3 Q W / L out = in
6 Wide-Swing Current Mirrors (Cont.) Let eff be the effective transistor gate-source voltage, GS - th, which is also the minimum DS for a transistor to be biased in the saturation region. Assume all of the transistor drain currents are equal, then eff eff 3 w L n D C (W w L ox L) Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-6 郭泰豪, Analog C Design, 08 eff w L ( D DS n w L Cox Since n n n 3 5 L eff eff n 4 eff G G G (n ) eff 5 4 th DS DS G GS G (neff th) eff out eff eff (n ) eff W L ( w GS 4 DS = eff th ) GS ) DS
7 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-7 郭泰豪, Analog C Design, 08 Wide-Swing Current Mirrors (Cont.) A common choice: n =, out > eff For a safe design f in = bias, DS should be made a little larger (> eff ), 0.05 to 0. larger depending on transistor - or whether body effect exists. Choose a little larger and f in is a varying current, in bias must be satisfied (i.e. DS = DS3 eff ) W L W L 3
8 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-8 郭泰豪, Analog C Design, 08 Constant Transconductance Bias Circuit Biasing circuits that provide stable transconductances Transistor transconductances are matched to the conductance of a resistor. As a result, to a first-order effect, the transistor transconductances are independent of power-supply voltage as well as process and temperature variations. 5 Q 0 Q 5 Q 4 Q Example w L w L w L w L w 0 3 L Unity current mirror 4 Q 5 Q 3 B
9 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-9 郭泰豪, Analog C Design, 08 Constant Transconductance Bias Circuit (Cont.) g eff 3 D3 m3 D5 eff 5 D3 eff 3 D5 B the other current mirror equation Simple derivation g m3 g m3 is determined by geometric ratios only, independent of powersupply voltages, process parameters, temperature, or any other parameters with large variability. At point A, loop gain (W L) (W L) 5 (W L) (W L) 0 eff 3 B eff 5 3 eff 3 D0 A W L W L B 3 5 B start up circuit is needed D D0 D
10 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-0 郭泰豪, Analog C Design, 08 Constant Transconductance Bias Circuit (Cont.) For a special case, g m3 B w L w 4 5 L Thus, not only is g m3 stablized, but all other transistor transconductances are also stablized since the ratios of transistor currents are mainly dependent on geometry. 3 For all n-channel transistors g mi (W L) (W L) D3 m3 For all p-channel transistors g mi n p i 3 Di (W L) (W L) i 3 g Di D3 g m3
11 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08 Constant Transconductance Bias Circuit (Cont.) Second-order effect Body effect The equations will be slightly modified Output impedance effect Can be reduced using cascoded p-channel current mirror Temperature effect (i) μ is proportional to T -3/. This corresponds to a 7% μ reduction from 7 (300 k) to 00 (373 k) (ii) Since g m = / B and g m = μc ox (W/L) eff eff will be increased by 7% if temperature effect of B is ignored. (positive TC of B, if it is on-chip, can somewhat offset this increase) (iii) As long as eff has not been designed to be too large (or DD is large enough), this limitation is tolerable in most applications.
12 Widlar current sources Bipolar BE BE0 C04 EF T ln C04 C0 Trial and error todetermine 9μA C0 MOSFET O assume D0 D0 O 0 D K D0 K 4 ' O nput Stage Bias 4 4 K ' K 4 ' EF K 4 EF K EF ' K 4 ' 4 C0 4 EF Q - EE Q0 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08 K ' D0 0 K EF D0 4 ' EF M - EE C0 4 D0 M0 4
13 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-3 郭泰豪, Analog C Design, 08 Wide-Swing Constant Transconductance Bias Circuit Wide-swing current mirrors + constant g m bias circuit Q 8 Q 9 Q Q 4 Q 7 Q 0 Q Q Q 4 Q 3 Q 5 0 bias-p casc-p 0 0 Q 6 Q 8 Small W/L Q B 40 5kΩ 0 Q Q 5 0 Q 0 casc-n Q 7 bias-n Bias loop Cascode bias Start-up circuitry
14 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-4 郭泰豪, Analog C Design, 08 Wide-Swing Constant Transconductance Bias Circuit (Cont.) Wide-swing : Minimize DS of bias transistors to eff Constant g m : g m = / B Minimization of finite output impedance effect : Use cascode bias Start-up Approximate current characteristics of the bias loop DS(Q8 ) DS(Q ) 7 DS(Q8 ) B A At point A, loop gain (W / L) (W / L) DS (Q 7 ) (W / L) (W / L)
15 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-5 郭泰豪, Analog C Design, 08 Wide-Swing Constant Transconductance Bias Circuit (Cont.) Start-up (Cont.) Positive feedback bias loop: Two stable points, A and B. At point A, loop gain > must be satisfied. Operational principle of start-up circuit All currents in the bias loop are zero, Q 7 will be off Q 8 is always on, the gates of Q 5 and Q 6 will be pulled high Q 5 and Q 6 will inject currents into the bias loop, which will start up the circuit. Once the loop starts up, Q 7 will be on, pulling the gates of Q 5 and Q 6 low, and thereby turning them off so they no longer affect the bias loop. This circuit is only one example of a start-up loop, and there are many other variations. For example, sometimes Q 8, is replaced by an actual resistor
16 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-6 郭泰豪, Analog C Design, 08 Enhanced-Output-mpedance Current Mirrors General structure For wide-swing, bias eff out g m r ds r ds (+A) This technique for outputimpedance enhancement is not useful when bipolar Transistors (Q, Q, and Q 3 ) are used. in bias out out A out Q Q 3 Q out might be limited by db. This parasitic conductance, db, is a result of collisions between highly energized electrons resulting in electron-hole pairs to be generated with the holes escaping to the substrate. The generation of these electron-hole pairs is commonly called impact ionization.
17 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-7 郭泰豪, Analog C Design, 08 Enhanced-Output-mpedance Current Mirrors (Cont.) A simple implementation example : regulated cascode mirror out gmrdsrds[ gm3(rds3 ro )] rds3 where rds3 ro bias t is not useful when bipolar in ro transistors are used. ds = eff3 + th (not a wide-swing source) Q 3 Q 4 Q Q out
18 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-8 郭泰豪, Analog C Design, 08 Enhanced-Output-mpedance Current Mirrors (Cont.) Sackinger implementation in b b out Q 4 r o Q Q 6 Q 3 Q 5 Q Use regulated cascode to increase output impedance r ds3 out gmrdsrds[ gm3(rds3 ro )] where rds3 ro Q, Q, Q 3, B, out match Q 4, Q 5, Q 6, B, in, respectively. DS = DS5 = eff3 + tn rather than the minimum required, which could be equal to eff. This limitation is especially harmful for modern technologies operating with power voltages of 3.3 or lower.
19 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-9 郭泰豪, Analog C Design, 08 Enhanced-Output-mpedance Current Mirrors (Cont.) Wide-swing + enhance output-impedance current mirrors in 7 bias 4 bias 4 bias out = in Q 5 Q 7 bias bias Q Q 8 Q 4 Q Q 80 Q 6 Level shift in front of the common source amplifier in the regulated cascode current source
20 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-0 郭泰豪, Analog C Design, 08 Enhanced-Output-mpedance Current Mirrors (Cont.) All transistors are biased with nearly the same current density, except for Q 3 and Q 7. As a result, all transistors have the same effective gate-source voltage, eff, except for Q 3 and Q 7, which have gate-source voltage of eff because they are biased at four times the current density. G3 = eff + tn DS = S4 = G3 - GS4 = ( eff + tn ) - ( eff + tn ) = eff out > DS + eff = eff Current Mirror Symbol Symbol A circuit example DD DD K : K
21 ncrease Output esistance of Current Mirrors Using Emitter/Source-Degenerated Structures Large o of current source/sink => more like ideal current source/sink For MOSFET o λ o ' W K ( )( L GS T ) ( λ DS ) For BJT AF o C S C (e BE / )( CE / AF ) Negative feedback to increase o Emitter-Degenerated Source-Degenerated App4-4- Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
22 ncrease Output esistance of Current Mirrors Using Emitter/Source-Degenerated Structures (Cont.) Emitter-Degenerated out in + - v be + E r π g m v be r o Δ C + Δv - o E - o (r r o [ r r [ (g o // ) [ g o ro[ (gm go)(r r [ g (r // )] o (r // ) g m g m o )(r m (r m // )] (r // )]r // )] // )] o App4- Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
23 ncrease Output esistance of Current Mirrors Using Emitter/Source-Degenerated Structures (Cont.) Source-Degenerated in out o + D Δ + - g m v gs S G g mb v bs r ds Δ - Similarly, r g g g r g o ds m mb ds ds m App Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
24 ncrease o Using Wilson Current Mirror BJT r out out r in o3 β ( F3 β F β F ) out in Q 3 + out out in + Q 4 Q 3 out Q Q Q Q MOSFET out + r out r g ds3 m3 g r m3 ds (r r ds3 ds //r in ) M 4 in M 3 out M M App Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
25 ncrease o Using Widlar Current Mirror (Cont.) Large area ratio caused by large current ratio is reduced BE ln( t in C BE ) C C in out Q + Q out terative method to obtain the value of C r out =r o (+g m ) (For CMOS implementation, Q and Q are NMOS) App Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
26 BiCMOS Cascode Current Mirrors BiCMOS Q M o =r o (same as bipolar cascode) M o =g m r o r o =0M Q o > BE + CE(sat) (BJT) o > gs + DS(sat) (MOSFET) o > gs + CE(sat) (BiCMOS) o(bicmos) o(bjt) > o(cmos) App Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
27 BiCMOS Double Cascode Current Mirrors BJT For =00, A =50, o =00A, r o =50M o = r o3 No improvement from cascode Q 3 Q o > BE + CE(sat) = min Q MOSFET For(W/L) =5, n C ox =40A/, =0. -, g m r o =M o =(g m3 r o3 )(g m r o )r o With same parameter as before o =40M o > GS + DS(sat) = min M 3 M M App Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
28 BiCMOS Double Cascode Current Mirrors (Cont.) BiCMOS o =(g m3 r o3 )r o =000M Pratical limit : stray conductance o > BE + DS(sat) = min Q M 3 Q The highest o can be realized by using BiCMOS or CMOS. However, o(bicmos) > o(cmos) & min(bicmos) < min(cmos). (n general, gs > BE ) BiCMOS provides larger voltage swing. App Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
29 Stability of Constant gm Bias (W/L) P ref bat M M :k bias_l K*(W/L) P ref SG g ref m SG μ p C μ OX p ref W L C OX P W L P ref K or 0 (W/L) N M 4 M 3 (W/L) N g m g m K DC loop gain, A 0 bat :k M M o M 4 M 3 A 0 gm gm 4 4 gm gm gm gm K K gm gm K K gm gm 3 3 positive feedback i stable at DC App Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
30 Stability of Constant gm Bias (Cont.) AC voltage loop gain z M DD : k M o C p o i gm gm 4 Loop gain gm gm o i 3 sc sc / g sc / g ( sc g ) m3 p p 3 P m P p Large C p Small C p m n C b M 4 M 3 C A 0 i With large C p positive feedback loop and loop gain > Unstable Pole-zero pair induced by C p and Solution: Add an on-chip capacitor at node n b, such that ω P ω Z Furthermore, C PS App z p p p 3 f p ' z ' ω Z is always less than ω P : P Z gm k ω P ω P and ω P ω P3 loop gain > the bias circuit unstable P Z g C m3 C p C g m3 C p nc C p oxn oxp Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08 (W (W L) L) M3 M C p Stability compensation criteria
31 Example: Stability Compensation of Constant gm Bias Constant gm bias circuit T-like 0.8μm process Parameter g m 53.5μS 0kΩ g m 96.3μS C p 3pF g m3,4 88μS C 46fF bias 7.μA C 35fF DD : k M M C p n C b M 4 M 3 C : Stability of bias circuit P g C m 7.76MHz, ω P < ω P and ω P < ω P3 unstable Stability compensation P P g C m MHz, P3 g C m 63.MHz Add an on-chip capacitor at node n b such that ω P < ω Z C g C. 76C 5 8pF m3 p p. App4-4-3 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
Advanced Operational Amplifiers
IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage
More informationSample and Hold (S/H)
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8- 郭泰豪, Analog C Design, 07 Sample and Hold (S/H) Sample and Hold (often referred to as Track and hold (T/H)) dentical in both function & circuit implementation
More informationBuilding Blocks of Integrated-Circuit Amplifiers
Building Blocks of ntegrated-circuit Amplifiers 1 The Basic Gain Cell CS and CE Amplifiers with Current Source Loads Current-source- or active-loaded CS amplifier Rin A o R A o g r r o g r 0 m o m o Current-source-
More informationOperational Amplifier (OPAMP)
Operational Amplifier (OPAMP) Analog Cs nclude Operational Amplifier Filters Analog-to-Digital Converter (ADC) Digital-to-Analog Converter (DAC) Analog Modulator Phase-Locked Loop Analog Multiplier Others
More informationEE 140 / EE 240A ANALOG INTEGRATED CIRCUITS FALL 2015 C. Nguyen PROBLEM SET #7
Issued: Friday, Oct. 16, 2015 PROBLEM SET #7 Due (at 8 a.m.): Monday, Oct. 26, 2015, in the EE 140/240A HW box near 125 Cory. 1. A design error has resulted in a mismatch in the circuit of Fig. PS7-1.
More informationECE315 / ECE515 Lecture 7 Date:
Lecture 7 ate: 01.09.2016 CG Amplifier Examples Biasing in MOS Amplifier Circuits Common Gate (CG) Amplifier CG Amplifier- nput is applied at the Source and the output is sensed at the rain. The Gate terminal
More informationSolid State Devices & Circuits. 18. Advanced Techniques
ECE 442 Solid State Devices & Circuits 18. Advanced Techniques Jose E. Schutt-Aine Electrical l&c Computer Engineering i University of Illinois jschutt@emlab.uiuc.edu 1 Darlington Configuration - Popular
More informationChapter 7 Building Blocks of Integrated Circuit Amplifiers: Part D: Advanced Current Mirrors
1 Chapter 7 Building Blocks of Integrated Circuit Amplifiers: Part D: Advanced Current Mirrors Current Mirror Example 2 Two Stage Op Amp (MOSFET) Current Mirror Example Three Stage 741 Opamp (BJT) 3 4
More informationAnalysis and Design of Analog Integrated Circuits Lecture 8. Cascode Techniques
Analysis and Design of Analog Integrated Circuits Lecture 8 Cascode Techniques Michael H. Perrott February 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Review of Large Signal Analysis
More informationMultistage Amplifiers
Multistage Amplifiers Single-stage transistor amplifiers are inadequate for meeting most design requirements for any of the four amplifier types (voltage, current, transconductance, and transresistance.)
More informationDesign and Simulation of Low Voltage Operational Amplifier
Design and Simulation of Low Voltage Operational Amplifier Zach Nelson Department of Electrical Engineering, University of Nevada, Las Vegas 4505 S Maryland Pkwy, Las Vegas, NV 89154 United States of America
More informationLecture 4: Voltage References
EE6378 Power Management Circuits Lecture 4: oltage References Instructor: t Prof. Hoi Lee Mixed-Signal & Power IC Laboratory Department of Electrical Engineering The University of Texas at Dallas Introduction
More informationCMOS Cascode Transconductance Amplifier
CMOS Cascode Transconductance Amplifier Basic topology. 5 V I SUP v s V G2 M 2 iout C L v OUT Device Data V Tn = 1 V V Tp = 1 V µ n C ox = 50 µa/v 2 µ p C ox = 25 µa/v 2 λ n = 0.05 V 1 λ p = 0.02 V 1 @
More informationLecture 030 ECE4430 Review III (1/9/04) Page 030-1
Lecture 030 ECE4430 Review III (1/9/04) Page 0301 LECTURE 030 ECE 4430 REVIEW III (READING: GHLM Chaps. 3 and 4) Objective The objective of this presentation is: 1.) Identify the prerequisite material
More informationAnalog Integrated Circuit Design Exercise 1
Analog Integrated Circuit Design Exercise 1 Integrated Electronic Systems Lab Prof. Dr.-Ing. Klaus Hofmann M.Sc. Katrin Hirmer, M.Sc. Sreekesh Lakshminarayanan Status: 21.10.2015 Pre-Assignments The lecture
More informationCurrent Mirrors. Basic BJT Current Mirror. Current mirrors are basic building blocks of analog design. Figure shows the basic NPN current mirror.
Current Mirrors Basic BJT Current Mirror Current mirrors are basic building blocks of analog design. Figure shows the basic NPN current mirror. For its analysis, we assume identical transistors and neglect
More informationEECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design
EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design References: Analog Integrated Circuit Design by D. Johns and K. Martin and Design of Analog CMOS Integrated Circuits by B. Razavi All figures
More informationSKEL 4283 Analog CMOS IC Design Current Mirrors
SKEL 4283 Analog CMOS IC Design Current Mirrors Dr. Nasir Shaikh Husin Faculty of Electrical Engineering Universiti Teknologi Malaysia Current Mirrors 1 Objectives Introduce and characterize the current
More informationEECS3611 Analog Integrated Circuit Design. Lecture 3. Current Source and Current Mirror
EECS3611 Analog ntegrated Circuit Design Lecture 3 Current Source and Current Mirror ntroduction Before any device can be used in any application, it has to be properly biased so that small signal AC parameters
More informationES 330 Electronics II Homework # 6 Soltuions (Fall 2016 Due Wednesday, October 26, 2016)
Page1 Name Solutions ES 330 Electronics Homework # 6 Soltuions (Fall 016 ue Wednesday, October 6, 016) Problem 1 (18 points) You are given a common-emitter BJT and a common-source MOSFET (n-channel). Fill
More informationBJT Amplifier. Superposition principle (linear amplifier)
BJT Amplifier Two types analysis DC analysis Applied DC voltage source AC analysis Time varying signal source Superposition principle (linear amplifier) The response of a linear amplifier circuit excited
More informationLecture 34: Designing amplifiers, biasing, frequency response. Context
Lecture 34: Designing amplifiers, biasing, frequency response Prof J. S. Smith Context We will figure out more of the design parameters for the amplifier we looked at in the last lecture, and then we will
More informationChapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier
Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in double-ended
More informationPreliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B
Preliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B Problem 1. Consider the following circuit, where a saw-tooth voltage is applied
More informationCOMPARISON OF THE MOSFET AND THE BJT:
COMPARISON OF THE MOSFET AND THE BJT: In this section we present a comparison of the characteristics of the two major electronic devices: the MOSFET and the BJT. To facilitate this comparison, typical
More information4.5 Biasing in MOS Amplifier Circuits
4.5 Biasing in MOS Amplifier Circuits Biasing: establishing an appropriate DC operating point for the MOSFET - A fundamental step in the design of a MOSFET amplifier circuit An appropriate DC operating
More informationLecture 240 Cascode Op Amps (3/28/10) Page 240-1
Lecture 240 Cascode Op Amps (3/28/10) Page 2401 LECTURE 240 CASCODE OP AMPS LECTURE ORGANIZATION Outline Lecture Organization Single Stage Cascode Op Amps Two Stage Cascode Op Amps Summary CMOS Analog
More informationAmplifiers Frequency Response Examples
ECE 5/45 Analog IC Design We will use the following MOSFET parameters for hand-calculations and the µm CMOS models for corresponding simulations. Table : Long-channel MOSFET parameters. Parameter NMOS
More informationINF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation
INF3410 Fall 2013 Compensation content Introduction Two Stage Opamps Compensation Slew Rate Systematic Offset Advanced Current Mirrors Operational Transconductance Amplifiers Current Mirror Opamps Folded
More informationChapter 4. CMOS Cascode Amplifiers. 4.1 Introduction. 4.2 CMOS Cascode Amplifiers
Chapter 4 CMOS Cascode Amplifiers 4.1 Introduction A single stage CMOS amplifier cannot give desired dc voltage gain, output resistance and transconductance. The voltage gain can be made to attain higher
More information55:041 Electronic Circuits
55:041 Electronic Circuits Mosfet Review Sections of Chapter 3 &4 A. Kruger Mosfet Review, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width 1 10-6 m or less Thickness 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor
More informationEE105 Fall 2015 Microelectronic Devices and Circuits
EE105 Fall 2015 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 11-1 Transistor Operating Mode in Amplifiers Transistors are biased in flat part of
More informationTWO AND ONE STAGES OTA
TWO AND ONE STAGES OTA F. Maloberti Department of Electronics Integrated Microsystem Group University of Pavia, 7100 Pavia, Italy franco@ele.unipv.it tel. +39-38-50505; fax. +39-038-505677 474 EE Department
More informationChapter 11. Differential Amplifier Circuits
Chapter 11 Differential Amplifier Circuits 11.0 ntroduction Differential amplifier or diff-amp is a multi-transistor amplifier. t is the fundamental building block of analog circuit. t is virtually formed
More informationChapter 12 Opertational Amplifier Circuits
1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded cascode circuit.
More information1. The fundamental current mirror with MOS transistors
1. The fundamental current mirror with MOS transistors The test schematic (ogl-simpla-mos.asc): 1. Size the transistors in the mirror for a current gain equal to unity, a 30μA input current and V DSat
More informationBasic Circuits. Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair,
Basic Circuits Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair, CCS - Basic Circuits P. Fischer, ZITI, Uni Heidelberg, Seite 1 Reminder: Effect of Transistor Sizes Very crude classification:
More informationINF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation
INF3410 Fall 2015 Book Chapter 6: Basic Opamp Design and Compensation content Introduction Two Stage Opamps Compensation Slew Rate Systematic Offset Advanced Current Mirrors Operational Transconductance
More informationLecture 14. FET Current and Voltage Sources and Current Mirrors. The Building Blocks of Analog Circuits - IV
Lecture 4 FET Current and oltage s and Current Mirrors The Building Blocks of Analog Circuits n this lecture you will learn: Current and voltage sources using FETs FET current mirrors Cascode current mirror
More informationECE 3110: Engineering Electronics II Fall Final Exam. Dec. 16, 8:00-10:00am. Name: (78 points total)
Final Exam Dec. 16, 8:00-10:00am Name: (78 points total) Problem 1: Consider the emitter follower in Fig. 7, which is being used as an output stage. For Q 1, assume β = and initally assume that V BE =
More information55:041 Electronic Circuits
55:041 Electronic Circuits MOSFETs Sections of Chapter 3 &4 A. Kruger MOSFETs, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width = 1 10-6 m or less Thickness = 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor
More informationLecture 300 Low Voltage Op Amps (3/28/10) Page 300-1
Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1 LECTURE 300 LOW VOLTAGE OP AMPS LECTURE ORGANIZATION Outline Introduction Low voltage input stages Low voltage gain stages Low voltage bias circuits
More informationBuilding Blocks of Integrated-Circuit Amplifiers
CHAPTER 7 Building Blocks of Integrated-Circuit Amplifiers Introduction 7. 493 IC Design Philosophy 7. The Basic Gain Cell 494 495 7.3 The Cascode Amplifier 506 7.4 IC Biasing Current Sources, Current
More informationClass-AB Low-Voltage CMOS Unity-Gain Buffers
Class-AB Low-Voltage CMOS Unity-Gain Buffers Mariano Jimenez, Antonio Torralba, Ramón G. Carvajal and J. Ramírez-Angulo Abstract Class-AB circuits, which are able to deal with currents several orders of
More informationIndex. Small-Signal Models, 14 saturation current, 3, 5 Transistor Cutoff Frequency, 18 transconductance, 16, 22 transit time, 10
Index A absolute value, 308 additional pole, 271 analog multiplier, 190 B BiCMOS,107 Bode plot, 266 base-emitter voltage, 16, 50 base-emitter voltages, 296 bias current, 111, 124, 133, 137, 166, 185 bipolar
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
OTA-output buffer 1 According to the types of loads, the driving capability of the output stages differs. For switched capacitor circuits which have high impedance capacitive loads, class A output stage
More informationMetal-Oxide-Silicon (MOS) devices PMOS. n-type
Metal-Oxide-Silicon (MOS devices Principle of MOS Field Effect Transistor transistor operation Metal (poly gate on oxide between source and drain Source and drain implants of opposite type to substrate.
More informationQUESTION BANK for Analog Electronics 4EC111 *
OpenStax-CNX module: m54983 1 QUESTION BANK for Analog Electronics 4EC111 * Bijay_Kumar Sharma This work is produced by OpenStax-CNX and licensed under the Creative Commons Attribution License 4.0 Abstract
More informationLaboratory #9 MOSFET Biasing and Current Mirror
Laboratory #9 MOSFET Biasing and Current Mirror. Objectives 1. Review the MOSFET characteristics and transfer function. 2. Understand the relationship between the bias, the input signal and the output
More informationMicroelectronics Part 2: Basic analog CMOS circuits
GBM830 Dispositifs Médicaux Intelligents Microelectronics Part : Basic analog CMOS circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim!! http://www.cours.polymtl.ca/gbm830/! mohamad.sawan@polymtl.ca!
More information6.012 Microelectronic Devices and Circuits
Page 1 of 13 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Microelectronic Devices and Circuits Final Eam Closed Book: Formula sheet provided;
More informationMicroelectronic Circuits II. Ch 10 : Operational-Amplifier Circuits
Microelectronic Circuits II Ch 0 : Operational-Amplifier Circuits 0. The Two-stage CMOS Op Amp 0.2 The Folded-Cascode CMOS Op Amp CNU EE 0.- Operational-Amplifier Introduction - Analog ICs : operational
More informationECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers
ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic
More informationImproving Amplifier Voltage Gain
15.1 Multistage ac-coupled Amplifiers 1077 TABLE 15.3 Three-Stage Amplifier Summary HAND ANALYSIS SPICE RESULTS Voltage gain 998 1010 Input signal range 92.7 V Input resistance 1 M 1M Output resistance
More informationLecture 16: MOS Transistor models: Linear models, SPICE models. Context. In the last lecture, we discussed the MOS transistor, and
Lecture 16: MOS Transistor models: Linear models, SPICE models Context In the last lecture, we discussed the MOS transistor, and added a correction due to the changing depletion region, called the body
More informationExperiment #7 MOSFET Dynamic Circuits II
Experiment #7 MOSFET Dynamic Circuits II Jonathan Roderick Introduction The previous experiment introduced the canonic cells for MOSFETs. The small signal model was presented and was used to discuss the
More informationOrister Corporation. LDO Thesis
Orister Corporation LDO Thesis AGENDA What is a Linear egulator LDO ntroductions LDO S Terms and Definitions LDO S LAYOUT What s a Linear egulator A linear regulator operates by using a voltage-controlled
More informationVoltage Biasing Considerations (From the CS atom toward the differential pair atom) Claudio Talarico, Gonzaga University
Voltage Biasing Considerations (From the CS atom toward the differential pair atom) Claudio Talarico, Gonzaga University Voltage Biasing Considerations In addition to bias currents, building a complete
More informationSAMPLE FINAL EXAMINATION FALL TERM
ENGINEERING SCIENCES 154 ELECTRONIC DEVICES AND CIRCUITS SAMPLE FINAL EXAMINATION FALL TERM 2001-2002 NAME Some Possible Solutions a. Please answer all of the questions in the spaces provided. If you need
More informationUnit 3: Integrated-circuit amplifiers (contd.)
Unit 3: Integrated-circuit amplifiers (contd.) COMMON-SOURCE AND COMMON-EMITTER AMPLIFIERS The Common-Source Circuit The most basic IC MOS amplifier is shown in fig.(1). The source of MOS transistor is
More informationUNIT I BIASING OF DISCRETE BJT AND MOSFET PART A
UNIT I BIASING OF DISCRETE BJT AND MOSFET PART A 1. Why do we choose Q point at the center of the load line? 2. Name the two techniques used in the stability of the q point.explain. 3. Give the expression
More informationHomework Assignment 12
Homework Assignment 12 Question 1 Shown the is Bode plot of the magnitude of the gain transfer function of a constant GBP amplifier. By how much will the amplifier delay a sine wave with the following
More informationECEN 5008: Analog IC Design. Final Exam
ECEN 5008 Initials: 1/10 ECEN 5008: Analog IC Design Final Exam Spring 2004 Instructions: 1. Exam Policy: Time-limited, 150-minute exam. When the time is called, all work must stop. Put your initials on
More informationF7 Transistor Amplifiers
Lars Ohlsson 2018-09-25 F7 Transistor Amplifiers Outline Transfer characteristics Small signal operation and models Basic configurations Common source (CS) CS/CE w/ source/ emitter degeneration resistance
More informationLaboratory #5 BJT Basics and MOSFET Basics
Laboratory #5 BJT Basics and MOSFET Basics I. Objectives 1. Understand the physical structure of BJTs and MOSFETs. 2. Learn to measure I-V characteristics of BJTs and MOSFETs. II. Components and Instruments
More informationMicroelectronics Exercises of Topic 5 ICT Systems Engineering EPSEM - UPC
Microelectronics Exercises of Topic 5 ICT Systems Engineering EPSEM - UPC F. Xavier Moncunill Autumn 2018 5 Analog integrated circuits Exercise 5.1 This problem aims to follow the steps in the design of
More informationHomework Assignment 07
Homework Assignment 07 Question 1 (Short Takes). 2 points each unless otherwise noted. 1. A single-pole op-amp has an open-loop low-frequency gain of A = 10 5 and an open loop, 3-dB frequency of 4 Hz.
More informationA Compact Folded-cascode Operational Amplifier with Class-AB Output Stage
A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage EEE 523 Advanced Analog Integrated Circuits Project Report Fuding Ge You are an engineer who is assigned the project to design
More informationWhat is the typical voltage gain of the basic two stage CMOS opamp we studied? (i) 20dB (ii) 40dB (iii) 80dB (iv) 100dB
Department of Electronic ELEC 5808 (ELG 6388) Signal Processing Electronics Final Examination Dec 14th, 2010 5:30PM - 7:30PM R. Mason answer all questions one 8.5 x 11 crib sheets allowed 1. (5 points)
More informationChapter 4 Single-stage MOS amplifiers
Chapter 4 Single-stage MOS amplifiers ELEC-H402/CH4: Single-stage MOS amplifiers 1 Single-stage MOS amplifiers NMOS as an amplifier: example of common-source circuit NMOS amplifier example Introduction
More informationECE 442 Solid State Devices & Circuits. 15. Differential Amplifiers
ECE 442 Solid State Devices & Circuits 15. Differential Amplifiers Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 442 Jose Schutt Aine 1 Background
More informationIntegrated Circuit Amplifiers. Comparison of MOSFETs and BJTs
Integrated Circuit Amplifiers Comparison of MOSFETs and BJTs 17 Typical CMOS Device Parameters 0.8 µm 0.25 µm 0.13 µm Parameter NMOS PMOS NMOS PMOS NMOS PMOS t ox (nm) 15 15 6 6 2.7 2.7 C ox (ff/µm 2 )
More informationMICROELECTRONIC CIRCUIT DESIGN Third Edition
MICROELECTRONIC CIRCUIT DESIGN Third Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 1/25/08 Chapter 1 1.3 1.52 years, 5.06 years 1.5 1.95 years, 6.46 years 1.8 113
More informationDigital Electronics. Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region. Positive Logic.
Digital Electronics Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region Positive Logic Logic 1 Negative Logic Logic 0 Voltage Transition Region Transition
More informationCMOS Analog Circuits
CMOS Analog Circuits L8B: Common Source Amplifier with Actie Load- (9.8.3) B. Mazhari Dept. of EE, IIT Kanpur Problems with current design -.586 in 65k 50/ O -3.3 DD = 3.3 DD f 3dB. Although sufficient
More informationChapter 10 Feedback ECE 3120 Microelectronics II Dr. Suketu Naik
1 Chapter 10 Feedback Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: Active-Loaded Differential Pair 4. Ch 10: Feedback 5. Ch 11: Output
More informationDesign of Miller Compensated Two-Stage Operational Amplifier for Data Converter Applications
Design of Miller Compensated Two-Stage Operational Amplifier for Data Converter Applications Prema Kumar. G Shravan Kudikala Casest, School Of Physics Casest, School Of Physics University Of Hyderabad
More informationLECTURE 19 DIFFERENTIAL AMPLIFIER
Lecture 19 Differential Amplifier (6/4/14) Page 191 LECTURE 19 DIFFERENTIAL AMPLIFIER LECTURE ORGANIZATION Outline Characterization of a differential amplifier Differential amplifier with a current mirror
More informationEE105 Fall 2015 Microelectronic Devices and Circuits
EE105 Fall 2015 Microelectronic Devices and Circuits Multi-Stage Amplifiers Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of MOS Amplifiers Common
More informationReading. Lecture 33: Context. Lecture Outline. Chapter 9, multi-stage amplifiers. Prof. J. S. Smith
eading Lecture 33: Chapter 9, multi-stage amplifiers Prof J. S. Smith Context Lecture Outline We are continuing to review some of the building blocks for multi-stage amplifiers, including current sources
More informationFull Paper ACEEE Int. J. on Control System and Instrumentation, Vol. 4, No. 2, June 2013
ACEEE Int J on Control System and Instrumentation, Vol 4, No 2, June 2013 Analys and Design of CMOS Source Followers and Super Source Follower Mr D K Shedge 1, Mr D A Itole 2, Mr M P Gajare 3, and Dr P
More informationWeek 7: Common-Collector Amplifier, MOS Field Effect Transistor
EE 2110A Electronic Circuits Week 7: Common-Collector Amplifier, MOS Field Effect Transistor ecture 07-1 Topics to coer Common-Collector Amplifier MOS Field Effect Transistor Physical Operation and I-V
More informationECE315 / ECE515 Lecture 9 Date:
Lecture 9 Date: 03.09.2015 Biasing in MOS Amplifier Circuits Biasing using Single Power Supply The general form of a single-supply MOSFET amplifier biasing circuit is: We typically attempt to satisfy three
More informationLecture #3: Voltage Regulator
Lecture #3: Voltage Regulator UNVERSTY OF CALFORNA, SAN DEGO Voltage regulator is a constant voltage source with a high current capacity to drive a low impedance load. A full-wave rectifier followed by
More informationECE315 / ECE515 Lecture 8 Date:
ECE35 / ECE55 Lecture 8 Date: 05.09.06 CS Amplifier with Constant Current Source Current Steering Circuits CS Stage Followed by CG Stage Cascode as Current Source Cascode as Amplifier ECE35 / ECE55 CS
More informationINF3410 Fall Book Chapter 3: Basic Current Mirrors and Single-Stage Amplifiers
INF3410 Fall 2013 Amplifiers content Simple Current Mirror Common-Source Amplifier Interrupt: A word on output resistance Common-Drain Amplifier with active load / Source Follower Common-Gate Amplifier
More informationINTRODUCTION TO ELECTRONICS EHB 222E
INTRODUCTION TO ELECTRONICS EHB 222E MOS Field Effect Transistors (MOSFETS II) MOSFETS 1/ INTRODUCTION TO ELECTRONICS 1 MOSFETS Amplifiers Cut off when v GS < V t v DS decreases starting point A, once
More informationLecture 20 Transistor Amplifiers (II) Other Amplifier Stages
Lecture 20 Transistor Amplifiers (II) Other Amplifier Stages Outline Common drain amplifier Common gate amplifier Reading Assignment: Howe and Sodini; Chapter 8, Sections 8.78.9 6.02 Spring 2009 . Common
More informationThe Miller Approximation. CE Frequency Response. The exact analysis is worked out on pp of H&S.
CE Frequency Response The exact analysis is worked out on pp. 639-64 of H&S. The Miller Approximation Therefore, we consider the effect of C µ on the input node only V ---------- out V s = r g π m ------------------
More informationAnalog Integrated Circuit Configurations
Analog Integrated Circuit Configurations Basic stages: differential pairs, current biasing, mirrors, etc. Approximate analysis for initial design MOSFET and Bipolar circuits Basic Current Bias Sources
More informationOperational Amplifiers
CHAPTER 9 Operational Amplifiers Analog IC Analysis and Design 9- Chih-Cheng Hsieh Outline. General Consideration. One-Stage Op Amps / Two-Stage Op Amps 3. Gain Boosting 4. Common-Mode Feedback 5. Input
More informationDesign of High-Speed Op-Amps for Signal Processing
Design of High-Speed Op-Amps for Signal Processing R. Jacob (Jake) Baker, PhD, PE Professor and Chair Boise State University 1910 University Dr. Boise, ID 83725-2075 jbaker@ieee.org Abstract - As CMOS
More informationSystem on a Chip. Prof. Dr. Michael Kraft
System on a Chip Prof. Dr. Michael Kraft Lecture 4: Filters Filters General Theory Continuous Time Filters Background Filters are used to separate signals in the frequency domain, e.g. remove noise, tune
More informationECE 546 Lecture 12 Integrated Circuits
ECE 546 Lecture 12 Integrated Circuits Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine 1 Integrated Circuits IC Requirements
More informationD n ox GS THN DS GS THN DS GS THN. D n ox GS THN DS GS THN DS GS THN
Name: EXAM #3 Closed book, closed notes. Calculators may be used for numeric computations only. All work is to be your own - show your work for maximum partial credit. Data: Use the following data in all
More informationLow Dropout Voltage Regulator Operation and Performance Review
Low Drop Voltage Regulator peration and Performance Review Eric Chen & Alex Leng ntroduction n today s power management systems, high power efficiency becomes necessary to maximize the lifetime of the
More informationMOS Field Effect Transistors
MOS Field Effect Transistors A gate contact gate interconnect n polysilicon gate source contacts W active area (thin oxide area) polysilicon gate contact metal interconnect drain contacts A bulk contact
More informationF9 Differential and Multistage Amplifiers
Lars Ohlsson 018-10-0 F9 Differential and Multistage Amplifiers Outline MOS differential pair Common mode signal operation Differential mode signal operation Large signal operation Small signal operation
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
Low power OTA 1 Two-Stage, Miller Op Amp Operating in Weak Inversion Low frequency response: gm1 gm6 Av 0 g g g g A v 0 ds2 ds4 ds6 ds7 I D m, ds D nvt g g I n GB and SR: GB 1 1 n 1 2 4 6 6 7 g 2 2 m1
More informationYou will be asked to make the following statement and provide your signature on the top of your solutions.
1 EE 435 Name Exam 1 Spring 216 Instructions: The points allocated to each problem are as indicated. Note that the first and last problem are weighted more heavily than the rest of the problems. On those
More information