Designing CMOS folded-cascode operational amplifier with flicker noise minimisation

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1 Microelectronics Journal 32 (200) Short Communication Designing CMOS folded-cascode operational amplifier with flicker noise minimisation P.K. Chan*, L.S. Ng, L. Siek, K.T. Lau Microelectronics Journal School of Electrical and Electronic Engineering, Block S, Nanyang Technological University, Nanyang Avenue, Singapore, Singapore Received 8 November 999; revised 26 April 2000; accepted 27 April 2000 Abstract The strategy for minimising the flicker noise in the folded-cascode amplifier topology is presented and the inter-relationship of design parameters for optimum design is described. The HSPICE simulation results correlate very well with the theory and validate the design methodology. The proposed solution offers good tradeoff on the conflicting performance parameters such as noise, silicon area, bandwidth and power consumption. It will be useful for the analytic model in CAD design optimisation and allows fast computation or first-order hand analysis on noise evaluation Elsevier Science Ltd. All rights reserved. Keywords: Noise optimisation; CMOS operational amplifier. Introduction In CMOS operational amplifiers, the low frequency noise is usually dominated by flicker noise. The origin of flicker noise is due to extra energy states existent at the boundary between SiO 2 and Si. These can trap and release electrons from the channel of MOS device. Due to the slow process, the flicker noise component is significant high in value at low frequencies. The flicker noise is inversely proportional to the gate area. In addition, PMOS devices are quieter than NMOS counterparts. As a consequence, low noise design practice adopts large size p-channel input transistors with high transconductance whenever possible. This is also in conjunction with long-channel transistors with small transconductance as active load [2,3]. However, excessive size of p-channel input transistors and active loads increase the silicon area as well as the parasitic capacitances substantially. Hence, more power consumption is needed to move the parasitic poles to higher frequency. For efficient circuit design, the approach to minimise noise, particularly the flicker noise, becomes an important design strategy in the CMOS operational amplifiers. Previous research work [] had demonstrated noise optimisation of the single differential stage operational amplifier. In this paper, the foldedcascode structure is analysed because it is being used in a wide range of analogue sample-data circuit applications such as fast-settling amplifier, interface circuit, switchedcapacitor filter, ADC, DAC and so forth. Furthermore, there is no such optimisation equation in the well-known analogue CAD tools [4,5] or literature. The motivation of this paper is to derive the new closed-form noise optimisation equation for generic folded-cascode amplifier topology and compare the results with those of the two-stage operational amplifier as a reference basis. 2. /f noise optimisation The noise sources of the CMOS operational amplifier originate from flicker noise and thermal noise components. The flicker noise component is usually larger than the thermal noise component for frequencies below 0 khz for typical bias conditions and device geometries. The total noise current of a MOSFET from the Gray and Meyer noise model [2] is given as i 2 t ˆ KFg 2 m 8KTg m 3 Neglecting the thermal noise contribution, the total noise current can be approximated as * Corresponding author. Fax: address: epkchan@ntu.edu.sg (P.K. Chan). i 2 t K Fg 2 m /00/$ - see front matter 2000 Elsevier Science Ltd. All rights reserved. PII: S (00)0005-

2 70 P.K. Chan et al. / Microelectronics Journal 32 (200) Substituting Eqs. (2) (4) into Eq. (5), we have v 2 eq2s 2K " F K! F3m n L # C OX W f L K F m p 6 with Fig.. Two-stage opamp. where the symbols have their usual meanings, and the subscript n represents n-channel device, and subscript p represents p-channel device. It is apparent from Eq. (6) that there exists a minimum as L varies. For very low values of L, the first term is dominant, whereas for large L values, the second term is dominant. Although the low-noise design practice adapts long channel length L 3 for active load and short channel length L for good phase margin, it should be noticed that the condition of excessive channel length in L 3 and too-short channel length in L does not lead to the necessary minimum noise criteria. Thus, by differentiating Eq. (6) with respect to L and setting the derivative to zero, the value of L yielding minimum input-referred voltage [] is g 2 W m ˆ 2mC OX L I D 3 where K F is the flicker noise coefficient, g m the transconductance parameter of the MOSFET device, C OX the gate oxide capacitance per unit area, W the channel width, L the channel length, f the frequency, m the effective mobility, I D the drain current and the bandwidth. Thus, the equivalent input-referred voltage noise can be written as v 2 eq K F Noise analysis of the two-stage operational amplifier [2] of Fig. yields v 2 eq2s " # 2 v 2 n g 2 m3 v2 n3 g m Fig. 2. Folded-cascode opamp. 4 5 L ;2Sopt ˆ L 3 s K F3 m n K F m p It can be shown from the above analysis, that the low frequency noise contribution is similar to that of the single stage differential amplifier. Following similar mathematical treatment [3] for the high-swing folded-cascode operational amplifier as depicted in Fig. 2, we can obtain 2K F C OX W f " L I! # D8 L I D L 2 8 K F3m n K F m p!! ID3 L I D K F8 K F The extra noise term due to M8 is generated as compared with the Eq. (6). The total noise for the folded cascode amplifier can be optimised via controlling the biasing current ratios. Although the equation illustrates the noise performance with respective design parameters, it does not indicate the optimal design strategies because there are many choices in the design. Using the goal of minimum noise as the lower bound, the new noise optimisation equation is obtained by differentiating Eq. (8). This is given as L ;FCopt ˆ v! K F3 m n ID3 K u t F8 ID8 K F m p I D K F I D Thus, the solution of L depends on the process parameters as well as other design parameters. These design parameters are the transistor lengths of M3 and M8 and the biasing current ratios I D3 /I D and I D8 /I D. Noise minimisation strategy leads to long channel lengths and low biasing currents for M3 and M8 as far as meeting other performance L 2 8 7! (8) 9

3 P.K. Chan et al. / Microelectronics Journal 32 (200) Table Range of K F values for NMOS model Width length mm mm mm 0 mm m 0.8 mm mm mm mm mm mm m Table 2 Range of K F values for PMOS model Width length mm mm mm 0 mm m 0.8 mm mm mm mm mm mm m objectives such as slew-rate, input common-mode voltage range and gain bandwidth at a specified phase margin. In general design practice of folded-cascode amplifier, the biasing currents are often chosen such that I D ˆ I D8 ; I D3 ˆ 2I D8 : For K F ˆ K F8 ; Eq. (8) can be simplified to 2K F C OX W f " K! # F3m n 2L L K F m p L L As can be seen from Eq. (0), L 8 is made larger than L and the second term is much greater than the third term in the bracket. Thus, Eq. (0) can be approximated as 2K " F K! # F3m n 2L C OX W f L K F m p By differentiating Eq. () with respect to L and setting the derivative to zero, we get p L ;FCopt ˆ L 2 s 3 2 K F3 m n K F m p It is interesting to note thatpthe optimum value of L in folded-cascode amplifier is 2 times larger than that in Eq. (7) for the two-stage amplifier. 3. Results and discussions The low noise design methodology was verified by simulations using the realistic Level 28 HSPICE models, together with the measured flicker noise coefficients in unit of V 2 F for different sizes of MOS transistors in Tables and 2 which ensure good accuracy in noise prediction. The process parameters are given as C OX ˆ 9:7 0 6 F=mm 2 m p C OX ˆ 30 gma=v 2 ; m n C OX ˆ 90 ma=v 2 and m n =m p 3: For a given channel length of active load, the optimum length for low noise design can be obtained. Using the relevant flicker noise coefficients from Tables and 2 in association with the process parameters and Eq. (6), the flicker noise level can be computed. Fig. 3 compares the theoretical and simulated noise curves at different channel lengths of input transistor pair in the two-stage operational amplifier design using a 0.8 mm CMOS technology in a single 5 V supply. As can be seen from the figure, the flicker noise Fig. 3. Noise plot of two-stage opamp. Fig. 4. Noise plot of folded-cascode opamp.

4 72 P.K. Chan et al. / Microelectronics Journal 32 (200) Table 3 Performance of the optimised two-stage operational amplifier Performance parameters UGB DC Gain 30 pf load khz Input CMR Output CMR CMRR PSRR Total supply current (core amplifier) Power consumption Two-stage amplifier 5.50 MHz 77.0 db 54.0 degree p nv= Hz V V 88 db 07 db.8 ma 5.9 mw Table 4 Aspect ratio for folded-cascode amplifier with or without equation aided design Transistor Aspect ratio Aspect ratio (with equation aided) M, M2 560/ /3. M3, M4 75/20 7/20 M5, M6 53.6/ /.6 M7, M0 25.6/ /.6 M8, M9 68/8 64/4 L 3 ˆ 20 mm; I D3 =I D ˆ :6; I D8 =I D ˆ 0:6: Table 4 compares the dimension of transistors of the foldedcascoded operational amplifier with or without using the optimisation equation in a 5 V design. The respective performance parameters are summarised in Table 5. Although the low noise result can be achieved using L ˆ 2 mm and L 3 ˆ 20 mm in the design without employing the design equation, it is not an optimum solution. On the other hand, the results of this work show that not only does the optimisation equation aid the designers to achieve low-noise amplifier design objective in a systematic manner, it can improve the existing designs by reducing the silicon area, parasitic capacitances and enhancing other performance parameters without sacrificing bandwidth/supply current ratio and low noise performance etc.. The substantial reduction in 30.5% area (M M4, M8 M9 and compensation capacitor Cc) from the optimised amplifier demonstrates the usefulness of the proposed optimisation Eq. (9). It is observed that the reasonable derivation of the minimum point on the channel length L from either two-stage or folded-cascode design would not cause any sharp increase in the noise level. This gives an important implication that L can be adjusted in a certain range to suit for other performance needs such as gain-bandwidth control, stability, other parameter optimisation and so forth. component varies in a quadratic-like behaviour as the channel length L increases from 2 to 5. mm. The existence of a minimum noise point is very close to the theoretical prediction of L ˆ 4:0 mm for L 3 ˆ 20 mm: The simulated inputreferred noise is slightly higher than the theoretical result. This is consistent because the optimisation ignores the contribution from the thermal noise component. Table 3 summaries the simulated performance of the optimised two-stage operational amplifier in a single 5 V design. The noise pattern is also confirmed in Fig. 4 for highswing folded-cascode amplifier design. It can be seen that the minimum noise point occurs when L ˆ 3: mm for 4. Conclusions The new closed-form flicker noise optimisation equation for the folded-cascode amplifier topology is proposed. Not only does it indicate the inter-relationships of the design parameters, it avoids excessive over-designs in the foldedcascode amplifier. Extensive Spice simulation results confirm the validity of the noise minimisation methodology. This equation will be useful for the equation-based optimisers for fast computation of design parameters in meeting performance objectives under design constraints. The established result from this work can be reused for large Table 5 Resuts of optimised and un-optimised folded-cascode amplifier Performance parameters Custom low noise amplifier After optimisation UGB 8.6 MHz 0 MHz DC gain 79.5 db 8 db 0 pf load 66.5 degree 7 degree Max output swing 2 Vpp 2 Vpp Supply current (core amplier) 350 ma 320 ma BW/I 24.6 khz/ma 3.3 khz/ma Power consumption.75 mw p.6 mw p khz 4 nv= Hz 34.8 nv= Hz I D3 /I D 75 ma/87.5 ma 60 ma/00 ma I D8 /I D 87.5 ma/87.5 ma 60mA/00 ma Compensation capacitor, Cc 5 pf 4 pf Area of Cc M M4 M8 M mm mm 2 Normalised area 0.695

5 P.K. Chan et al. / Microelectronics Journal 32 (200) groups of other cascode amplifier variants with minimum modifications. References [] J.C. Bertails, Low-frequency noise considerations for MOS amplifiers design, IEEE J. Solid-Stage Circuits vol. SC-4 (August) (979) [2] P.R. Gray, R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 2nd ed., Wiley, New York, 984, pp [3] K.R. Laker, W.M.C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, New York, 994, pp [4] G.R. Degrauwe, et al., IDAC: an interactive design tool for analog CMOS circuits, IEEE J. Solid-State Circuits 22 (6) (987) [5] G.E. Gielen, C.C. Walscharts, M.C. Sansen, Analog circuit design optimisation based on symbolic simulation and simulated annealing, IEEE J. Solid-State Circuits 25 (3) (990)