2. Single Stage OpAmps


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1 /74 2. Single Stage OpAmps Francesc Serra Graells Departament de Microelectrònica i Sistemes Electrònics Universitat Autònoma de Barcelona Integrated Circuits and Systems IMBCNM(CSIC)
2 2/74 The MonoTransistor Amplifier 2 Differential Topologies 3 Common Mode Feedback 4 Folded Amplifiers 5 Cascode Topologies 6 Gain Enhancement Techniques
3 3/74 The MonoTransistor Amplifier 2 Differential Topologies 3 Common Mode Feedback 4 Folded Amplifiers 5 Cascode Topologies 6 Gain Enhancement Techniques
4 4/74 SingleTransistor Topologies Operational voltage amplifier (OpAmp)? Currentdriven bias point to control circuit power Supposing forward saturation, drain is selected as output port due to its high impedance (CLM): Common source Common gate Back gate
5 5/74 SingleTransistor Topologies Operational voltage amplifier (OpAmp)? Currentdriven bias point to control circuit power Supposing forward saturation, drain is selected as output port due to its high impedance (CLM): Power efficiency Common source Common gate Back gate Moderate G m /I D Highest G m /I D Lowest G m /I D High input impedance Low input impedance Low input impedance Inverting amplifier Easier feedback Noninverting amplifier p+ n+ n+ Inverting amplifier Latchup Triplewell required
6 6/74 Voltage Transfer Curve Large signal analysis of common source amplifier: e.g. autobiasing operating in strong inversion and forward saturation: V B =0 unless specified CLM negligible in large signal in saturation in conduction
7 7/74 Gain and Frequency Response Common source small signal analysis: Incremental equivalent circuit: G D strong inversion and forward saturation bias point B S G D B S
8 8/74 Gain and Frequency Response Incremental equivalent circuit: DC voltage gain 3dB/oct 6dB/oct 3dB/oct In general, for CMOS amplifiers: strong inversion and forward saturation bias point input transconductance output resistance
9 9/74 Gain and Frequency Response Incremental equivalent circuit: Spectral bandwidth openloop closedloop 20dB/dec max. closedloop (i.e. follower) Frequency 0.5oct/oct strong inversion and forward saturation bias point 0.5oct/oct
10 0/74 Dynamic Range Noise equivalent circuit: Thermal noise contribution only (f > flicker corner): x0 (20dB) x (0dB) Time Uncorrelated phenomena and lowfrequency: Equivalent input noise:
11 /74 Dynamic Range Noise equivalent circuit: Thermal noise contribution only (f > flicker corner): x0 (20dB) x (0dB) Time Bandwidth Temperature Supply Power Dynamic Range.5dB/oct 3dB/oct
12 2/74 Full CMOS Circuit Similar performance analysis: Large signal VTC: in conduction in saturation All operating in strong inversion and forward saturation bias points: in saturation in conduction
13 3/74 Full CMOS Circuit Similar performance analysis: Small signal gain and bandwidth: 3dB/oct 6dB/oct 3dB/oct All operating in strong inversion and forward saturation bias points: 0.5oct/oct 0.5oct/oct
14 4/74 The MonoTransistor Amplifier 2 Differential Topologies 3 Common Mode Feedback 4 Folded Amplifiers 5 Cascode Topologies 6 Gain Enhancement Techniques
15 5/74 FullyDifferential vs SingleEnded Singleended OpAmps: Power rails resistive parasitics Digital Compact area and power Poor signal integrity Capacitive/inductive coupling parasitics Dynamic sources of interference: Large signals (e.g. digital states) Power supply currents EM fields Temperature gradients Mechanical stress
16 6/74 FullyDifferential vs SingleEnded Pseudodifferential OpAmps: Signal true info Digital Signal baseline only Interference rejection Area and power overheads (x2)
17 7/74 FullyDifferential vs SingleEnded Pseudodifferential OpAmps: Signal true info Digital Signal baseline only Interference rejection Area and power overheads (x2) Fullscale extension (+6dB) Noise increase (+3dB) SNR (+3dB) Time
18 8/74 FullyDifferential vs SingleEnded Pseudodifferential OpAmps: Signal true info Digital Signal baseline only Interference rejection Area and power overheads (x2) Fullscale extension (+6dB) Noise increase (+3dB) SNR (+3dB) Distortion cancellation (even harm.) Limited by device matching Time
19 9/74 FullyDifferential OpAmps Basic CMOS topology: : : M7 : 2 device multiplicity same aspect ratio
20 20/74 FullyDifferential OpAmps Basic CMOS topology: Differential input only: : : M7?? : 2 device multiplicity same aspect ratio
21 2/74 FullyDifferential OpAmps Basic CMOS topology: Differential input only: : : M7 : 2 device multiplicity 6 current mirror asymmetry Not full cancellation of unwanted terms same aspect ratio Mostly used for singleended signaling
22 22/74 FullyDifferential OpAmps All operating in strong inversion saturation + neglecting CLM Basic CMOS topology: Large signal VTC: : : M7 in conduction M7 M7 in saturation : 2 in saturation in conduction
23 23/74 FullyDifferential OpAmps All operating in strong inversion saturation + neglecting CLM Basic CMOS topology: Large signal VTC: : : M7 in conduction in saturation : 2 Reduced output range in saturation in conduction
24 24/74 FullyDifferential OpAmps All operating in strong inversion saturation + neglecting CLM Basic CMOS topology: Large signal VTC: : : M7 : 2 Reduced output range
25 25/74 FullyDifferential OpAmps All operating in strong inversion saturation + neglecting CLM Basic CMOS topology: Large signal VTC: : : M7 : 2 Reduced output range
26 26/74 FullyDifferential OpAmps All operating in strong inversion saturation + neglecting CLM Basic CMOS topology: Large signal VTC: : : M7 : 2 Prob. Reduced output range More offset contributions Pelgrom's Law Threshold voltage mismatching only
27 27/74 FullyDifferential OpAmps Basic CMOS topology: Small signal differential and common DC gains: : : M7 : 2
28 28/74 FullyDifferential OpAmps Basic CMOS topology: Small signal differential and common DC gains: : : M7 : 2 differential output common output differential input common input
29 29/74 FullyDifferential OpAmps Basic CMOS topology: Small signal differential and common DC gains: : : M7 Perfect matching (= and =M7): : 2 differential output differential input
30 30/74 FullyDifferential OpAmps Basic CMOS topology: Small signal differential and common DC gains: : : M7 Perfect matching (= and =M7): : 2 Real matching (e.g. V TH =V TH2 ): Neglecting common output
31 3/74 FullyDifferential OpAmps Basic CMOS topology: Summary of design guidelines: : : M7 : 2 Reduced output range Matching is critical performance resources
32 32/74 The MonoTransistor Amplifier 2 Differential Topologies 3 Common Mode Feedback 4 Folded Amplifiers 5 Cascode Topologies 6 Gain Enhancement Techniques
33 33/74 CommonMode Output Issue Singleended differential OpAmps: Fullydifferential OpAmps: e.g. max. feedback M7 High sensitivity to technology mismatching ( 7 and )! Welldefined and stable commonmode level Specific auxiliary control circuitry is needed in practice...
34 34/74 CommonMode Output Issue Commonmode feedback (CMFB) loop: Behaviorally equivalent... CMFB control functionality: Sensing commonmode output Computing error according to reference level Applying needed commonmode correction Not to be confused with CMRR! Multistage OpAmps require one CMFB loops for each stage CMFB control design? gain bandwidth accuracy stability
35 35/74 ContinuousTime CMFB Resistivebased sensing: Passive commonmode output estimation R R2
36 36/74 ContinuousTime CMFB Resistivebased sensing: Passive commonmode output estimation R R2 OpAmp original OR is preserved Resistive extra loading......or limited CMFB bandwidth
37 37/74 ContinuousTime CMFB Resistivebased sensing: M7 M8 R R2 Resistive loading is avoided OR severe reduction Power consumption overhead Commonmode output level is technology dependent!
38 38/74 ContinuousTime CMFB Resistivebased sensing: M7 M8 Masterslave automatic tuning R R2 M9 Resistive loading is avoided OR severe reduction Power consumption overhead Commonmode output level is technology dependent!
39 39/74 ContinuousTime CMFB Resistivebased sensing: Lowpass CMFB filtering C R R2 : 2 Compact circuit solution No power consumption overhead Commonmode output defined by technology Strong OR reduction
40 40/74 ContinuousTime CMFB MOSbased sensing: Supposing, and M7 working in deep conduction: M8 M9 0 By CMFB symmetry (=): x x2 M7 By bias symmetry ( 6=M7 and =): Masterslave tuning
41 4/74 ContinuousTime CMFB MOSbased sensing: Supposing, and M7 working in deep conduction: M8 M9 0 By CMFB symmetry (=): x x2 M7 By bias symmetry ( 6=M7 and =): Masterslave tuning Resistive loading is avoided No power consumption overhead Negligible OR reduction Technology compensation Gain nonlinearity
42 42/74 DiscreteTime CMFB Switchedcapacitor (SC) implementation: e.g. fullydifferential integrator stage clock C2P CP CN C2N
43 43/74 DiscreteTime CMFB Switchedcapacitor (SC) implementation: e.g. fullydifferential integrator stage clock M7 C2P CP CFP CFN CN C2N Capacitive CMFB sensing Reduced power overheads Low loopgain
44 44/74 The MonoTransistor Amplifier 2 Differential Topologies 3 Common Mode Feedback 4 Folded Amplifiers 5 Cascode Topologies 6 Gain Enhancement Techniques
45 45/74 Output Range Issue Basic fullydifferential topology (not showing CMFB): : : M7 : 2 Time OR improvement requires very large aspect ratios! Not compatible with other optimization rules (e.g. CMRR)
46 46/74 Folded Topologies Fullydifferential folded OpAmp (not showing CMFB): : :?? M7 M8 M9 0 : : 2 :
47 47/74 Folded Topologies All operating in strong inversion saturation + neglecting CLM Fullydifferential folded OpAmp (not showing CMFB): Still a single stage Opamp! lowimpedance nodes : : M7 M8 M9 0 : : 2 : Static power consumption (x2) Device silicon area (x2)
48 48/74 Folded Topologies All operating in strong inversion saturation + neglecting CLM Fullydifferential folded OpAmp (not showing CMFB): Still a single stage Opamp! lowimpedance nodes : : M7 M8 M9 0 : : 2 : Static power consumption (x2) Fullscale OR optimization Device silicon area (x2)
49 49/74 Folded Topologies All operating in strong inversion saturation + neglecting CLM Fullydifferential folded OpAmp (not showing CMFB): : : M7 M8 M9 0 : : 2 : Static power consumption (x2) Device silicon area (x2) Fullscale OR optimization High supply voltage needed...
50 50/74 Folded Topologies Fullydifferential dual folded OpAmp (not showing CMFB): : : 2 : 2 : M9 0 M7 M8 2 3 : 2 Static power consumption (x3) Device silicon area (x3)
51 5/74 Folded Topologies All operating in strong inversion saturation + neglecting CLM Fullydifferential dual folded OpAmp (not showing CMFB): : : 2 : 2 : Still a single stage Opamp! M9 lowimpedance nodes 0 Suposing: M7 M8 2 3 : 2 Static power consumption (x3) Device silicon area (x3) Same OR optimization Compatible with low supply voltage
52 52/74 Folded Topologies : : Singleended folded OpAmp counterparts: M7 M8 M9 0 : : : : 2 : M7 M8 : M9 2 0 :
53 53/74 Folded Topologies Singleended folded OpAmp counterparts: : : M9 2 : 2 : 0 M7 M8 2 3 : 2 : M9 : 2 : 2 0 M7 M8 2 3 : 2
54 54/74 The MonoTransistor Amplifier 2 Differential Topologies 3 Common Mode Feedback 4 Folded Amplifiers 5 Cascode Topologies 6 Gain Enhancement Techniques
55 55/74 Principle Basis CMOS OpAmp general linear model: input transconductance output resistance Enhancement by increasing MOSFET output impedance?
56 56/74 Principle Basis CMOS OpAmp general linear model: 20dB/dec Frequency input transconductance output resistance Gain improvement: Enhancement by increasing MOSFET output impedance? Accurate feedback functions Lower equivalent input noise No speed enhancement (GBW)
57 57/74 Principle of Operation Output impedance multiplier: Introducing cascoding in OpAmps: DC voltage biasing level cascode device transconductor device my device cascode device Aplicable to most analog basic building blocks (e.g. current mirror, voltage differential pair) voltage attenuation
58 58/74 Basic Cascode OpAmp Lowfrequency smallsignal analysis: CMOS OpAmp model:
59 59/74 Basic Cascode OpAmp Lowfrequency smallsignal analysis: CMOS OpAmp model:
60 60/74 Basic Cascode OpAmp Lowfrequency smallsignal analysis: CMOS OpAmp model: voltage gain factor! similar transconductance series combination voltage gain factor! higher output impedance output impedance of cascode device output impedance of transconductor device
61 6/74 Regulated Cascode OpAmp?? even larger attenuation factors!
62 62/74 Regulated Cascode OpAmp Lowfrequency smallsignal analysis: CMOS OpAmp model: even larger attenuation factors!
63 63/74 Regulated Cascode OpAmp Lowfrequency smallsignal analysis: CMOS OpAmp model: even larger attenuation factors! Minimalist implementation:
64 64/74 Output Range Optimization Basic cascode DC biasing: All operating in strong inversion saturation + neglecting CLM Regulated cascode DC biasing: supposing =: alternative lowvoltage approach: operating in strong inversion conduction
65 65/74 Practical Cascode OpAmps Fully differential + folded + cascode topology example: cascoding not needed here... optimized DC biasing M7 M8 M9 lowimpedance nodes dual cascoding required! 4 5 6
66 66/74 The MonoTransistor Amplifier 2 Differential Topologies 3 Common Mode Feedback 4 Folded Amplifiers 5 Cascode Topologies 6 Gain Enhancement Techniques
67 67/74 Principle Basis CMOS OpAmp general linear model: input transconductance output resistance Enhancement by increasing MOSFET input transconductance?
68 68/74 Principle Basis CMOS OpAmp general linear model: 20dB/dec Frequency input transconductance output resistance Gain improvement: Enhancement by increasing MOSFET input transconductance? Accurate feedback functions Lower equivalent input noise Speed enhancement (GBW)
69 69/74 Partial Positive Feedback Basic differential transconductor:
70 70/74 Partial Positive Feedback Basic differential transconductor: Introducing local positive feedback: Folded structure Crosscoupled pair Partial feedback design by sizing ratio keeping same large signal range : crosscoupled devices : /N /N : : M7 M8 lowimpedance nodes still a single stage transconductor...
71 7/74 Partial Positive Feedback Small signal transconductance: : : /N /N : : M7 M8
72 72/74 Partial Positive Feedback Small signal transconductance: Halfcircuit analysis: : : /N /N : : Perfect symmetry (no mismatching) Infinite tail sink resistance M7 M8 Purely differential input commonmode = virtual ground
73 73/74 Partial Positive Feedback Small signal transconductance: Halfcircuit analysis: : : /N /N : : Perfect symmetry (no mismatching) Infinite tail sink resistance M7 M8 Purely differential input
74 74/74 Practical Gain Enhanced OpAmp Singleended + folded + crosscoupled example: M7 M8 Larger gain and GBW Compatible with folding and cascoding M9 0 Local positive feedback vs global negative feedback: Prone to instability It can generate hysteresis
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