# Experiment #7 MOSFET Dynamic Circuits II

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1 Experiment #7 MOSFET Dynamic Circuits II Jonathan Roderick Introduction The previous experiment introduced the canonic cells for MOSFETs. The small signal model was presented and was used to discuss the performance of each canonic cell. What the previous lab didn t clearly present are the limitations of the canonic cells. These limitations are one reason why circuits don t comprise of just a single stage that incorporates a single canonic cell. An integrated circuit amplifier doesn t consist on just one common source amplifier. To be sure, a common source canonic cell(s) may be used in the amplifier topology, but other elements and canonic cells are also used to bolster the performance of the amplifier. Another example is the voltage buffer. A voltage buffer in an integrated circuit design doesn t consist of a single common drain canonic cell. As you probably discovered in the pervious lab, the gain of a common drain configured MOSFET yields a gain less than unity and, depending on the MOS technology used it can be considerably less than one. This lab will present ways to combine the canonic cells in order to overcome certain inherent limitations of a single cell. The design strategies and topologies presented here are not comprehensive of all the possible solutions thus discovered to overcome the limitations of MOSFETs. However, they should give you insight on how approach practical problems in MOSFET analog integrated circuit design. Common Source Amplifier A common occurrence a circuit designer faces is how do get more gain out of a common source amplifier. One reason is the relatively low transconductance associated with a MOSFET, as compared to a bipolar transistor. A common source amplifier is shown below in figure 7.1. Note that only the ac representation is shown, bias is neglected. R R s C L Figure 7.1. A Common Source Amplifier. 1

2 From the previous lab, it was shown that a common source amplifier has a gain of: A V Vo = = gm R (7.1) V s This is assuming that the output resistance of the MOSFET is much greater than R. If it isn t, than the net effective resistance is the parallel combination of the resistor R and the drain-source resistance of the device. The transconductance, g m, of a MOSFET is defined as: g m W = 2 kn I DQ (7.2) L From these equations it can be seen that the only gain variables that a circuit designer has control over are: Resistance, R, the drain bias current, I DQ, and the gate aspect ratio (or size) of the transistor. In integrated circuit design, a resistor is not usually a passive element as depicted in figure 7.1. Resistances are usually realized by active devices. Large on-chip passive resistance takes up much more area than a resistance realized by using an active device. In the case of the common source amplifier shown in figure 7.1, a PMOS device would be biased with a dc voltage to achieve the desired resistance. Ideally, you would like that PMOS to act like a dc current source, shown in figure 7.2. At low frequency this would maximize the small signal gain due to the ideally infinite resistance associated with a dc current source. I DC R s C L Figure 7.2. An Ideal Common Source Configuration. 2

3 As you have probably already discovered, nothing in circuit design is ideal. Which in this case is also probably beneficial because who could use an amplifier with infinite gain. The point to all of this is to try and maximize the amount of gain you can realistically achieve by making the small resistance as large as possible. In most MOSFET integrated circuits this is achieved by replacing the DC current source in figure 7.2 with a PMOS version of the current mirror that was presented in experiment #5. This is shown below in figure 7.3. Note: In can be seen in figure 7.3 that the PMOS current mirror uses a passive resistor R 1 to establish the reference current, I ref, needed to bias the common source. It should be conveyed that like figure 7.1 this resistance is usually realized with a MOSFET. Normally another NMOS transistor that is either diode connected or biased with a DC voltage is used to generate the required amount of resistance. For the purposes of this explanation it will be left as an effective resistance, R eff. Once again figure 7.3 doesn t tell the whole story. Some means of a DC bias is needed at the gate, this is neglected and it is assumed that the input signal,, has the appropriate amount of DC offset to ensure everything is biased correctly. M 3 M 2 I ref I DQ R eff R s C L Figure 7.3. A Common Source with a Current Mirror Load. One may recognize that the small signal output resistance of the topology feature in figure 7.3,, is nothing more than the parallel combination of the output resistance from the current mirror and common source amplifier. This derivation is left as a prelab exercise. As stated before, a passive on-chip resistor consumes a great deal of area and its resistance is proportional to that area. Thus large value on-chip passive resistors are extremely inefficient, from a layout area standpoint. Thus, the gain of a common source canonic cell was increase by being able to achieve a larger low frequency, small signal resistance with a MOSFET current mirror than what can be realized with typical on-chip passive resistor. However, this all assumes that the drain-to-source (or output) resistance of a MOSFET is very large. As device geometries scale down this assumption begins to fail. This next section will deal with what is known as a cascode configuration. This is nothing more than a combination of canonic cells that helps increase the drain-to-source resistance of a MOSFET. 3

4 Cascode Configuration The cascode configuration is shown in figure 7.4. Going back to experiment #6, one can see that this cascode configuration is nothing more than a common gate that has been stacked on top of the common source amplifier. Thus, knowing the performance of each canonic cell one should be able to calculate the gain by inspection. The new output resistance should be calculated by replacing each transistor with its small signal model. Both of these are left as prelab exercises. R eff V DC M 2 C L R s Figure 7.4. Common Source Cascode. The cascode configuration has a couple of advantages over the traditional common source amplifier. As you should find out in the prelab, the output resistance for short channel devices is increase and hence the gain of the overall circuit is increased. Another benefit is achieved from a speed perspective. The common base transistor reduces what is known as the Miller Effect. In MOSFETs, the Miller Effect is not as problematic as it is in bipolar transistors, but it still can limit the speed of the circuit. The Miller Effect occurs when a capacitor is connected between two nodes that experience inverting gain. This effectively increases the capacitance seen across the nodes by a factor of one plus the gain. Now in a traditional common source configuration there isn t a capacitor explicitly placed between the gate and drain of transistor. However if you go back to the last experiment, one can see that the MOSFET small signal model has parasitic capacitance associated with it. This parasitic capacitance is the gate-drain capacitance, C gd, of the device. Also from experiment #6, it is know that a common source amplifier has a gain of g m between the gate and drain. So in a common source amplifier not only do you already have a high impedance node associated with the drain, but now there is an effective capacitor connected to that node with the value: C = C 1 + g ) (7.3) eff gd ( m 4

5 Hence, one can now see that the time constant associated with this node has increased and will effectively slow the circuit down. This could also potentially render the amplifier unstable if the dominate pole criteria is violated. Bipolar transistors have a much larger g m associated with them, thus the Miller Effect when doing IC design with BJTs is much more pronounced. It was stated above that one of the main benefits of the cascode was to increase the output resistance of the common source, thus increasing the gain. This modification was successful because the assumption of very large drain-source of the traditional common source resistance is no longer valid when dealing with small geometry devices. In figure 7.4, the load is symbolized by an effective resistance, R eff, but it is assumed that this effective resistance would be replace by some sort of active circuitry, i.e. current mirror. Now if the assumption of large drain-to-source resistance is not valid for the traditional common source, then it may not be valid for the devices in the current mirror either. Figure 7.5 shows how to increase the output resistance by applying the cascode configuration to the current mirror. M 4 M 2 M 3 I ref I DQ R ref Figure 7.5. Cascode Current Mirror. The output resistance is derived by replacing all the transis tors with a small signal model and doing a small signal analysis at the output. This is left as a prelab exercise. Conclusion The MOS canonic cells were presented in experiment #6. These cells are the fundamental building blocks of analog integrated circuit design. This lab focused on using the canonic cells in combination to overcome their inherent limitations when used as a single cell. Thus when doing circuit analysis, one may always break down a circuit topology into the canonic cells in order to obtain insight into why a circuit was designed the way it was. An advanced understanding of these basic building blocks will allow a circuit designer to create vast circuit topologies by effectively placing canonic cells as needed. 5

6 BS250P (Courtesy of Zetex ) BS250P Spice Model (Courtesy of ORCAD) XPMOS D G S BS250P.SUBCKT BS250P M MBS250 RG RL E8 C E-12 C E-12 D1 3 5 DBS250.MODEL MBS250 PMOS VTO= RS=2.041 RD=0.697 IS=1E-15 KP= CBD=105E-12 PB=1 LAMBDA=1.2E-2.MODEL DBS250 D IS=2E-13 RS=0.309.ENDS BS250P Reference Reading 1) John Choma, Jr. EE348 lecture notes. University of Southern California. Spring ) David Johns & Ken Martin. Analog integrated Circuit Design. John Wiley & Sons, Inc., New York, ) Paul R. Gray & Robert G. Meyer. Analysis and Design of Analog Integrated Circuits. John Wiley & Sons, Inc., New York,

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