Experiment #7 MOSFET Dynamic Circuits II

Save this PDF as:

Size: px
Start display at page:

Transcription

1 Experiment #7 MOSFET Dynamic Circuits II Jonathan Roderick Introduction The previous experiment introduced the canonic cells for MOSFETs. The small signal model was presented and was used to discuss the performance of each canonic cell. What the previous lab didn t clearly present are the limitations of the canonic cells. These limitations are one reason why circuits don t comprise of just a single stage that incorporates a single canonic cell. An integrated circuit amplifier doesn t consist on just one common source amplifier. To be sure, a common source canonic cell(s) may be used in the amplifier topology, but other elements and canonic cells are also used to bolster the performance of the amplifier. Another example is the voltage buffer. A voltage buffer in an integrated circuit design doesn t consist of a single common drain canonic cell. As you probably discovered in the pervious lab, the gain of a common drain configured MOSFET yields a gain less than unity and, depending on the MOS technology used it can be considerably less than one. This lab will present ways to combine the canonic cells in order to overcome certain inherent limitations of a single cell. The design strategies and topologies presented here are not comprehensive of all the possible solutions thus discovered to overcome the limitations of MOSFETs. However, they should give you insight on how approach practical problems in MOSFET analog integrated circuit design. Common Source Amplifier A common occurrence a circuit designer faces is how do get more gain out of a common source amplifier. One reason is the relatively low transconductance associated with a MOSFET, as compared to a bipolar transistor. A common source amplifier is shown below in figure 7.1. Note that only the ac representation is shown, bias is neglected. R R s C L Figure 7.1. A Common Source Amplifier. 1

2 From the previous lab, it was shown that a common source amplifier has a gain of: A V Vo = = gm R (7.1) V s This is assuming that the output resistance of the MOSFET is much greater than R. If it isn t, than the net effective resistance is the parallel combination of the resistor R and the drain-source resistance of the device. The transconductance, g m, of a MOSFET is defined as: g m W = 2 kn I DQ (7.2) L From these equations it can be seen that the only gain variables that a circuit designer has control over are: Resistance, R, the drain bias current, I DQ, and the gate aspect ratio (or size) of the transistor. In integrated circuit design, a resistor is not usually a passive element as depicted in figure 7.1. Resistances are usually realized by active devices. Large on-chip passive resistance takes up much more area than a resistance realized by using an active device. In the case of the common source amplifier shown in figure 7.1, a PMOS device would be biased with a dc voltage to achieve the desired resistance. Ideally, you would like that PMOS to act like a dc current source, shown in figure 7.2. At low frequency this would maximize the small signal gain due to the ideally infinite resistance associated with a dc current source. I DC R s C L Figure 7.2. An Ideal Common Source Configuration. 2

3 As you have probably already discovered, nothing in circuit design is ideal. Which in this case is also probably beneficial because who could use an amplifier with infinite gain. The point to all of this is to try and maximize the amount of gain you can realistically achieve by making the small resistance as large as possible. In most MOSFET integrated circuits this is achieved by replacing the DC current source in figure 7.2 with a PMOS version of the current mirror that was presented in experiment #5. This is shown below in figure 7.3. Note: In can be seen in figure 7.3 that the PMOS current mirror uses a passive resistor R 1 to establish the reference current, I ref, needed to bias the common source. It should be conveyed that like figure 7.1 this resistance is usually realized with a MOSFET. Normally another NMOS transistor that is either diode connected or biased with a DC voltage is used to generate the required amount of resistance. For the purposes of this explanation it will be left as an effective resistance, R eff. Once again figure 7.3 doesn t tell the whole story. Some means of a DC bias is needed at the gate, this is neglected and it is assumed that the input signal,, has the appropriate amount of DC offset to ensure everything is biased correctly. M 3 M 2 I ref I DQ R eff R s C L Figure 7.3. A Common Source with a Current Mirror Load. One may recognize that the small signal output resistance of the topology feature in figure 7.3,, is nothing more than the parallel combination of the output resistance from the current mirror and common source amplifier. This derivation is left as a prelab exercise. As stated before, a passive on-chip resistor consumes a great deal of area and its resistance is proportional to that area. Thus large value on-chip passive resistors are extremely inefficient, from a layout area standpoint. Thus, the gain of a common source canonic cell was increase by being able to achieve a larger low frequency, small signal resistance with a MOSFET current mirror than what can be realized with typical on-chip passive resistor. However, this all assumes that the drain-to-source (or output) resistance of a MOSFET is very large. As device geometries scale down this assumption begins to fail. This next section will deal with what is known as a cascode configuration. This is nothing more than a combination of canonic cells that helps increase the drain-to-source resistance of a MOSFET. 3

4 Cascode Configuration The cascode configuration is shown in figure 7.4. Going back to experiment #6, one can see that this cascode configuration is nothing more than a common gate that has been stacked on top of the common source amplifier. Thus, knowing the performance of each canonic cell one should be able to calculate the gain by inspection. The new output resistance should be calculated by replacing each transistor with its small signal model. Both of these are left as prelab exercises. R eff V DC M 2 C L R s Figure 7.4. Common Source Cascode. The cascode configuration has a couple of advantages over the traditional common source amplifier. As you should find out in the prelab, the output resistance for short channel devices is increase and hence the gain of the overall circuit is increased. Another benefit is achieved from a speed perspective. The common base transistor reduces what is known as the Miller Effect. In MOSFETs, the Miller Effect is not as problematic as it is in bipolar transistors, but it still can limit the speed of the circuit. The Miller Effect occurs when a capacitor is connected between two nodes that experience inverting gain. This effectively increases the capacitance seen across the nodes by a factor of one plus the gain. Now in a traditional common source configuration there isn t a capacitor explicitly placed between the gate and drain of transistor. However if you go back to the last experiment, one can see that the MOSFET small signal model has parasitic capacitance associated with it. This parasitic capacitance is the gate-drain capacitance, C gd, of the device. Also from experiment #6, it is know that a common source amplifier has a gain of g m between the gate and drain. So in a common source amplifier not only do you already have a high impedance node associated with the drain, but now there is an effective capacitor connected to that node with the value: C = C 1 + g ) (7.3) eff gd ( m 4

5 Hence, one can now see that the time constant associated with this node has increased and will effectively slow the circuit down. This could also potentially render the amplifier unstable if the dominate pole criteria is violated. Bipolar transistors have a much larger g m associated with them, thus the Miller Effect when doing IC design with BJTs is much more pronounced. It was stated above that one of the main benefits of the cascode was to increase the output resistance of the common source, thus increasing the gain. This modification was successful because the assumption of very large drain-source of the traditional common source resistance is no longer valid when dealing with small geometry devices. In figure 7.4, the load is symbolized by an effective resistance, R eff, but it is assumed that this effective resistance would be replace by some sort of active circuitry, i.e. current mirror. Now if the assumption of large drain-to-source resistance is not valid for the traditional common source, then it may not be valid for the devices in the current mirror either. Figure 7.5 shows how to increase the output resistance by applying the cascode configuration to the current mirror. M 4 M 2 M 3 I ref I DQ R ref Figure 7.5. Cascode Current Mirror. The output resistance is derived by replacing all the transis tors with a small signal model and doing a small signal analysis at the output. This is left as a prelab exercise. Conclusion The MOS canonic cells were presented in experiment #6. These cells are the fundamental building blocks of analog integrated circuit design. This lab focused on using the canonic cells in combination to overcome their inherent limitations when used as a single cell. Thus when doing circuit analysis, one may always break down a circuit topology into the canonic cells in order to obtain insight into why a circuit was designed the way it was. An advanced understanding of these basic building blocks will allow a circuit designer to create vast circuit topologies by effectively placing canonic cells as needed. 5

6 BS250P (Courtesy of Zetex ) BS250P Spice Model (Courtesy of ORCAD) XPMOS D G S BS250P.SUBCKT BS250P M MBS250 RG RL E8 C E-12 C E-12 D1 3 5 DBS250.MODEL MBS250 PMOS VTO= RS=2.041 RD=0.697 IS=1E-15 KP= CBD=105E-12 PB=1 LAMBDA=1.2E-2.MODEL DBS250 D IS=2E-13 RS=0.309.ENDS BS250P Reference Reading 1) John Choma, Jr. EE348 lecture notes. University of Southern California. Spring ) David Johns & Ken Martin. Analog integrated Circuit Design. John Wiley & Sons, Inc., New York, ) Paul R. Gray & Robert G. Meyer. Analysis and Design of Analog Integrated Circuits. John Wiley & Sons, Inc., New York,

7 Pre-lab Exercise 1) In Spice, rebuild and simulate the common source amplifier example that was featured in experiment #5. A schematic diagram is shown if figure 5.9. Double the gain by the three methods with in your control that were described in this lab. Verify your designs with Spice simulations. Use procedures a-c below to assist you and record how much the gain did increase for each. Describe any challenges or trade offs that you had to make in your designs. Does simply doubling any of the variables in procedures a-c result in the gain being doubled? Why or why not? a. Double the gate-aspect ratio. b. Double I DQ. This will involve calculating new bias resistor values. Record your new values. c. Double the effective output resistance, while keeping V gs and I DQ the same as before. 2) Derive the small signal output resistance of the common source featured in figure ) Derive the small signal gain and output resistance of the common source cascode in figure ) Neglecting the load, how much greater is the common source cascode output resistance as compared to the traditional common source amplifier (This means the output resistance looking down the drain of the transistor M 2 for the cascode, and for the traditional). 5) Calculate the small signal output resistance of the cascode current mirror shown in figure 7.5. How much larger is it compared to the traditional current mirror. 6) One drawback to using cascode topologies is the amount of signal swing that is allowed (a.k.a. overhead). Replace R eff in figure 7.6 with the cascode current mirror in figure 7.7 and derive an expression for max AC signal swing (i.e. max < < min) that can be achieved. It should be in terms of device DC biasing voltages (i.e. V gs and V ds ) and guarantees that all devices operate in saturation. Note: The 2N7000 and BS250P are not small geometry devices, so the large drain-to-source approximation is normally valid. Device Specifications: Caution: Never exceed the device maximum limitations during design. 2N7000 Idmax=200mA Vdsmax=60V Vth 0.8V BS250P Idmax=-250mA Vdsmax=-45V Vth -1V 7

8 Lab Exercise 1) In the prelab, you were asked to double the gain of a common source amplifier in exercise #1. Build and measure the designs you came up with for procedures a-c. Do your results agree with you Spice results? Why or why not? Use a 200mV peak-to-peak sine wave that has a frequency of 5k to verify your designs. 2) In experiment #6 you were asked to build a common source amplifier and drive a variety of resistive loads (exercise #2). You should have found that a common source cannot drive small resistive loads because it hurts the gain. To remedy this you are given the task of designing a common source, common drain circuit, shown below in figure 7.6. Start with what you did in exercise #2 from experiment #6 and add on the common drain canonic cell. Make sure you correctly bias both transistors in saturation and that the drain current of both transistor is the same. Use previous the work you have done in past two experiments to help correctly bias the circuit. Now repeat the procedure in exercise #2 from experiment #6 for this topology. Do not worry about any gain loss due to the gain of the common drain being less than unity. However, verify any loss of gain is not due to an improperly biased transistor. Did this circuit perform better? Record all your finding. Procedure from exercise #2 from experiment #6: Connect a load of 1Meg Ohm at ut. Measure the output and calculate the gain using a 200mV peak-to-peak 4kHz sine wave. Repeat this procedure for load values of 50k, 5k, 1k, 500, and 50 ohms. Did your results change for any of these values? If so, why? R b1 R d R d1 C c M 2 C c R b2 R ss R ss1 R L Figure 7.6. Common Source, Common Drain Amplifier. 3) Build the circuit from exercise #6 from the prelab. Your job is correctly bias it for maximum signal swing while making sure all devices are in saturation. Measure the maximum signal swing you can achieve by adjusting the amplitude of a 5kHz sine wave. Do these results agree with what you derived in the prelab? Why or why not? 8

Experiment #6 MOSFET Dynamic circuits

Experiment #6 MOSFET Dynamic circuits Jonathan Roderick Introduction: This experiment will build upon the concepts that were presented in the previous lab and introduce dynamic circuits using MOSFETS.

Laboratory Experiment 6 EE348L. Spring 2005

Laboratory Experiment 6 EE348L Spring 2005 B. Madhavan Spring 2005 B. Madhavan Page 1 of 22 EE348L, Spring 2005 B. Madhavan 2 of 22 EE348L, Spring 2005 Table of Contents 6 Experiment #6: MOSFETs Continued...5

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic

MOSFET Amplifier Design

MOSFET Amplifier Design Introduction In this lab, you will design a basic 2-stage amplifier using the same 4007 chip as in lab 2. As a reminder, the PSpice model parameters are: NMOS: LEVEL=1, VTO=1.4,

ECEN 474/704 Lab 6: Differential Pairs

ECEN 474/704 Lab 6: Differential Pairs Objective Design, simulate and layout various differential pairs used in different types of differential amplifiers such as operational transconductance amplifiers

Experiment #12 BJT Differential Pairs

Introduction: Experiment #1 BJT Differential Pairs Jonathan Roderick differential pair is a four port network that is shown in figure 1.1. These ports are labeled through D. However, a differential pair

Experiment 9- Single Stage Amplifiers with Passive Loads - MOS

Experiment 9- Single Stage Amplifiers with Passive oads - MOS D. Yee,.T. Yeung, M. Yang, S.M. Mehta, and R.T. Howe UC Berkeley EE 105 1.0 Objective This is the second part of the single stage amplifier

Solid State Devices & Circuits. 18. Advanced Techniques

ECE 442 Solid State Devices & Circuits 18. Advanced Techniques Jose E. Schutt-Aine Electrical l&c Computer Engineering i University of Illinois jschutt@emlab.uiuc.edu 1 Darlington Configuration - Popular

Lecture 33: Context. Prof. J. S. Smith

Lecture 33: Prof J. S. Smith Context We are continuing to review some of the building blocks for multi-stage amplifiers, including current sources and cascode connected devices, and we will also look at

Lecture 34: Designing amplifiers, biasing, frequency response. Context

Lecture 34: Designing amplifiers, biasing, frequency response Prof J. S. Smith Context We will figure out more of the design parameters for the amplifier we looked at in the last lecture, and then we will

Operational Amplifiers

CHAPTER 9 Operational Amplifiers Analog IC Analysis and Design 9- Chih-Cheng Hsieh Outline. General Consideration. One-Stage Op Amps / Two-Stage Op Amps 3. Gain Boosting 4. Common-Mode Feedback 5. Input

Reading. Lecture 33: Context. Lecture Outline. Chapter 9, multi-stage amplifiers. Prof. J. S. Smith

eading Lecture 33: Chapter 9, multi-stage amplifiers Prof J. S. Smith Context Lecture Outline We are continuing to review some of the building blocks for multi-stage amplifiers, including current sources

Microelectronics Exercises of Topic 5 ICT Systems Engineering EPSEM - UPC

Microelectronics Exercises of Topic 5 ICT Systems Engineering EPSEM - UPC F. Xavier Moncunill Autumn 2018 5 Analog integrated circuits Exercise 5.1 This problem aims to follow the steps in the design of

Chapter 12 Opertational Amplifier Circuits

1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded cascode circuit.

Chapter 7 Building Blocks of Integrated Circuit Amplifiers: Part D: Advanced Current Mirrors

1 Chapter 7 Building Blocks of Integrated Circuit Amplifiers: Part D: Advanced Current Mirrors Current Mirror Example 2 Two Stage Op Amp (MOSFET) Current Mirror Example Three Stage 741 Opamp (BJT) 3 4

ECE315 / ECE515 Lecture 7 Date:

Lecture 7 ate: 01.09.2016 CG Amplifier Examples Biasing in MOS Amplifier Circuits Common Gate (CG) Amplifier CG Amplifier- nput is applied at the Source and the output is sensed at the rain. The Gate terminal

Basic Circuits. Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair,

Basic Circuits Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair, CCS - Basic Circuits P. Fischer, ZITI, Uni Heidelberg, Seite 1 Reminder: Effect of Transistor Sizes Very crude classification:

INTRODUCTION TO ELECTRONICS EHB 222E

INTRODUCTION TO ELECTRONICS EHB 222E MOS Field Effect Transistors (MOSFETS II) MOSFETS 1/ INTRODUCTION TO ELECTRONICS 1 MOSFETS Amplifiers Cut off when v GS < V t v DS decreases starting point A, once

Lab Experiments. Boost converter (Experiment 2) Control circuit (Experiment 1) Power diode. + V g. C Power MOSFET. Load.

Lab Experiments L Power diode V g C Power MOSFET Load Boost converter (Experiment 2) V ref PWM chip UC3525A Gate driver TSC427 Control circuit (Experiment 1) Adjust duty cycle D The UC3525 PWM Control

Experiment 6: Biasing Circuitry

1 Objective UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE105 Lab Experiments Experiment 6: Biasing Circuitry Setting up a biasing

1. The fundamental current mirror with MOS transistors

1. The fundamental current mirror with MOS transistors The test schematic (ogl-simpla-mos.asc): 1. Size the transistors in the mirror for a current gain equal to unity, a 30μA input current and V DSat

ECEN 474/704 Lab 7: Operational Transconductance Amplifiers

ECEN 474/704 Lab 7: Operational Transconductance Amplifiers Objective Design, simulate and layout an operational transconductance amplifier. Introduction The operational transconductance amplifier (OTA)

Current Supply Topology. CMOS Cascode Transconductance Amplifier. Basic topology. p-channel cascode current supply is an obvious solution

CMOS Cascode Transconductance Amplifier Basic topology. Current Supply Topology p-channel cascode current supply is an obvious solution Current supply must have a very high source resistance r oc since

ECE 310L : LAB 9. Fall 2012 (Hay)

ECE 310L : LAB 9 PRELAB ASSIGNMENT: Read the lab assignment in its entirety. 1. For the circuit shown in Figure 3, compute a value for R1 that will result in a 1N5230B zener diode current of approximately

ES 330 Electronics II Homework # 6 Soltuions (Fall 2016 Due Wednesday, October 26, 2016)

Page1 Name Solutions ES 330 Electronics Homework # 6 Soltuions (Fall 016 ue Wednesday, October 6, 016) Problem 1 (18 points) You are given a common-emitter BJT and a common-source MOSFET (n-channel). Fill

Current Mirrors. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-1

Current Mirrors Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08 { Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08 { Current Source and Sink Symbol

Amplifiers Frequency Response Examples

ECE 5/45 Analog IC Design We will use the following MOSFET parameters for hand-calculations and the µm CMOS models for corresponding simulations. Table : Long-channel MOSFET parameters. Parameter NMOS

A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage

A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage EEE 523 Advanced Analog Integrated Circuits Project Report Fuding Ge You are an engineer who is assigned the project to design

University of Pittsburgh

University of Pittsburgh Experiment #4 Lab Report MOSFET Amplifiers and Current Mirrors Submission Date: 07/03/2018 Instructors: Dr. Ahmed Dallal Shangqian Gao Submitted By: Nick Haver & Alex Williams

6.776 High Speed Communication Circuits Lecture 7 High Freqeuncy, Broadband Amplifiers

6.776 High Speed Communication Circuits Lecture 7 High Freqeuncy, Broadband Amplifiers Massachusetts Institute of Technology February 24, 2005 Copyright 2005 by Hae-Seung Lee and Michael H. Perrott High

Lecture 2, Amplifiers 1. Analog building blocks

Lecture 2, Amplifiers 1 Analog building blocks Outline of today's lecture Further work on the analog building blocks Common-source, common-drain, common-gate Active vs passive load Other "simple" analog

Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier

Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in double-ended

Experiment 6: Biasing Circuitry

1 Objective UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE105 Lab Experiments Experiment 6: Biasing Circuitry Setting up a biasing

Laboratory Experiment 5 EE348L. Spring 2005

Laboratory Experiment 5 EE348L Spring 2005 B. Madhavan Spring 2005 B. Madhavan Page 1 of 29 EE348L, Spring 2005 B. Madhavan - 2 of 29- EE348L, Spring 2005 Table of Contents 5 Experiment #5: MOSFETs...5

Laboratory Experiment 8 EE348L. Spring 2005

Laboratory Experiment 8 EE348L Spring 2005 B. Madhavan Spring 2005 B. Madhavan Page 1 of 1 EE348L, Spring 2005 B. Madhavan - 2 of 2- EE348L, Spring 2005 Table of Contents 8 Experiment #8: Introduction

Lecture 16: MOS Transistor models: Linear models, SPICE models. Context. In the last lecture, we discussed the MOS transistor, and

Lecture 16: MOS Transistor models: Linear models, SPICE models Context In the last lecture, we discussed the MOS transistor, and added a correction due to the changing depletion region, called the body

ECE4902 C Lab 7

ECE902 C2012 - Lab MOSFET Differential Amplifier Resistive Load Active Load PURPOSE: The primary purpose of this lab is to measure the performance of the differential amplifier. This is an important topology

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

OTA-output buffer 1 According to the types of loads, the driving capability of the output stages differs. For switched capacitor circuits which have high impedance capacitive loads, class A output stage

DC Coupling: General Trends

DC Coupling: General Trends * Goal: want both input and output to be centered at halfway between the positive and negative supplies (or ground, for a single supply) -- in order to have maximum possible

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

Low power OTA 1 Two-Stage, Miller Op Amp Operating in Weak Inversion Low frequency response: gm1 gm6 Av 0 g g g g A v 0 ds2 ds4 ds6 ds7 I D m, ds D nvt g g I n GB and SR: GB 1 1 n 1 2 4 6 6 7 g 2 2 m1

Laboratory 1 Single-Stage MOSFET Amplifier Analysis and Design Due Date: Week of February 21, 2011, at the beginning of your lab section

Laboratory 1 Single-Stage MOSFET Amplifier Analysis and Design Due Date: Week of February 21, 2011, at the beginning of your lab section Objective To analyze and design single-stage common source amplifiers.

Analog Integrated Circuit Configurations Basic stages: differential pairs, current biasing, mirrors, etc. Approximate analysis for initial design MOSFET and Bipolar circuits Basic Current Bias Sources

Homework Assignment 07

Homework Assignment 07 Question 1 (Short Takes). 2 points each unless otherwise noted. 1. A single-pole op-amp has an open-loop low-frequency gain of A = 10 5 and an open loop, 3-dB frequency of 4 Hz.

Homework Assignment 07

Homework Assignment 07 Question 1 (Short Takes). 2 points each unless otherwise noted. 1. A single-pole op-amp has an open-loop low-frequency gain of A = 10 5 and an open loop, 3-dB frequency of 4 Hz.

Laboratory 1 Single-Stage MOSFET Amplifier Analysis and Design Due Date: Week of October 5, 2015, at the beginning of your lab section

Objective Laboratory 1 Single-Stage MOSFET Amplifier Analysis and Design Due Date: Week of October 5, 2015, at the beginning of your lab section To analyze and design single-stage common source amplifiers.

Gechstudentszone.wordpress.com

UNIT 4: Small Signal Analysis of Amplifiers 4.1 Basic FET Amplifiers In the last chapter, we described the operation of the FET, in particular the MOSFET, and analyzed and designed the dc response of circuits

Laboratory 1 Single-Stage MOSFET Amplifier Analysis and Design Due Date: Week of February 20, 2014, at the beginning of your lab section

Laboratory 1 Single-Stage MOSFET Amplifier Analysis and Design Due Date: Week of February 20, 2014, at the beginning of your lab section Objective To analyze and design single-stage common source amplifiers.

Analog Integrated Circuit Design Exercise 1 Integrated Electronic Systems Lab Prof. Dr.-Ing. Klaus Hofmann M.Sc. Katrin Hirmer, M.Sc. Sreekesh Lakshminarayanan Status: 21.10.2015 Pre-Assignments The lecture

Current Mirrors. Current Source and Sink, Small Signal and Large Signal Analysis of MOS. Knowledge of Various kinds of Current Mirrors

Motivation Current Mirrors Current sources have many important applications in analog design. For example, some digital-to-analog converters employ an array of current sources to produce an analog output

d. Can you find intrinsic gain more easily by examining the equation for current? Explain.

EECS140 Final Spring 2017 Name SID 1. [8] In a vacuum tube, the plate (or anode) current is a function of the plate voltage (output) and the grid voltage (input). I P = k(v P + µv G ) 3/2 where µ is a

EE4902 C Lab 5 MOSFET Common Source Amplifier with Active Load Bandwidth of MOSFET Common Source Amplifier: Resistive Load / Active Load

EE4902 C200 - Lab 5 MOSFET Common Source Amplifier with Active Load Bandwidth of MOSFET Common Source Amplifier: Resistive Load / Active Load PURPOSE: The primary purpose of this lab is to measure the

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1 LECTURE 300 LOW VOLTAGE OP AMPS LECTURE ORGANIZATION Outline Introduction Low voltage input stages Low voltage gain stages Low voltage bias circuits

SAMPLE FINAL EXAMINATION FALL TERM

ENGINEERING SCIENCES 154 ELECTRONIC DEVICES AND CIRCUITS SAMPLE FINAL EXAMINATION FALL TERM 2001-2002 NAME Some Possible Solutions a. Please answer all of the questions in the spaces provided. If you need

EE320L Electronics I. Laboratory. Laboratory Exercise #2. Basic Op-Amp Circuits. Angsuman Roy. Department of Electrical and Computer Engineering

EE320L Electronics I Laboratory Laboratory Exercise #2 Basic Op-Amp Circuits By Angsuman Roy Department of Electrical and Computer Engineering University of Nevada, Las Vegas Objective: The purpose of

ECE4902 C Lab 5 MOSFET Common Source Amplifier with Active Load Bandwidth of MOSFET Common Source Amplifier: Resistive Load / Active Load

ECE4902 C2012 - Lab 5 MOSFET Common Source Amplifier with Active Load Bandwidth of MOSFET Common Source Amplifier: Resistive Load / Active Load PURPOSE: The primary purpose of this lab is to measure the

EE4902 C Lab 7

EE4902 C2007 - Lab 7 MOSFET Differential Amplifier Resistive Load Active Load PURPOSE: The primary purpose of this lab is to measure the performance of the differential amplifier. This is an important

Chapter 4. CMOS Cascode Amplifiers. 4.1 Introduction. 4.2 CMOS Cascode Amplifiers

Chapter 4 CMOS Cascode Amplifiers 4.1 Introduction A single stage CMOS amplifier cannot give desired dc voltage gain, output resistance and transconductance. The voltage gain can be made to attain higher

Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation

Rail-To-Rail Op-Amp Design with Negative Miller Capacitance Compensation Muhaned Zaidi, Ian Grout, Abu Khari bin A ain Abstract In this paper, a two-stage op-amp design is considered using both Miller

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,

What is the typical voltage gain of the basic two stage CMOS opamp we studied? (i) 20dB (ii) 40dB (iii) 80dB (iv) 100dB

Department of Electronic ELEC 5808 (ELG 6388) Signal Processing Electronics Final Examination Dec 14th, 2010 5:30PM - 7:30PM R. Mason answer all questions one 8.5 x 11 crib sheets allowed 1. (5 points)

Microelectronic Circuits II. Ch 10 : Operational-Amplifier Circuits

Microelectronic Circuits II Ch 0 : Operational-Amplifier Circuits 0. The Two-stage CMOS Op Amp 0.2 The Folded-Cascode CMOS Op Amp CNU EE 0.- Operational-Amplifier Introduction - Analog ICs : operational

Improving Amplifier Voltage Gain

15.1 Multistage ac-coupled Amplifiers 1077 TABLE 15.3 Three-Stage Amplifier Summary HAND ANALYSIS SPICE RESULTS Voltage gain 998 1010 Input signal range 92.7 V Input resistance 1 M 1M Output resistance

Applied Electronics II

Applied Electronics II Chapter 2: Differential Amplifier School of Electrical and Computer Engineering Addis Ababa Institute of Technology Addis Ababa University Daniel D./Abel G. April 4, 2016 Chapter

55:041 Electronic Circuits

55:041 Electronic Circuits MOSFETs Sections of Chapter 3 &4 A. Kruger MOSFETs, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width = 1 10-6 m or less Thickness = 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor

Lecture 13. Biasing and Loading Single Stage FET Amplifiers. The Building Blocks of Analog Circuits - III

Lecture 3 Biasing and Loading Single Stage FET Amplifiers The Building Blocks of Analog Circuits III In this lecture you will learn: Current biasing of circuits Current sources and sinks for CS, CG, and

COMPARISON OF THE MOSFET AND THE BJT:

COMPARISON OF THE MOSFET AND THE BJT: In this section we present a comparison of the characteristics of the two major electronic devices: the MOSFET and the BJT. To facilitate this comparison, typical

Topology Selection: Input

Project #2: Design of an Operational Amplifier By: Adrian Ildefonso Nedeljko Karaulac I have neither given nor received any unauthorized assistance on this project. Process: Baker s 50nm CAD Tool: Cadence

I1 19u 5V R11 1MEG IDC Q7 Q2N3904 Q2N3904. Figure 3.1 A scaled down 741 op amp used in this lab

Lab 3: 74 Op amp Purpose: The purpose of this laboratory is to become familiar with a two stage operational amplifier (op amp). Students will analyze the circuit manually and compare the results with SPICE.

Experiment 5 Single-Stage MOS Amplifiers

Experiment 5 Single-Stage MOS Amplifiers B. Cagdaser, H. Chong, R. Lu, and R. T. Howe UC Berkeley EE 105 Fall 2005 1 Objective This is the first lab dealing with the use of transistors in amplifiers. We

EE301 Electronics I , Fall

EE301 Electronics I 2018-2019, Fall 1. Introduction to Microelectronics (1 Week/3 Hrs.) Introduction, Historical Background, Basic Consepts 2. Rewiev of Semiconductors (1 Week/3 Hrs.) Semiconductor materials

Lab 6: MOSFET AMPLIFIER

Lab 6: MOSFET AMPLIFIER NOTE: This is a "take home" lab. You are expected to do the lab on your own time (still working with your lab partner) and then submit your lab reports. Lab instructors will be

Design of High-Speed Op-Amps for Signal Processing

Design of High-Speed Op-Amps for Signal Processing R. Jacob (Jake) Baker, PhD, PE Professor and Chair Boise State University 1910 University Dr. Boise, ID 83725-2075 jbaker@ieee.org Abstract - As CMOS

Experiment #2 OP-AMP THEORY & APPLICATIONS

Experiment #2 OP-MP THEOY & PPLICTIONS Jonathan oderick Scott Kilpatrick Burgess Introduction: Operational amplifiers (op-amps for short) are incredibly useful devices that can be used to construct a multitude

ECE315 / ECE515 Lecture 9 Date:

Lecture 9 Date: 03.09.2015 Biasing in MOS Amplifier Circuits Biasing using Single Power Supply The general form of a single-supply MOSFET amplifier biasing circuit is: We typically attempt to satisfy three

Differential Amplifier Design

Fall - 2009 EE114 - Design Project Differential Amplifier Design Submitted by Piyush Keshri (0559 4497) Jeffrey Tu (0554 4565) On November 20th, 2009 EE114 - Design Project Stanford University Page No.

ETIN25 Analogue IC Design. Laboratory Manual Lab 2

Department of Electrical and Information Technology LTH ETIN25 Analogue IC Design Laboratory Manual Lab 2 Jonas Lindstrand Martin Liliebladh Markus Törmänen September 2011 Laboratory 2: Design and Simulation

System on a Chip. Prof. Dr. Michael Kraft

System on a Chip Prof. Dr. Michael Kraft Lecture 4: Filters Filters General Theory Continuous Time Filters Background Filters are used to separate signals in the frequency domain, e.g. remove noise, tune

UNIT-1 Bipolar Junction Transistors. Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press

UNIT-1 Bipolar Junction Transistors Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press Figure 6.1 A simplified structure of the npn transistor. Microelectronic Circuits, Sixth

Lecture 240 Cascode Op Amps (3/28/10) Page 240-1

Lecture 240 Cascode Op Amps (3/28/10) Page 2401 LECTURE 240 CASCODE OP AMPS LECTURE ORGANIZATION Outline Lecture Organization Single Stage Cascode Op Amps Two Stage Cascode Op Amps Summary CMOS Analog

CMOS Instrumentation Amplifier with Offset Cancellation Circuitry for Biomedical Application

CMOS Instrumentation Amplifier with Offset Cancellation Circuitry for Biomedical Application Author Mohd-Yasin, Faisal, Yap, M., I Reaz, M. Published 2006 Conference Title 5th WSEAS Int. Conference on

EE 330 Laboratory 8 Discrete Semiconductor Amplifiers

EE 330 Laboratory 8 Discrete Semiconductor Amplifiers Fall 2017 Contents Objective:... 2 Discussion:... 2 Components Needed:... 2 Part 1 Voltage Controlled Amplifier... 2 Part 2 Common Source Amplifier...

IOWA STATE UNIVERSITY. EE501 Project. Fully Differential Multi-Stage Op-Amp Design. Ryan Boesch 11/12/2008

IOWA STATE UNIVERSITY EE501 Project Fully Differential Multi-Stage Op-Amp Design Ryan Boesch 11/12/2008 This report documents the design, simulation, layout, and post-layout simulation of a fully differential

MOS IC Amplifiers. Token Ring LAN JSSC 12/89

MO IC Amplifiers MOFETs are inferior to BJTs for analog design in terms of quality per silicon area But MO is the technology of choice for digital applications Therefore, most analog portions of mixed-signal

Experiment 10 Current Sources and Voltage Sources

Experiment 10 Current Sources and Voltage Sources W.T. Yeung and R.T. Howe UC Berkeley EE 105 Fall 2003 1.0 Objective This experiment will introduce techniques for current source biasing. Several different

High Voltage Operational Amplifiers in SOI Technology

High Voltage Operational Amplifiers in SOI Technology Kishore Penmetsa, Kenneth V. Noren, Herbert L. Hess and Kevin M. Buck Department of Electrical Engineering, University of Idaho Abstract This paper

LECTURE 19 DIFFERENTIAL AMPLIFIER

Lecture 19 Differential Amplifier (6/4/14) Page 191 LECTURE 19 DIFFERENTIAL AMPLIFIER LECTURE ORGANIZATION Outline Characterization of a differential amplifier Differential amplifier with a current mirror

ECE 546 Lecture 12 Integrated Circuits

ECE 546 Lecture 12 Integrated Circuits Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine 1 Integrated Circuits IC Requirements

Lecture 030 ECE4430 Review III (1/9/04) Page 030-1

Lecture 030 ECE4430 Review III (1/9/04) Page 0301 LECTURE 030 ECE 4430 REVIEW III (READING: GHLM Chaps. 3 and 4) Objective The objective of this presentation is: 1.) Identify the prerequisite material

Low Output Impedance 0.6µm-CMOS Sub-Bandgap Reference. V. Gupta and G.A. Rincón-Mora

Low Output Impedance 0.6µm-CMOS Sub-Bandgap Reference V. Gupta and G.A. Rincón-Mora Abstract: A 0.6µm-CMOS sub-bandgap reference circuit whose output voltage is, unlike reported literature, concurrently

Atypical op amp consists of a differential input stage,

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 6, JUNE 1998 915 Low-Voltage Class Buffers with Quiescent Current Control Fan You, S. H. K. Embabi, and Edgar Sánchez-Sinencio Abstract This paper presents

ECE 255, MOSFET Amplifiers

ECE 255, MOSFET Amplifiers 26 October 2017 In this lecture, the basic configurations of MOSFET amplifiers will be studied similar to that of BJT. Previously, it has been shown that with the transistor

EECS3611 Analog Integrated Circuit Design. Lecture 3. Current Source and Current Mirror

EECS3611 Analog ntegrated Circuit Design Lecture 3 Current Source and Current Mirror ntroduction Before any device can be used in any application, it has to be properly biased so that small signal AC parameters

Homework Assignment 06

Homework Assignment 06 Question 1 (Short Takes) One point each unless otherwise indicated. 1. Consider the current mirror below, and neglect base currents. What is? Answer: 2. In the current mirrors below,