ECEN 5008: Analog IC Design. Final Exam

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1 ECEN 5008 Initials: 1/10 ECEN 5008: Analog IC Design Final Exam Spring 2004 Instructions: 1. Exam Policy: Time-limited, 150-minute exam. When the time is called, all work must stop. Put your initials on the top of each page before the exam ends. Be sure to put your name in the space below. Open book, open notes. No cooperation is allowed. Show all work, partial credit will be given. 2. Work in the space provided, or on the back of the sheet, if necessary. Turn in these sheets. 3. The exam has 3 problems. The maximum number of points for each question and part is indicated in the square brackets. NAME: Problem 1 [30]: Problem 2 [10]: Problem 3 [60]: TOTAL [100]: Final Course Grade:

2 ECEN 5008 Initials: 2/10 1. [30 points] The approximate small-signal model for a multi-stage op-amp is shown in Figure 1 below. The small-signal parameters are give by: Gm 1 50µ A/ V, Gm2 100µ A/ V R1 R2 1MΩ, Ro 500Ω C C 500 ff, C 5pF v v 1 C 12 v 2 R o v id G m1 *v id R 1 C 1 G m2 *v 1 R 2 C 2 v 2 v o v Figure 1: Op-amp small-signal model a) [8] Solve for the op-amp transfer function from the differential input to the output in the following factored pole-zero form. Work in the space below & on the back of the opposite page, and place your results in the box below. A dm A o s 1 ω p s 1 ω 1 z s 1 ω p 2 Ao f f f z p1 p2

3 ECEN 5008 Initials: 3/10 b) [8] With the op-amp of Fig.1 in the closed-loop non-inverting, unity-gain configuration (as shown in Fig.1(b)), solve for the crossover frequency f c and phase margin PM of the resulting loop gain: v g - v o Figure 1(b) f c PM c) [14] With the op-amp of Fig.1 in the closed-loop configuration shown in Fig.1(c) below, write an analytical expression for the loop gain T(s), then find the approximate maximum value of R 1 (within ~20%) such that the closed-loop system has a R 2 100k phase margin PM > 60. v g R 1 - v o C L 100pF Figure 1(c) T ( s) R 1_ max

4 ECEN 5008 Initials: 4/10 2. [10 points] Find an analytical expression for the -3dB bandwidth of the amplifier circuit shown in Fig. 2 below using the ZVTC method. The transconductance amplifier can be modeled with infinite input impedance and an output current gain of G. m C 1 R 3 V i R 1 I o R 4 G m V o R 2 I o G m *(V -V - ) R 5 Figure 2 f 3 db

5 ECEN 5008 Initials: 5/10 3. [60 points] All parts to this problem refer to Figure 3 (last page of exam), which shows a schematic diagram of the ST Microelectronics TS271 op-amp. You may tear this page off for your reference and do not need to turn it in. Device parameters and sizes are given in Fig.3. Each of the following subparts can be completed independently ((a) through (f)). (a) Basic Operation: 1. [2] Determine the inverting & non-inverting inputs of the op-amp and circle the correct completion of the following sentence: a. The gate of T1 is: inverting or non-inverting 2. [5] At the top of Fig.3, five sections of the circuit are identified in brackets. Briefly (one phrase each) explain the purpose or function of each block below: Group (1): Group (2): Group (3): Group (4): Group (5): (b) DC Bias: 1. [5] Assuming that i 1 10µ A, V V V i i 0, V output 0V, and there is no load current, solve for the DC bias currents and voltages i 2 through i 5 and v 1 through v 4. Place your work below and on the back of the opposite page and your results in the table below: Currents Voltages i 2 v 1 i 3 v 2 i 4 v 3 i 5 v 4

6 ECEN 5008 Initials: 6/10 (c) Small-signal model & gain: 1. [5] At the DC operating point i 1 10µ A i i 0 V, V output 0V, solve for the smallsignal voltage gain from the differential input v id to v 3 : v v id 3 A3 2. [5] At the DC operating point i 1 10µ A, V V V i i 0, V o 0V, solve for the small-signal voltage gain from the differential input v id to the op-amp output. You may assume that the opamp has a R L 1 MΩ load attached to the output. A o v v output id

7 ECEN 5008 Initials: 7/10 3. [5] At the DC operating point i 1 10µ A, V V V i i 0, V o 0V, solve for the approximate output resistance of the op-amp (looking into the Output terminal): R output (d) Input and output operating range: 1. [5] Determine the common-mode input voltage range of the op-amp and specify the limiting transistors at each boundary: V icm T: T:

8 ECEN 5008 Initials: 8/10 2. [5] Determine the output voltage range of the op-amp and specify the limiting transistors at each boundary: V output T: T: (e) Current limitations: 1. [3] Solve the slew-rate limitation of the op-amp due to capacitor C13pF: SR

9 ECEN 5008 Initials: 9/10 2. [8] Solve for the short circuit output current (assuming the output is shorted to ground (0V)) for the two cases: very large positive and negative input differential voltages. V 0, ( ) id >> I o short V 0, ( ) id << I o short (f) Current reference and bias. This part focuses on the group (1) current bias circuitry. You may assume the following process characteristics: VT Thermal Voltage : VT 25.9mV, 86µ V C T Vbe Base emitter : Vbe 660mV, 2mV C T 1 R2 3 Resistor : TC( R2 ) 1200 ppm C C R T 2

10 ECEN 5008 Initials: 10/10 1. [5] Write an expression for the DC component of the bias current i r as a function of device parameters and R 2 (Note: bipolar transistor T 25 has twice the emitter area of T 24, as shown by double arrows). I r 2. [2] Solve for R2 such that the bias current I r 10µ A. R 2 3. [5] Solve for the temperature coefficient of the bias current: TC( i ) r 1 I r ir T

11 V v 1 v 2 v 3 v 4 i 1 i 2 3pF i 4 i 5 i r i 3 NMOS : PMOS : µ C n µ C p ox ox -5V 100µ A / V, V 1V, γ 0, λ 0.01[ V 2 1 tn n n 50µ A / V, V 1V, γ 0, λ 0.02[ V 2 1 tp p p ] ] All MOS devices have W/L 10u / 1u except for: T 7 &T 16 both have W/L 20u / 1u All MOS body connections tied to device source Figure 3: Schematic from ST Microelectronics TS271C Op-Amp Datasheet

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