Chapter 12 Opertational Amplifier Circuits

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1 1 Chapter 12 Opertational Amplifier Circuits

2 Learning Objectives 1) The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded cascode circuit. 2) The complete circuit of an analog IC classic: the 741 op-amp. Though 40 years old, the 741 circuit includes so many interesting and useful design techniques that its study is still a must. 3) Applications of negative feedback within op-amp circuits to achieve bias stability and increased CMRR. 4) How to break a large analog circuit into its recognizable blocks, to be able to make the analysis amendable to a pencil-and-paper approach which is the best way to learn design. 5) Some of the modern techniques employed in the design of low-voltage single-supply BJT op amps. 6) Most importantly, how the different topics we learned about in the preceding chapters come together in the design of the most important analog IC the op amp. 2

3 3 Two Stage OPAMP

4 12.1 The Two Stage CMOS Op Amp 4 Figure 12.1 The basic two-stage CMOS op-amp configuration.

5 The Circuit 5 Two Stages: Differential Pair Q 1 /Q 2. Biased by current source Q 5 Fed by a reference current I REF Current Mirror Load Q 3 /Q 4. Frequency Compensation Voltage Gain 20V/V to 60V/V Reasonable Common-Mode Rejection Ratio (CMRR)

6 Input Common-Mode Range and Output Swing 6 (eq12.1) dc offset elimination: (eq12.4) (eq1 W/L W/L 2 W/L 6 7 W/L 4 5 (eq12.2) common-mode input: VICM VSS Vtn VOV 3 Vtp (eq12.3) common-mode input: V V V V V ICM DD OV 5 tp OV1 V V V V V V V V SS OV 3 tn tp ICM tp OV 1 OV 5 2.5) VSS VOV 6 vo VDD VOV 7

7 Voltage Gain 7 Simplified equivalent circuit model for small-signal operation of CMOS amplifier. Input resistance is practically infinite (R in ). First-stage transconductance (G m1 ) is equal to values for Q 1 and Q 2. Since Q 1 and Q 2 are operated at equal bias currents (I/2) and equal overdrive voltages, equation (12.7) applies.

8 Input Common-Mode Range and Output Swing 8 (eq12.7) stage-one transconductance: (eq12.8) (eq12.9) (eq12.10) R r r 1 o2 o4 o2 A2 o4 A4 (eq12.11) gain of first stage: r V / I /2 r V / I /2 1 m1 1 (eq12.12) gain of first stage: A gm1 r r (eq12.13) gain of first stage: A 1 G A G R 1 m1 o2 2 I / 2 V o / V V V OV 1 A2 A4 V I OV 1 OV 1

9 Input Common-Mode Range and Output Swing (eq12.14) stage-two transconductance: (eq12.15) (eq12.16) (eq12.17) R r r 2 o6 o7 r V / I o6 A6 D6 r V / I V / I o4 A7 D7 A7 D6 G g m2 m6 2I V D6 OV 6 (eq12.18) voltage gain of second stage: A2 Gm2R2 (eq12.19) voltage gain of second stage: A g r r (eq12.21) output resistance: R r r 2 m6 o6 o (eq12.20) voltage gain of second stage: A2 / V V V (eq12.21) overall dc gain: Av Gm1R1Gm 2R2 (eq12.22) overall dc gain: A g r r g r v r OV 6 A6 A7 m1 o2 o4 m6 o6 o7 o o6 o7 9

10 Common-Mode Rejection Ratio 10 CMRR of two-stage amplifier is determined by first stage CMRR = [g m1 (r o2 r o4 )[2g m3 R SS ] RSS is output resistance of the bias source Q 5 CMRR is of the order of (g m r o ) 2 G m r o is proportional to V A /V OV CMRR is increased if long channels are used.

11 (eq12.25) (eq12.26) ( eq12.27) (eq12.28) (eq12.29) Frequency Response C C C C C C 1 gd2 db2 gd 4 db4 gs6 C C C C C f f f 2 db6 db7 gd7 L P1 P2 P2 1 2 R G Gm2 2 C G 2 C 1 m2 2 2 m2 C R C C (eq12.30) (eq12.31) (eq12.32) (eq12.33) f f t v P1 t G G C m1 C m1 m2 C A f G 2 C G G C 2 m1 m2 11

12 Frequency Response 12 Figure 12.4: Typical frequency response of the two-stage op amp.

13 Frequency Response 13 (eq12.34) (eq12.36) Z (eq12.37) P2 1 t tan fp 2 1 t tan fz total O 1 ft 1 ft 90 tan tan fz fz (eq12.38) phase margin 180 f f O total

14 Slew Rate 14 Figure 12.6: A unity-gain follower with a large step input. Since the output voltage cannot change immediately, a large differential voltage appears between the opamp input terminals.

15 Slew Rate 15 Figure 12.7: Model of the two-stage CMOS op-amp of Fig when a large differential voltage is applied.

16 Relationship Between SR and f t Simple relationship exists between unity-gain bandwidth (f t ) and slew rate (SR). Equations (12.31) through (12.40). SR = 2f t V OV Slew rate is determined by the overdrive voltage at which first-stage transistors are operated. For a given bias current I, a larger V OV is obtained if Q 1 and Q 2 are p- channel devices. 16

17 Power Supply Rejection Ratio (PSRR) 17 mixed-signal circuit IC chip which combines analog and digital devices. Switching activity in digital portion results in ripple within power supplies. This ripple may affect op amp output. power-supply rejection ratio the ability of a circuit to eliminate any ripple in the circuit power supplies. PSRR is generally improved through utilization of capacitors.

18 Power Supply Rejection Ratio (PSRR) 18 (eq12.42) (eq12.43) (eq12.44) (eq12.45) (eq12.46) (eq12.47) (eq12.48) PSRR A / A PSRR A / A A v / v o A v / v o o7 vo vss r o6 r o7 A v / v o d d dd ss r ss r r o7 o6 o7 PSRR A / A g r r g r r d m1 o2 o4 m6 o6

19 Design Trade-Offs The performance of the two-stage CMOS amplifier are primarily determined by two design parameters: Length (L) of channel of each MOSFET Overdrive voltage (V OV ) at which transistor is operated. transition frequency (f T ) is defined below. It determined high-frequency operation. 19 (eq12.49) f g / 2 C C T m gs gd

20 20 Folded-Cascode CMOS Op Amp

21 12.2 The Folded-Cascode CMOS Op Amp 21 Figure 12.8: Structure of the folded-cascode CMOS op amp.

22 12.2 The Folded-Cascode CMOS Op Amp 22

23 Input Common-Mode Range and Output Swing 23 (eq12.51) (eq12.52) (eq12.53) (eq12.54) (eq12.55) (eq12.56) V V V V ICM max DD OV 9 tn V V V V V ICM min SS OV 11 OV1 tn V V V V V V V V SS OV 11 OV1 tn ICM DD OV 9 tn V V V V BIAS DD OV 10 SG4 v V V V Omax DD OV 10 OV 4 vomin VSS VOV 7 VOV 5 V tn

24 Voltage Gain 24 (eq12.57) (eq12.58) (eq12.59) (eq12.60) (eq12.61) (eq12.62) (eq12.63) G g g G m m1 m2 m 2 I /2 V R R R OV 1 OV 1 o o4 o6 R g r r r o4 m4 o4 o2 o10 R g r r o6 m6 o6 o8 o m4 o4 o2 o10 m6 o6 o8 v m o V R g r r r g r r A G R I

25 The Circuit 25 Figure 12.10: Small-signal equivalent circuit of the folded-cascode CMOS amplifier. Note that this circuit is in effect an operational transconductance amplifier (OTA).

26 Op Amp

27 12.3 The 741 Op-Amp Circuit 27 Figure 12.13: The 741 op-amp circuit: Q11, Q12, and R5 generate a reference bias current; IREF. Q10, Q9, and Q8 bias the input stage, which is composed of Q1 to Q7. The second gain stage is composed of Q16 and Q17 with Q13B acting as active load. The class AB output stage is formed by Q14 and Q20 with biasing devices Q13A, Q18, and Q19, and an input buffer Q23. Transistors Q15, Q21, Q24, and Q22 serve to protect the amplifier against output short circuits and are normally cut off.

28 741 consists of three-stages: The Input Stage 28 Input Differential Stage (Q 1 through Q 7 ) Emitter Followers: Q 1, Q 2 Differential Common-Base: Q 3, Q 4 Load Circuit: Q 5, Q 6, Q 7 Biasing: Q 8, Q 9, Q 10 Intermediate Single-Ended High-Gain Stage Output-Buffering Stage (other transistors)

29 The Second Stage Consists of Q 16, Q 17, and Q 13B Emitter Follower: Q 16 Common-Emitter: Q 17 Load: Q 13B Output of second stage is taken at collector of Q 17. Capacitor C C is connected in feedback path of second stage. Frequency compensation using Miller Technique. 29

30 The Output Stage 30 Provides low output resistance. Able to supply relatively large load current. With minimal power dissipation. Consists of Q 14 and Q 20. Complementary pair. Transistors Q 18 and Q 19 are fed by current source Q 13A and bias transistors Q 14 and Q 20.

31 Device Parameters 31 npn: I S = A, b = 200, V A = 125V pnp: I S = A, b = 50, V A = 50V Q 13A and Q 13B : I SA = 0.25(10-14 )A, I SB = 0.75(10-14 )A These devices are non-standard. Q 14 and Q 20 will be assumed to have area three times of the standard device for increased loading.

32 12.4 DC Analysis of the for V V 15 V, V V 0. 7 V, I 0.73mA I CC EE EB11 BE 12 REF REF V V V V R CC EB12 BE11 EE I REF (eq12.75) VTln I R IC 10 (eq12.76) IC5 IC6 (eq12.77) IC5 IC3 I (eq12.78) IC6 IC4 I 2I V (eq12.79) IC7 IE7 b 5 N C10 4 IR BE 6 2 R 3

33 Biasing 33 Figure 12.14: The Widlar current source that biases the input stage.

34 12.4 DC Analysis of the

35 12.4 DC Analysis of the

12.5 Small Signal Analysis of 741 36 Figure 12.

36 12.5 Small Signal Analysis of Figure 12.21: Small-signal equivalent circuit for the input stage of the 741 op amp.

12.5 Small Signal Analysis of 741 37 Figure 12.

37 12.5 Small Signal Analysis of Figure 12.25: Small-signal equivalent-circuit model of the second stage.

38 38 Other Op Amp Circuits

39 Problem

40 From John and Martin 40

41 From Razavi 41

42 Others 42 Search for Discrete Op Amp Design [0] [1] [2] [3] [4] [5]

43 Summary 43 Most CMOS op-amps are designed to operate as part of a VLSI circuit and thus required to drive only small capacitive loads. Therefore, most do not have a low-output-resistance stage. There are basically two approaches to the design of CMOS opamps: a two-stage configuration and a single-stage topology using the folded-cascode circuit. In the two-stage CMOS op-amp, approximately equal gains are realized in the two stages. The threshold mismatch together with the low transconductance of the input stage result in a larger input offset voltage for the CMOS opamps than for bipolar units. Miller compensation is employed in the two-stage CMOS op-amp, but a series resistor is required to place the transmission zero at either s = infinity or on the negative real axis. CMOS op-amps have better slew rates.

44 Summary Use of the cascode configuration increases the gain of a CMOS amplifier stage by about two orders of magnitude, thus making possible a single-stage op-amp. The dominant pole of the folded-cascode op-amp is determined by the total capacitance at the output CL. Increasing CL improves the phase margin at the expense of reducing bandwidth. By using two complementary input differential pairs in parallel, the common-mode range may be extended. The output voltage swing of the folded-cascode op-amp may be extended by utilizing a wide-swing current mirror in place of the cascode mirror. The internal circuit of the 741 op-amp embodies many of the design techniques employed in bipolar analog integrated circuits. The 741 circuit consists of an input differential stage, a high-gain single-ended second stage, and a class AB output stage. It is the basis for many other devices. 44

45 Summary To obtain low input offset voltage and current, and high CMRR, the 741 input stage is designed to be perfectly balanced. The CMRR is increased by common-mode feedback, which also stabilizes the dc operating point. To obtain high input resistance and low input bias current, the input stage of the 741 is operated as a very low current level. The use of Miller Frequency compensation in the 741 circuit enables locating the dominant pole at a very low frequency, while utilizing a relatively small compensating capacitance. Two-stage op-amps may be modeled as a transconductance amplifier feeding an ideal integrator with CC as the integrating capacitor. The slew rate of a two-stage op-amp is determined by the first-stage bias current and frequency-compensation capacitor. While the 741 and similar op-amps nominally operate from 15V power supplies, modern BJT op-amps typically utilize a single ground-referenced supply of only 2 or 3V. 45

Solid State Devices & Circuits. 18. Advanced Techniques

ECE 442 Solid State Devices & Circuits 18. Advanced Techniques Jose E. Schutt-Aine Electrical l&c Computer Engineering i University of Illinois jschutt@emlab.uiuc.edu 1 Darlington Configuration - Popular