Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier"

Transcription

1 Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in double-ended (Differential) operation the output is measured between, two nodes those have opposite signal excursions around a fixed point. An important advantage of differential operation over single ended is higher immunity to environmental noise. Another common mode rejection advantage at differential operation occurs with noisy power supply The Difference Amplifiers The convenient way to represent the two input voltages is by their mean and difference values. The definition of the differential and common mode input voltages by the relations is given as, (5.1) (5.2) One way of implementing a difference amplifier is to use to single ended amplifier as shown in Fig The output would be the difference of two outputs (v o1 and v o2 ). Similar to the definition of common mode and differential signals, the common mode and differential output can be defined as, (5.3) (5.4) The common mode and the differential gains then become as, (5.5) 66

2 Figure 5.1. Possible implementation of a difference amplifier (5.6) A good differential amplifier has high differential gain independent of input common mode voltage, while the common mode gain should be as low as possible. The common mode rejection ratio, a figure of merit is defined as, (5.7) In simple suggested circuit (Fig. 5.1) the MOSFET currents, and hence the differential gain will depend on common mode voltage. A good difference amplifier will amplify only difference signal and not common mode signal. Hence, a better difference amplifier can be implemented by adding a current source to keep total MOSFET currents constant as shown in Fig.5.2. When the common mode voltage applied at two inputs changes, the voltage will get changed only at the node where two sources join (V s ). The current remains unchanged due to current source and hence the differential gain is unaffected by the common mode voltage. This gives a high CMRR. 67

3 Figure 5.2. A better implementation of the difference amplifier Single Ended Differential Amplifier A single output, which is proportional to the difference between two inputs, is needed very often. Thus, we need to combine the two outputs. This is achieved using current mirror loads, as shown in Fig.5.3. We can write, Figure 5.3. A difference amplifier with single-ended output 68

4 Due to current mirror action, I(M p2 ) = I(M p1 ). As Mp1 and Mn1 are in series, I(M p1 ) = I(M n1 ). Therefore, (5.8) Thus, we have single output proportional to difference of inputs. By definition we can write, Where, G m is the equivalent transconductance of differential amplifier stage. The effective G m is just the g m of either of the differential pair MOSFETs. Here the output being current, the circuit is also known as a differential transconductance amplifier. The output voltage of this circuit is the output current multiplied by the effective output resistance of the stage [46]. (5.9) Thus voltage gain can be given analogous to single stage CS amplifier as, and, Where, C tot includes C dg and C d of M n2 and M p2 respectively and the load capacitance if any Double Ended (Fully) Differential Amplifier An important application of fully differential amplifiers is their ability to suppress the effect of common mode interferences [40]. Like CS stage, linear resistors need not be implemented as the load of a differential pair. The differential amplifier can employ active load like diode connected or current source as shown in Fig

5 Figure 5.4 Differential pair with (a) Diode connected and (b) Current source load The small signal gain of differential amplifier can be obtained using the half circuit concept. For Fig.5.4 (a), the load is a MOSFET with gate and drain shorted which becomes a diode. The impedance offered by diode is (1/g m r o ) 1/g m. Where g m is a transconductance and r o is output resistance of diode connected MOSFET. The differential gain then becomes (5.10) Neglecting r o compared to 1/g m, (5.11) However, from (4.16) g m1 is given as (5.12) Also realizing the fact that M 1 and M 3 carry equal currents, voltage gain becomes as (5.13) 70

6 Similarly the small signal differential gain of current source load differential amplifier can be found out. The impedances offered by current sources will be r o3 and r o4. Thus the voltage gain becomes, (5.14) The diode-connected load consumes voltage headroom, thus creating a tradeoff between the output voltage swings, the voltage gain and ICMR. For given bias current and input device dimensions, the value of gain is decided by overdrive of PMOS diode-connected device. To get higher gain the aspect ratio of PMOS device must decrease thereby increasing the overdrive voltage and decreasing the common mode level at the output. The current source load can provide a relatively higher gain due to the output resistance of current source device. However, this limits the output voltage swing. To raise the voltage gain, the output resistance of current source device should be high. This increase in output resistance maintaining same overdrive voltage is brought by increasing W and L of the device, which leads to the large capacitance at output node [41]. To alleviate the above difficulty, part of bias currents of input MOSFETs can be provided by current sources with diode-connected loads as shown in Fig.5.5. The idea here is to lower the g m of load devices by reducing their current instead of aspect ratio. If M 5 and M 6 carry eighty percent of drain current of M 1 and M 2, the current through M 3 and M 4 is reduced by five times. For given overdrive of load devices, the transconductance of M 3 and M 4 is reduced by five times. Due to this, the differential gain is now five times as that of only diode-connected load. Figure 5.5. Differential pair with diode connected and current source load 71

7 5.1.4 Implementation of Single Ended Differential Amplifier The basic single ended differential amplifiers play a very important role in Monolithic IA. Hence, we started designing of single ended differential amplifier by replacing source resistance by improved current sources. The differential amplifier with active load and single ended output is the commonly used differential amplifier in CMOS analog circuits (Fig.5.6). This single ended differential amplifier has excellent features in terms of selfbias capability, common mode rejection, voltage gain and the gain-bandwidth product. In reference books, the simplified analysis of differential amplifier with active load and single ended output is specified. The differential voltage gain is evaluated by means of easy procedure, by replacing MOSFETs with small signal equivalent model. The analysis shows that the sources at input are at virtual ground for signal in case of pure differential input [47]. The circuit shown in Fig. 5.6 can be analyzed with some approximations. Using half circuit concept and replacing MOSFETs with small signal equivalent circuit the differential mode gain can be found out as, Figure 5.6. Single ended CMOS differential amplifier with active load and current source 72

8 Similarly, the common mode gain of differential amplifier in Fig. 5.6 can be derived as, The CMRR is directly proportional to differential mode gain and inversely proportional to common mode gain. Hence, keeping desired differential mode gain constant, the CMRR can be increased by using a tail current mirror source with higher output resistance. Hence, we are replacing tail current source by Wilson current mirror source that has higher output resistance. The output resistance R o of Wilson current mirror source from small signal equivalent model as per (4.73) is given by, (5.15) Figure 5.7. Single ended differential amplifier with current source replaced by Wilson mirror current source. 73

9 This shows that the output resistance of Wilson mirror current source is too larger as compared to the tail current mirror source in Fig Thus, improvement in CMRR can be expected. The complete circuit of single ended differential amplifier with modified current source is shown in Fig The simulated results are shown in Table 5.1 with the size of MOSFETs selected as M 1,2 = 40/1 µm/µm, M 3,4 = 58/0.25 µm/µm, M 5,6,7,8 = 10/0.25 µm/µm. The CMRR is seen to be increased by 10 times. Table 5.1: Simulated Results Parameters Differential amplifier with Differential amplifier with Wilson current mirror source mirror current source. V d 1mV 5mV V od 113mV 555mV A d V c 1V 1V V oc 40mV 3.02mV A c CMRR 69 db db Implementation of Double Ended (Fully) Differential Amplifier The load of a double differential amplifier can be diode connected or current source. The diode-connected load consumes voltage headroom thus reducing the output voltage swing, voltage gain and input CM range [50]. The current source load can provide higher voltage gain but at the cost of higher drain to source voltage required to keep MOSFET in saturation. In order to overcome the difficulty with diode connected and current source loads the part of bias current of input MOSFETs M 1, M 2 can be provided by PMOS current sources as shown in Fig

10 Figure 5.8. Double ended Differential Amplifier with diode connected and current source Loads The idea is to lower the g m of load devices by reducing their current instead of their aspect ratio (W/L) P. If M 5 and M 6 carry 80% of drain current of M 1 and M 2, the current through M 3 and M 4 gets reduced by five times. This translates to a factor of five reduction in transconductance of M 3 and M 4, hence as per (1) the differential gain increases by five times. The small signal gain of above balance differential amplifier will be in the range of 10 to 20 and the common mode gain will get reduced by five times as compared to diode connected loads [11][18]. The simulated results are as shown in Table 5.2. Table 5.2: Simulated Results of Double Ended Differential Amplifier Simulated results for Parameters Current source Diode Load Load Combined Load Ad Ac CMRR db db db 5.2 Operational Amplifiers (Op Amp) An operational amplifier is roughly defined as a high gain difference amplifier. High means a value adequate for the applications, typically in the range of 10 1 to Op amps 75

11 are usually employed in a feedback system; hence, their loop gain is selected according to the precision required for the closed loop system blocks. The efforts to serve as generalpurpose building block sought to create an ideal op amp, with very high voltage gain, high input impedance, and low output impedance but at the cost of speed, output voltage swings, and power dissipation [48]. Nowadays op amp design proceeds with realizing the trade-off between the parameters. Let us consider following op amp design parameters with importance and significance of each [42]. Gain The open loop gain of op amp determines the precision of the feedback system utilizing the op amp. Depending on application, the required gain may vary by four orders of magnitude. To compromise with speed and output voltage swings, the minimum required gain must be known. A high open loop gain may also be necessary to reduce nonlinearity. Small-Signal Bandwidth The high frequency behavior of op amp is desired in many applications. The open loop gain begins to drop with increase in frequency of operation, thus creating larger errors in the feedback system. The small signal bandwidth is usually defined as the unity-gain frequency f u, which is greater than 1 GHz for today s op amps. Sometimes the 3-dB frequency, f 3-dB, may also be specified. Large-Signal Bandwidth Op amps must operate with large transient signals in many modern applications. The nonlinear phenomena of op amp make it difficult to characterize the speed by simply small signal properties such as the open loop response. The large signal analysis shows that a large difference momentarily drives op amp into a nonlinear region of operation. Output Swing Many applications of op amp require large voltage swings to accommodate a wide range of signal amplitudes. Fully differential op amps became quite popular with need for large voltage swings. The double-ended differential amplifier circuits generate complementary outputs, thereby doubling the available swing. As seen from analog design octagon and 76

12 chapter earlier, the maximum voltage swing trades with device size and bias currents and hence speed. Achievement of large swings is also one of the challenges in today s op amp design. Linearity Op amps if operated in open loop suffer from substantial nonlinearities. In large gain differential amplifiers, the input pair of MOSFETs exhibits a nonlinear relationship between its differential drain current and input voltage. This problem of nonlinearity is tackled by two approaches one using fully differential form to suppress even-harmonics and secondly setting high open loop gain such that closed loop feedback system achieves adequate linearity. Actually, in many feedback systems linearity rather than the gain error requirement decides the choice of the open-loop gain. Noise and Offset The minimum signal level processed faithfully is determined by the input noise and offset of op amp. In op amp circuits, several devices decide noise and offset thus requiring large dimensions or bias currents. The trade off also exists between noise and output swing. With a given bias current, the overdrive of the load devices is lowered to permit larger swings at the output, thus transconductance increases and also drain noise current. Supply Rejection Many times op amps are used in mixed-signal systems and connected to noisy digital supply lines. The performance of op amps in presence of noise is quite important especially with increase in noise frequency. Fully differential topologies are used for this purpose One Stage Op-Amps All the differential amplifiers studied in earlier sections can be considered as op amps. Two topologies of differential amplifiers are shown in Fig. 5.9, single-ended and doubleended (differential) outputs. The small-signal low-frequency gain of both the circuits is given by g mn (r on r op ), where the P and N subscripts denote NMOS and PMOS devices. This value of gain provided by single stage differential amplifiers scarcely exceeds 20 in 77

13 submicron devices with typical currents. Generally, the bandwidth is determined by inter electrode capacitances and load capacitance, C L. The single-ended differential amplifier circuit exhibits a mirror pole whereas the double-ended does not. This difference is critical as far as stability of circuit is concerned. Both the circuits suffer from noise contributed by MOSFET devices. To achieve high gain the differential cascode topologies can be used as shown in Fig These cascode configurations of both single-ended and differential Figure 5.9. Simple op-amp topologies output op amps provide a gain of the order of g mn [(g mn r 2 on) (g mp r 2 op), but at the cost of reduced output swing and added pole. These configurations are known as telescopic cascode op amps. The single-ended cascode op amp circuit offers a mirror pole at node X, thus creating stability issue. The output swing of differential output cascode op amp is given by 2[V DD - (V OD1 +V OD3 +V CSS + V OD5 + V OD7 )]. This shows that the output swings of telescopic cascode op amps are limited compared to simple op amps. 78

14 Figure Cascode op amps The difficulty in shorting inputs and outputs is another drawback of the telescopic cascode op amp. This is required when op amp is used as a buffer but then cascode op amp will work for certain range of input as a buffer. Above two drawbacks of telescopic cascode op amps are overcome by folded cascode op amp. The folded cascode op amp also will offer the capability of handling input commonmode levels close to supply voltage. Telescopic cascode op amps can also be designed to provide a single-ended output. The cascode current mirror load converts the differential currents of main devices M 3 and M 4 to the single-ended output voltage as depicted in Fig.5.11 (a). However, here the voltage at X is given as V X =V DD - V GS5 - V GS7 and the output voltage V OUT is limited to V DD - V GS5 - V GS7 + V TH6. Thus one PMOS threshold voltage is wasted in the output swing. To improve the output voltage swing the PMOS load can be modified as shown in Fig (b). Here the MOSFETs M 7 and M 8 are biased at the edge of the triode region. Actually the circuit of Fig. 5.11(a) suffers from two disadvantages as compared to its counterpart in Fig. 5.11(b). First, it provides only half the maximum output voltage swing. Secondly, it includes a mirror pole at node X, thus limiting the speed of feedback systems using such amplifier. 79

15 Figure 5.11.Cascode op amps with single-ended output Design Example Statement: Design a fully differential telescopic op amp with specifications as : V DD = 3V, differential output maximum swing = 3V, power dissipation less than 0.5 mw, Voltage gain Assume µ n C ox = 60µA/V 2, µ p C ox = 30µA/V 2, λ n = 0.11V -1, λ p = 0.22V -1 (for effective channel 0.5µm), body effect coefficient γ = 0, V THN = V THP = 0.7V. Design Steps - The op amp topology along with two current mirrors fixing the drain currents of M 7 - M 9 is shown in Fig Let us begin with power dissipation, total current available is 0.167mA out of which half will be required for current mirrors and half available for the circuit. Each cascode branch thus carries a current around 40µA. The required output swing is 3V differential, thus each output node must be able to swing by 1.5V without driving any of the MOSFET into triode region. Therefore the total voltage available for M 9 and each cascode branch is equal to 1.5V. Hence, V OD7 + V OD5 + V OD3 + V OD1 + V OD9 = 1.5V. As M 9 carries maximum current 80µA, choosing V OD9 = 0.5V, leaving 1V for remaining four MOSFETs in cascode branch. Also M 5 - M 8, being PMOS suffer from low mobility, thus allocating over drive of 300mV approximately to each. Finally remaining 400mV is allocated between M 1 and M 3, 200mV each. 80

16 Figure Op amp topology along with two current mirrors With drain current and overdrive voltage known of each MOSFET, the aspect ratio can be found out from (4.6) of drain current. To get lower device capacitances the minimum channel length of MOSFET is selected 0.5µm. Thus we get the aspect ratios as (W/L) 1-4 = 11, (W/L) 5-8 = 14, (W/L) 9 = 4. Now to find out theoretical voltage gain, g m and r o will be required of MOSFETs which can be calculated using (4.15) and (4.17) g m1-4 = 4 x 10-4 A/V, g m5-8 = 2.67 x 10-4 A/V r o1-4 = 227.2kΩ, r o5-8 = kΩ The voltage gain of telescopic cascode op amp A g m1 [(g m3 r o1 r o3 ) ( g m5 r o5 r o7 ) = 1179 This gain is much lower than the desired gain To increase the gain we recognized that g m r o (WL/I D ). Thus keeping I D constant the gain can be increased by scaling W and L simultaneously keeping ratio constant. 81

17 Figure 5.13 Schematic of Telescopic cascode op-amp As M 1 M 4 appear in signal path, to keep their capacitances minimum their size will not be scaled. The PMOS devices M 5 M 8 affect the signal to smaller extent and hence are scaled. By scaling W and L, r o gets scaled while g m remains constant. Let us assume that scaling is done 1.4 times, therefore (W/L) 5-8 will be 21/0.7. Also λ p gets reduced by 1.4 times that is Modified PMOS devices, now will require slightly larger overdrive due to increase in dimension. Thus allotting 50mV more to M 5-8 and reducing overdrive of M 9 by 100 mv. The new dimension of M 9 comes out to be (W/L) 9 = 16. Now calculated gain comes out to be around The schematic of telescopic cascode op-amp simulated is shown in Fig and frequency and phase response comes out to be as shown in Fig

18 Figure 5.14 Frequency and phase response of Telescopic cascode op-amp 5.3 Source Followers A high voltage gain can be achieved from common source amplifier with high load impedance. If amplifier is required to drive a low impedance load then a buffer must be placed after amplifier. A buffer will drive the low impedance load with negligible loss of signal strength [53]. The common drain stages (source followers) are used as building blocks in a large number of high speed or high frequency applications, due to their intrinsic simplicity and wideband characteristics. The source followers suffer from non-ideal effects such as body effects, channel length modulations, signal-dependent capacitive effects and frequency distortions arising from capacitive loads. These non-ideal effects create a trade off among linearity, bandwidth and power dissipation. The analysis of source followers is based on non-linear parameters g m, g mb and r o in a low frequency small signal model. For NMOS source follower (NSF) as well as PMOS source follower (PSF), the input signal is applied to the gate and output is taken from the source. For signal levels above threshold voltage, the output voltage is equal to input voltage minus gate source voltage [52]. The gate source voltage consists of threshold and over drive voltage. If both these 83

19 voltages are constant, then output voltage is simply input voltage added with offset. The small signal gain would then be unity. Thus, the source follows the gate and circuit is known as a source follower. Actually threshold voltage depends on the body effect and the over drive depends on drain current. Also even if the drain current is kept constant, the overdrive depends to some extent on the drain-source voltage. Small signal equivalent circuits of MOSFETs with body effect can be used to evaluate the analysis of source follower circuits NMOS and PMOS Source Follower A. Small Signal Analysis of NSF The NSF in Fig consists of NMOS input transistor and NMOS current source as a load. The input signal V i consists of the DC biasing voltage V TH and the ac signal v i whereas the output signal V o consists of a DC biasing voltage V DS and the ac signal v o. For n-well process, the bulks of M 1 and M 2 share the same substrate. Hence, NSF suffers from the body effect. Figure 5.15 NMOS Source follower (NSF) circuit The small signal equivalent circuit of NSF is shown in Fig The body terminal is connected to lowest supply voltage (ground) to maintain source-body pn junction reverse biased. Since source is connected to output, v bs changes with output and g mb generator is active [1]. The load current source formed with M 2 is replaced by its drain resistance r o2. 84

20 Applying KVL around input loop, Figure 5.16 Small signal equivalent circuit of NSF (5.16) When the output is open circuited, i o = 0 and applying KCL at output node gives (5.17) From (5.16) substituting for v gs into (5.17) and rearranging, (5.18) If load current source is ideal,, (5.18) simplifies to (5.19) If r o1 is finite, the open circuit voltage gain of source follower is less than unity even if body effect is neglected. The variation in output voltage changes the drain-source voltage and the current through r o1. The large signal analysis shows that the over drive on gate also depends on the drain source voltage unless channel length modulation is negligible. This causes the small signal gain to be less than unity. 85

21 If, (5.20) Equation (5.20) shows that the voltage gain of the source follower is less than unity and it depends on =, which is typically in the range of 0.1 to 0.3. In addition, χ depends on source-body voltage, which is equal to v o when the body is grounded. Hence, gain found out in (5.20) depends on output voltage, causing distortion for large signal changes in the output. This can be overcome by selecting the type of source follower n-channel or p- channel fabricated in an isolated well. The well can be connected to source making v sb =0. In this case the parasitic capacitance from well to substrate increases reducing the bandwidth of source follower. The output resistance of source follower can be calculated from Fig by driving the output with a voltage source v o and setting v i = 0. (5.21) Then, (5.22) It is seen that the body effect reduces the output resistance, which is desirable as the source follower produces a voltage output. This desired effect results from the nonzero small signal current drawn by the g m generator. As and, this output resistance becomes, same as input resistance of common gate amplifier. The source followers are used as buffers and level shifters. They are more flexible as a level shifter because the dc value of V GS can be adjusted by changing aspect ratio W/L. B. Small Signal Analysis of PSF With the circuit of PSF, the most of designs have utilized a body tied PMOS input transistor to remove the bulk modulation effect and to improve the precision. This is possible as PMOS and NMOS transistors share the same substrate. Due to lower mobility 86

22 of PMOS devices, this results in higher output impedance than NSF. Also the transconductance efficiency is low in PSFs which results into small drive ability and a larger silicon area. Fig shows a conventional PSF in an n-well process which includes a PMOS input transistor and a PMOS current source. The small signal equivalent model for PSF will be same as NSF. In high frequency equivalent model, PSF will have additional capacitance due to bulk-well. In addition, the channel length modulation coefficients of M 1 and M 2 in PSF are smaller than that of NSF. This gives better linearity of PSF. Figure PMOS Source follower (PSF) circuit The Super Source Follower The output resistance of source follower is approximately 1/(g m +g mb ). As MOSFETs have much lower transconductance, this output resistance may be too high especially when a resistive load is to be driven. The output resistance can be reduced by increasing transconductance with increase in aspect ratio W/L of source follower and its dc bias current. This requires a proportionate increase in the area and power dissipation. To minimize the area and power dissipation required for low R o, the source follower configuration is used as shown in Fig The super follower as shown in Fig uses negative feedback through M 2 to reduce the output resistance [36].The qualitative analysis shows that, when the input voltage is constant and the output voltage increases; the drain 87

23 current of M 1 also increases, resulting into increased gate-source voltage of M 2.As a result, the drain current of M 2 increases, reducing the output resistance. Figure 5.18 Super-source follower circuit The dc bias current in M 2 is the different between I 1 and I 2, thereforei 1 > I 2 is required for proper operation. This condition can be used to find small signal parameters of MOSFETs. The small signal equivalent circuit is shown in Fig The body effect of M 2 is neglected becausev bs2 = 0. The polarities voltage controlled current sources for NMOS and PMOS are identical. The current sources I 1 and I 2 are replaced by their internal resistances r 1 and r 2 respectively. If the current sources I 1 and I 2 are ideal, r o1 and r o2. For practical current sources these resistances are large but finite. To find output resistance of the super source follower, set v i =0 and find the current i o that flows into the output node when it is driven by a voltage vo. Applying KCL at output under these conditions to Fig. 5.19, (5.23) Similarly applying KCL at drain of M 1 with v i = 0, (5.24) 88

24 Substituting for v 2 from (5.24) into (5.23) and rearranging gives, (5.25) Consider I 1 and I 2 ideal, r 1 and r 2. Also if r o2 and (g m1 +g mb1 ) r o1 >>1, (5.26) Figure 5.19 Small signal equivalent circuit of super source follower This is the output resistance of super source follower. Comparing (5.26) with (5.22), shows that the negative feedback through M 2 reduces the output resistance by a factor of about g m2 r o1. The open circuit voltage gain of super source follower can be found out from small signal equivalent circuit with the output open circuited. Applying KCL at the output node gives, (5.26) Also applying KCL at drain of M 1 gives, (5.27) 89

25 Substituting for v 2 from (5.26) into (5.27) and rearranging gives, (5.28) Assuming ideal current sources gives, (5.29) Comparing the open circuit voltage gain of the super source follower (5.29) with the open circuit voltage gain of a simple source follower (5.19) it is seen that the deviation of this gain from unity is greater in super source follower than a simple source follower. If,, this difference is small and the conclusion is that the super source follower has little effect on the open circuit voltage gain. The product g m r o for MOSFET is given by relation Where µ is mobility of charge carriers, C ox is gate oxide capacitance, λ is channel length modulation coefficient and W/L is aspect ratio. In addition, λ α 1/L, hence we get Therefore, the width and length can be adjusted to get desired product g m r o without changing I d Design Example Statement: Design a source follower with V DD = 3V, I D = 1 ma, having voltage gain close to unity output resistance not more than 100Ω and to handle input 2V p-p. Design steps - 90

26 As voltage gain desired is close to unity, the PMOS source follower with current source load as shown in Fig.5.17, will be preferred which has got less severe body effect compared to NMOS. Now from data given, And (Say which is close to unity) Thus we get, g m1 = To find overdrive, Therefore, The overdrive for M 1 can be calculated using relation, Thus V od1 =0.202 V Now the drain currents of both MOSFETs will be equal and given as, And As both MOSFETs carry same current above equations can be equated giving, We get, 91

27 Thus, Assuming wide band application let L= 0.5 µm, maximum value of V od2 is V, but allotting V od2 = 0.65 V. Then we get, Figure 5.20 Schematic of PSF 92

28 Figure 5.21 Frequency and phase response of PSF If (W/L) 1 =1000, (W) 1 = 500 µm. (W/L) 2 = let take 120, (W) 2 =60 µm. The schematic of PSF simulated is shown in Fig and as expected, the wide band frequency response is obtained as shown in Fig This chapter deals with the different configurations of the differential amplifiers used in the schematic of IA. The detailed designing of the telescopic cascode op amp is carried out which forms basis for the designing of various circuits in the IA. The last stage in most of the monolithic circuits is a buffer. The buffer can be designed using NMOS or PMOS source followers but one designed with PMOS gives properties close to a good buffer. The function of level shifter also is well accomplished by source follower. ***** 93

Chapter 13: Introduction to Switched- Capacitor Circuits

Chapter 13: Introduction to Switched- Capacitor Circuits Chapter 13: Introduction to Switched- Capacitor Circuits 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4 Switched-Capacitor Integrator 13.5 Switched-Capacitor

More information

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1 Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1 LECTURE 300 LOW VOLTAGE OP AMPS LECTURE ORGANIZATION Outline Introduction Low voltage input stages Low voltage gain stages Low voltage bias circuits

More information

CHAPTER 4 ULTRA WIDE BAND LOW NOISE AMPLIFIER DESIGN

CHAPTER 4 ULTRA WIDE BAND LOW NOISE AMPLIFIER DESIGN 93 CHAPTER 4 ULTRA WIDE BAND LOW NOISE AMPLIFIER DESIGN 4.1 INTRODUCTION Ultra Wide Band (UWB) system is capable of transmitting data over a wide spectrum of frequency bands with low power and high data

More information

Difference between BJTs and FETs. Junction Field Effect Transistors (JFET)

Difference between BJTs and FETs. Junction Field Effect Transistors (JFET) Difference between BJTs and FETs Transistors can be categorized according to their structure, and two of the more commonly known transistor structures, are the BJT and FET. The comparison between BJTs

More information

6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers

6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers 6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott Broadband Communication

More information

Unit 3: Integrated-circuit amplifiers (contd.)

Unit 3: Integrated-circuit amplifiers (contd.) Unit 3: Integrated-circuit amplifiers (contd.) COMMON-SOURCE AND COMMON-EMITTER AMPLIFIERS The Common-Source Circuit The most basic IC MOS amplifier is shown in fig.(1). The source of MOS transistor is

More information

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,

More information

MOS Field Effect Transistors

MOS Field Effect Transistors MOS Field Effect Transistors A gate contact gate interconnect n polysilicon gate source contacts W active area (thin oxide area) polysilicon gate contact metal interconnect drain contacts A bulk contact

More information

An Improved Bandgap Reference (BGR) Circuit with Constant Voltage and Current Outputs

An Improved Bandgap Reference (BGR) Circuit with Constant Voltage and Current Outputs International Journal of Research in Engineering and Innovation Vol-1, Issue-6 (2017), 60-64 International Journal of Research in Engineering and Innovation (IJREI) journal home page: http://www.ijrei.com

More information

Improving Amplifier Voltage Gain

Improving Amplifier Voltage Gain 15.1 Multistage ac-coupled Amplifiers 1077 TABLE 15.3 Three-Stage Amplifier Summary HAND ANALYSIS SPICE RESULTS Voltage gain 998 1010 Input signal range 92.7 V Input resistance 1 M 1M Output resistance

More information

Low voltage, low power, bulk-driven amplifier

Low voltage, low power, bulk-driven amplifier University of Arkansas, Fayetteville ScholarWorks@UARK Electrical Engineering Undergraduate Honors Theses Electrical Engineering 5-2009 Low voltage, low power, bulk-driven amplifier Shama Huda University

More information

A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER

A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei ABSTRACT A novel class-ab architecture for single-stage operational amplifiers is presented. The structure

More information

Metal-Oxide-Silicon (MOS) devices PMOS. n-type

Metal-Oxide-Silicon (MOS) devices PMOS. n-type Metal-Oxide-Silicon (MOS devices Principle of MOS Field Effect Transistor transistor operation Metal (poly gate on oxide between source and drain Source and drain implants of opposite type to substrate.

More information

Basic OpAmp Design and Compensation. Chapter 6

Basic OpAmp Design and Compensation. Chapter 6 Basic OpAmp Design and Compensation Chapter 6 6.1 OpAmp applications Typical applications of OpAmps in analog integrated circuits: (a) Amplification and filtering (b) Biasing and regulation (c) Switched-capacitor

More information

Lecture 20: Passive Mixers

Lecture 20: Passive Mixers EECS 142 Lecture 20: Passive Mixers Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California, Berkeley EECS 142 Lecture 20 p.

More information

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

Radivoje Đurić, 2015, Analogna Integrisana Kola 1 OTA-output buffer 1 According to the types of loads, the driving capability of the output stages differs. For switched capacitor circuits which have high impedance capacitive loads, class A output stage

More information

DESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER

DESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER DESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER Mayank Gupta mayank@ee.ucla.edu N. V. Girish envy@ee.ucla.edu Design I. Design II. University of California, Los Angeles EE215A Term Project

More information

Lecture 350 Low Voltage Op Amps (3/26/02) Page 350-1

Lecture 350 Low Voltage Op Amps (3/26/02) Page 350-1 Lecture 350 Low Voltage Op Amps (3/26/02) Page 3501 LECTURE 350 LOW VOLTAGE OP AMPS (READING: AH 415432) Objective The objective of this presentation is: 1.) How to design standard circuit blocks with

More information

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic

More information

6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain- Bandwidth Issue for Broadband Amplifiers

6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain- Bandwidth Issue for Broadband Amplifiers 6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain- Bandwidth Issue for Broadband Amplifiers Massachusetts Institute of Technology February 17, 2005 Copyright 2005

More information

BJT Amplifier. Superposition principle (linear amplifier)

BJT Amplifier. Superposition principle (linear amplifier) BJT Amplifier Two types analysis DC analysis Applied DC voltage source AC analysis Time varying signal source Superposition principle (linear amplifier) The response of a linear amplifier circuit excited

More information

Chapter 12 Opertational Amplifier Circuits

Chapter 12 Opertational Amplifier Circuits 1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded cascode circuit.

More information

Homework Assignment 07

Homework Assignment 07 Homework Assignment 07 Question 1 (Short Takes). 2 points each unless otherwise noted. 1. A single-pole op-amp has an open-loop low-frequency gain of A = 10 5 and an open loop, 3-dB frequency of 4 Hz.

More information

Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation

Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation Rail-To-Rail Op-Amp Design with Negative Miller Capacitance Compensation Muhaned Zaidi, Ian Grout, Abu Khari bin A ain Abstract In this paper, a two-stage op-amp design is considered using both Miller

More information

MOSFET & IC Basics - GATE Problems (Part - I)

MOSFET & IC Basics - GATE Problems (Part - I) MOSFET & IC Basics - GATE Problems (Part - I) 1. Channel current is reduced on application of a more positive voltage to the GATE of the depletion mode n channel MOSFET. (True/False) [GATE 1994: 1 Mark]

More information

Design of High-Speed Op-Amps for Signal Processing

Design of High-Speed Op-Amps for Signal Processing Design of High-Speed Op-Amps for Signal Processing R. Jacob (Jake) Baker, PhD, PE Professor and Chair Boise State University 1910 University Dr. Boise, ID 83725-2075 jbaker@ieee.org Abstract - As CMOS

More information

A Unity Gain Fully-Differential 10bit and 40MSps Sample-And-Hold Amplifier in 0.18μm CMOS

A Unity Gain Fully-Differential 10bit and 40MSps Sample-And-Hold Amplifier in 0.18μm CMOS A Unity Gain Fully-Differential 0bit and 40MSps Sample-And-Hold Amplifier in 0.8μm CMOS Sanaz Haddadian, and Rahele Hedayati Abstract A 0bit, 40 MSps, sample and hold, implemented in 0.8-μm CMOS technology

More information

IJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 02, 2016 ISSN (online):

IJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 02, 2016 ISSN (online): IJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 02, 2016 ISSN (online): 2321-0613 Design & Analysis of CMOS Telescopic Operational Transconductance Amplifier (OTA) with

More information

Chapter 15 Goals. ac-coupled Amplifiers Example of a Three-Stage Amplifier

Chapter 15 Goals. ac-coupled Amplifiers Example of a Three-Stage Amplifier Chapter 15 Goals ac-coupled multistage amplifiers including voltage gain, input and output resistances, and small-signal limitations. dc-coupled multistage amplifiers. Darlington configuration and cascode

More information

Chapter 11. Differential Amplifier Circuits

Chapter 11. Differential Amplifier Circuits Chapter 11 Differential Amplifier Circuits 11.0 ntroduction Differential amplifier or diff-amp is a multi-transistor amplifier. t is the fundamental building block of analog circuit. t is virtually formed

More information

ANALOG FUNDAMENTALS C. Topic 4 BASIC FET AMPLIFIER CONFIGURATIONS

ANALOG FUNDAMENTALS C. Topic 4 BASIC FET AMPLIFIER CONFIGURATIONS AV18-AFC ANALOG FUNDAMENTALS C Topic 4 BASIC FET AMPLIFIER CONFIGURATIONS 1 ANALOG FUNDAMENTALS C AV18-AFC Overview This topic identifies the basic FET amplifier configurations and their principles of

More information

Course Outline. 4. Chapter 5: MOS Field Effect Transistors (MOSFET) 5. Chapter 6: Bipolar Junction Transistors (BJT)

Course Outline. 4. Chapter 5: MOS Field Effect Transistors (MOSFET) 5. Chapter 6: Bipolar Junction Transistors (BJT) Course Outline 1. Chapter 1: Signals and Amplifiers 1 2. Chapter 3: Semiconductors 3. Chapter 4: Diodes 4. Chapter 5: MOS Field Effect Transistors (MOSFET) 5. Chapter 6: Bipolar Junction Transistors (BJT)

More information

Low Power and Fast Transient High Swing CMOS Telescopic Operational Amplifier

Low Power and Fast Transient High Swing CMOS Telescopic Operational Amplifier RESEARCH ARTICLE OPEN ACCESS Low Power and Fast Transient High Swing CMOS Telescopic Operational Amplifier Akshay Kumar Kansal 1, Asst Prof. Gayatri Sakya 2 Electronics and Communication Department, 1,2

More information

Chapter 8. Field Effect Transistor

Chapter 8. Field Effect Transistor Chapter 8. Field Effect Transistor Field Effect Transistor: The field effect transistor is a semiconductor device, which depends for its operation on the control of current by an electric field. There

More information

A low voltage rail-to-rail operational amplifier with constant operation and improved process robustness

A low voltage rail-to-rail operational amplifier with constant operation and improved process robustness Graduate Theses and Dissertations Graduate College 2009 A low voltage rail-to-rail operational amplifier with constant operation and improved process robustness Rien Lerone Beal Iowa State University Follow

More information

ISSN:

ISSN: 468 Modeling and Design of a CMOS Low Drop-out (LDO) Voltage Regulator PRIYADARSHINI JAINAPUR 1, CHIRAG SHARMA 2 1 Department of E&CE, Nitte Meenakshi Institute of Technology, Yelahanka, Bangalore-560064,

More information

Gechstudentszone.wordpress.com

Gechstudentszone.wordpress.com UNIT 4: Small Signal Analysis of Amplifiers 4.1 Basic FET Amplifiers In the last chapter, we described the operation of the FET, in particular the MOSFET, and analyzed and designed the dc response of circuits

More information

EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design

EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design References: Analog Integrated Circuit Design by D. Johns and K. Martin and Design of Analog CMOS Integrated Circuits by B. Razavi All figures

More information

ES250: Electrical Science. HW6: The Operational Amplifier

ES250: Electrical Science. HW6: The Operational Amplifier ES250: Electrical Science HW6: The Operational Amplifier Introduction This chapter introduces the operational amplifier or op amp We will learn how to analyze and design circuits that contain op amps,

More information

University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1. A High Speed Operational Amplifier

University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1. A High Speed Operational Amplifier University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1 A High Speed Operational Amplifier A. Halim El-Saadi, Mohammed El-Tanani, University of Michigan Abstract This paper

More information

Design of a High Speed Mixed Signal CMOS Mutliplying Circuit

Design of a High Speed Mixed Signal CMOS Mutliplying Circuit Brigham Young University BYU ScholarsArchive All Theses and Dissertations 2004-03-12 Design of a High Speed Mixed Signal CMOS Mutliplying Circuit David Ray Bartholomew Brigham Young University - Provo

More information

Operational Amplifiers

Operational Amplifiers Monolithic Amplifier Circuits: Operational Amplifiers Chapter Jón Tómas Guðmundsson tumi@hi.is. Week Fall 200 Operational amplifiers (op amps) are an integral part of many analog and mixedsignal systems

More information

INF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation

INF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation INF3410 Fall 2013 Compensation content Introduction Two Stage Opamps Compensation Slew Rate Systematic Offset Advanced Current Mirrors Operational Transconductance Amplifiers Current Mirror Opamps Folded

More information

Special-Purpose Operational Amplifier Circuits

Special-Purpose Operational Amplifier Circuits Special-Purpose Operational Amplifier Circuits Instrumentation Amplifier An instrumentation amplifier (IA) is a differential voltagegain device that amplifies the difference between the voltages existing

More information

Lecture 240 Cascode Op Amps (3/28/10) Page 240-1

Lecture 240 Cascode Op Amps (3/28/10) Page 240-1 Lecture 240 Cascode Op Amps (3/28/10) Page 2401 LECTURE 240 CASCODE OP AMPS LECTURE ORGANIZATION Outline Lecture Organization Single Stage Cascode Op Amps Two Stage Cascode Op Amps Summary CMOS Analog

More information

2. Single Stage OpAmps

2. Single Stage OpAmps /74 2. Single Stage OpAmps Francesc Serra Graells francesc.serra.graells@uab.cat Departament de Microelectrònica i Sistemes Electrònics Universitat Autònoma de Barcelona paco.serra@imb-cnm.csic.es Integrated

More information

Design and Simulation of Low Dropout Regulator

Design and Simulation of Low Dropout Regulator Design and Simulation of Low Dropout Regulator Chaitra S Kumar 1, K Sujatha 2 1 MTech Student, Department of Electronics, BMSCE, Bangalore, India 2 Assistant Professor, Department of Electronics, BMSCE,

More information

Voltage Feedback Op Amp (VF-OpAmp)

Voltage Feedback Op Amp (VF-OpAmp) Data Sheet Voltage Feedback Op Amp (VF-OpAmp) Features 55 db dc gain 30 ma current drive Less than 1 V head/floor room 300 V/µs slew rate Capacitive load stable 40 kω input impedance 300 MHz unity gain

More information

Technology-Independent CMOS Op Amp in Minimum Channel Length

Technology-Independent CMOS Op Amp in Minimum Channel Length Technology-Independent CMOS Op Amp in Minimum Channel Length A Thesis Presented to The Academic Faculty by Susanta Sengupta In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy

More information

Due to the absence of internal nodes, inverter-based Gm-C filters [1,2] allow achieving bandwidths beyond what is possible

Due to the absence of internal nodes, inverter-based Gm-C filters [1,2] allow achieving bandwidths beyond what is possible A Forward-Body-Bias Tuned 450MHz Gm-C 3 rd -Order Low-Pass Filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V Supply Joeri Lechevallier 1,2, Remko Struiksma 1, Hani Sherry 2, Andreia Cathelin

More information

Design of Low Power High Speed Fully Dynamic CMOS Latched Comparator

Design of Low Power High Speed Fully Dynamic CMOS Latched Comparator International Journal of Engineering Research and Development e-issn: 2278-067X, p-issn: 2278-800X, www.ijerd.com Volume 10, Issue 4 (April 2014), PP.01-06 Design of Low Power High Speed Fully Dynamic

More information

CMOS Operational Amplifier

CMOS Operational Amplifier The George Washington University Department of Electrical and Computer Engineering Course: ECE218 Instructor: Mona E. Zaghloul Students: Shunping Wang Yiping (Neil) Tsai Data: 05/14/07 Introduction In

More information

Low Power Op-Amp Based on Weak Inversion with Miller-Cascoded Frequency Compensation

Low Power Op-Amp Based on Weak Inversion with Miller-Cascoded Frequency Compensation Low Power Op-Amp Based on Weak Inversion with Miller-Cascoded Frequency Compensation Maryam Borhani, Farhad Razaghian Abstract A design for a rail-to-rail input and output operational amplifier is introduced.

More information

Basic Information of Operational Amplifiers

Basic Information of Operational Amplifiers EC1254 Linear Integrated Circuits Unit I: Part - II Basic Information of Operational Amplifiers Mr. V. VAITHIANATHAN, M.Tech (PhD) Assistant Professor, ECE Department Objectives of this presentation To

More information

THE TREND toward implementing systems with low

THE TREND toward implementing systems with low 724 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 7, JULY 1995 Design of a 100-MHz 10-mW 3-V Sample-and-Hold Amplifier in Digital Bipolar Technology Behzad Razavi, Member, IEEE Abstract This paper

More information

Lecture 030 ECE4430 Review III (1/9/04) Page 030-1

Lecture 030 ECE4430 Review III (1/9/04) Page 030-1 Lecture 030 ECE4430 Review III (1/9/04) Page 0301 LECTURE 030 ECE 4430 REVIEW III (READING: GHLM Chaps. 3 and 4) Objective The objective of this presentation is: 1.) Identify the prerequisite material

More information

Gechstudentszone.wordpress.com

Gechstudentszone.wordpress.com 8.1 Operational Amplifier (Op-Amp) UNIT 8: Operational Amplifier An operational amplifier ("op-amp") is a DC-coupled high-gain electronic voltage amplifier with a differential input and, usually, a single-ended

More information

PRECISION N-CHANNEL EPAD MOSFET ARRAY DUAL HIGH DRIVE NANOPOWER MATCHED PAIR

PRECISION N-CHANNEL EPAD MOSFET ARRAY DUAL HIGH DRIVE NANOPOWER MATCHED PAIR TM ADVANCED LINEAR DEVICES, INC. PRECISION N-CHANNEL EPAD MOSFET ARRAY DUAL HIGH DRIVE NANOPOWER MATCHED PAIR e EPAD ALD194 E N A B L E D VGS(th)= +.4V GENERAL DESCRIPTION FEATURES & BENEFITS The ALD194

More information

Common-Source Amplifiers

Common-Source Amplifiers Lab 2: Common-Source Amplifiers Introduction The common-source stage is the most basic amplifier stage encountered in CMOS analog circuits. Because of its very high input impedance, moderate-to-high gain,

More information

CSE 577 Spring Insoo Kim, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Penn State University

CSE 577 Spring Insoo Kim, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Penn State University CSE 577 Spring 2011 Basic Amplifiers and Differential Amplifier, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Penn State University Don t let the computer

More information

LSJ689. Linear Systems. Application Note. By Bob Cordell. Three Decades of Quality Through Innovation

LSJ689. Linear Systems. Application Note. By Bob Cordell. Three Decades of Quality Through Innovation Three Decades of Quality Through Innovation P-Channel Dual JFETs Make High-Performance Complementary Input Stages Possible Linear Systems Lower Current Noise Lower Bias Current Required LSJ689 Application

More information

Lecture 3 Switched-Capacitor Circuits Trevor Caldwell

Lecture 3 Switched-Capacitor Circuits Trevor Caldwell Advanced Analog Circuits Lecture 3 Switched-Capacitor Circuits Trevor Caldwell trevor.caldwell@analog.com Lecture Plan Date Lecture (Wednesday 2-4pm) Reference Homework 2017-01-11 1 MOD1 & MOD2 ST 2, 3,

More information

3-Stage Transimpedance Amplifier

3-Stage Transimpedance Amplifier 3-Stage Transimpedance Amplifier ECE 3400 - Dr. Maysam Ghovanloo Garren Boggs TEAM 11 Vasundhara Rawat December 11, 2015 Project Specifications and Design Approach Goal: Design a 3-stage transimpedance

More information

Rail to rail CMOS complementary input stage with only one active differential pair at a time

Rail to rail CMOS complementary input stage with only one active differential pair at a time LETTER IEICE Electronics Express, Vol.11, No.12, 1 5 Rail to rail CMOS complementary input stage with only one active differential pair at a time Maria Rodanas Valero 1a), Alejandro Roman-Loera 2, Jaime

More information

Design of a Folded Cascode Operational Amplifier in a 1.2 Micron Silicon-Carbide CMOS Process

Design of a Folded Cascode Operational Amplifier in a 1.2 Micron Silicon-Carbide CMOS Process University of Arkansas, Fayetteville ScholarWorks@UARK Electrical Engineering Undergraduate Honors Theses Electrical Engineering 5-2017 Design of a Folded Cascode Operational Amplifier in a 1.2 Micron

More information

Multistage Amplifiers

Multistage Amplifiers Multistage Amplifiers Single-stage transistor amplifiers are inadequate for meeting most design requirements for any of the four amplifier types (voltage, current, transconductance, and transresistance.)

More information

Tuesday, February 1st, 9:15 12:00. Snorre Aunet Nanoelectronics group Department of Informatics University of Oslo

Tuesday, February 1st, 9:15 12:00. Snorre Aunet Nanoelectronics group Department of Informatics University of Oslo Bandgap references, sampling switches Tuesday, February 1st, 9:15 12:00 Snorre Aunet (sa@ifi.uio.no) Nanoelectronics group Department of Informatics University of Oslo Outline Tuesday, February 1st 11.11

More information

Examining a New In-Amp Architecture for Communication Satellites

Examining a New In-Amp Architecture for Communication Satellites Examining a New In-Amp Architecture for Communication Satellites Introduction With more than 500 conventional sensors monitoring the condition and performance of various subsystems on a medium sized spacecraft,

More information

Design of a High Dynamic Range CMOS Variable Gain Amplifier for Wireless Sensor Networks

Design of a High Dynamic Range CMOS Variable Gain Amplifier for Wireless Sensor Networks University of Arkansas, Fayetteville ScholarWorks@UARK Theses and Dissertations 5-2012 Design of a High Dynamic Range CMOS Variable Gain Amplifier for Wireless Sensor Networks Yue Yu University of Arkansas,

More information

A Novel Design of Low Voltage,Wilson Current Mirror based Wideband Operational Transconductance Amplifier

A Novel Design of Low Voltage,Wilson Current Mirror based Wideband Operational Transconductance Amplifier A Novel Design of Low Voltage,Wilson Current Mirror based Wideband Operational Transconductance Amplifier Kehul A. Shah 1, N.M.Devashrayee 2 1(Associative Prof., Department of Electronics and Communication,

More information

Design and Layout of Two Stage High Bandwidth Operational Amplifier

Design and Layout of Two Stage High Bandwidth Operational Amplifier Design and Layout of Two Stage High Bandwidth Operational Amplifier Yasir Mahmood Qureshi Abstract This paper presents the design and layout of a two stage, high speed operational amplifiers using standard

More information

Atypical op amp consists of a differential input stage,

Atypical op amp consists of a differential input stage, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 6, JUNE 1998 915 Low-Voltage Class Buffers with Quiescent Current Control Fan You, S. H. K. Embabi, and Edgar Sánchez-Sinencio Abstract This paper presents

More information

Georgia Institute of Technology School of Electrical and Computer Engineering. Midterm Exam

Georgia Institute of Technology School of Electrical and Computer Engineering. Midterm Exam Georgia Institute of Technology School of Electrical and Computer Engineering Midterm Exam ECE-3400 Fall 2013 Tue, September 24, 2013 Duration: 80min First name Solutions Last name Solutions ID number

More information

A 2.6GHz/5.2GHz CMOS Voltage-Controlled Oscillator*

A 2.6GHz/5.2GHz CMOS Voltage-Controlled Oscillator* WP 23.6 A 2.6GHz/5.2GHz CMOS Voltage-Controlled Oscillator* Christopher Lam, Behzad Razavi University of California, Los Angeles, CA New wireless local area network (WLAN) standards have recently emerged

More information

Current Source/Sinks

Current Source/Sinks Motivation Current Source/Sinks Biasing is a very important step in MOS based analog design. A current sink and current source are two terminal components whose current at any instant of time is independent

More information

Low-voltage, High-precision Bandgap Current Reference Circuit

Low-voltage, High-precision Bandgap Current Reference Circuit Low-voltage, High-precision Bandgap Current Reference Circuit Chong Wei Keat, Harikrishnan Ramiah and Jeevan Kanesan Department of Electrical Engineering, Faculty of Engineering, University of Malaya,

More information

Experiment #7 MOSFET Dynamic Circuits II

Experiment #7 MOSFET Dynamic Circuits II Experiment #7 MOSFET Dynamic Circuits II Jonathan Roderick Introduction The previous experiment introduced the canonic cells for MOSFETs. The small signal model was presented and was used to discuss the

More information

A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage

A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage EEE 523 Advanced Analog Integrated Circuits Project Report Fuding Ge You are an engineer who is assigned the project to design

More information

A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions

A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions Brigham Young University BYU ScholarsArchive All Theses and Dissertations 2012-01-28 A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions Taylor Matt Waddel

More information

Field Effect Transistors (npn)

Field Effect Transistors (npn) Field Effect Transistors (npn) gate drain source FET 3 terminal device channel e - current from source to drain controlled by the electric field generated by the gate base collector emitter BJT 3 terminal

More information

IN RECENT years, low-dropout linear regulators (LDOs) are

IN RECENT years, low-dropout linear regulators (LDOs) are IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 52, NO. 9, SEPTEMBER 2005 563 Design of Low-Power Analog Drivers Based on Slew-Rate Enhancement Circuits for CMOS Low-Dropout Regulators

More information

DAT175: Topics in Electronic System Design

DAT175: Topics in Electronic System Design DAT175: Topics in Electronic System Design Analog Readout Circuitry for Hearing Aid in STM90nm 21 February 2010 Remzi Yagiz Mungan v1.10 1. Introduction In this project, the aim is to design an adjustable

More information

ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier

ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier Objective Design, simulate and test a two-stage operational amplifier Introduction Operational amplifiers (opamp) are essential components of

More information

Lecture 13 Date:

Lecture 13 Date: Lecture 13 Date: 9.09.016 Common Mode Rejection Ratio NonIdealities in Differential mplifier Common Mode Rejection Ratio (CMRR) Differential input amplifiers are devices/circuits that can input and amplify

More information

Operational Amplifier with Two-Stage Gain-Boost

Operational Amplifier with Two-Stage Gain-Boost Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization, Lisbon, Portugal, September 22-24, 2006 482 Operational Amplifier with Two-Stage Gain-Boost FRANZ SCHLÖGL

More information

BJT Circuits (MCQs of Moderate Complexity)

BJT Circuits (MCQs of Moderate Complexity) BJT Circuits (MCQs of Moderate Complexity) 1. The current ib through base of a silicon npn transistor is 1+0.1 cos (1000πt) ma. At 300K, the rπ in the small signal model of the transistor is i b B C r

More information

SP 22.3: A 12mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver

SP 22.3: A 12mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver SP 22.3: A 12mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver Arvin R. Shahani, Derek K. Shaeffer, Thomas H. Lee Stanford University, Stanford, CA At submicron channel lengths, CMOS is

More information

Operational Amplifiers

Operational Amplifiers Operational Amplifiers Table of contents 1. Design 1.1. The Differential Amplifier 1.2. Level Shifter 1.3. Power Amplifier 2. Characteristics 3. The Opamp without NFB 4. Linear Amplifiers 4.1. The Non-Inverting

More information

Single Supply, Rail to Rail Low Power FET-Input Op Amp AD820

Single Supply, Rail to Rail Low Power FET-Input Op Amp AD820 a FEATURES True Single Supply Operation Output Swings Rail-to-Rail Input Voltage Range Extends Below Ground Single Supply Capability from V to V Dual Supply Capability from. V to 8 V Excellent Load Drive

More information

Linear voltage to current conversion using submicron CMOS devices

Linear voltage to current conversion using submicron CMOS devices Brigham Young University BYU ScholarsArchive All Faculty Publications 2004-05-04 Linear voltage to current conversion using submicron CMOS devices David J. Comer comer.ee@byu.edu Donald Comer See next

More information

Design of a 5-V Compatible Rail-to-Rail Input/ Output Operational Amplifier in 3.3-V SOI CMOS for Wide Temperature Range Operation

Design of a 5-V Compatible Rail-to-Rail Input/ Output Operational Amplifier in 3.3-V SOI CMOS for Wide Temperature Range Operation University of Tennessee, Knoxville Trace: Tennessee Research and Creative Exchange Masters Theses Graduate School 12-2006 Design of a 5-V Compatible Rail-to-Rail Input/ Output Operational Amplifier in

More information

DESIGNING OF CURRENT MODE INSTRUMENTATION AMPLIFIER FOR BIO-SIGNAL USING 180NM CMOS TECHNOLOGY

DESIGNING OF CURRENT MODE INSTRUMENTATION AMPLIFIER FOR BIO-SIGNAL USING 180NM CMOS TECHNOLOGY DESIGNING OF CURRENT MODE INSTRUMENTATION AMPLIFIER FOR BIO-SIGNAL USING 180NM CMOS TECHNOLOGY GAYTRI GUPTA AMITY University Email: Gaytri.er@gmail.com Abstract In this paper we have describes the design

More information

Single Supply, Rail to Rail Low Power FET-Input Op Amp AD820

Single Supply, Rail to Rail Low Power FET-Input Op Amp AD820 a FEATURES True Single Supply Operation Output Swings Rail-to-Rail Input Voltage Range Extends Below Ground Single Supply Capability from + V to + V Dual Supply Capability from. V to 8 V Excellent Load

More information

55:041 Electronic Circuits

55:041 Electronic Circuits 55:041 Electronic Circuits Mosfet Review Sections of Chapter 3 &4 A. Kruger Mosfet Review, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width 1 10-6 m or less Thickness 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor

More information

IMPROVED CURRENT MIRROR OUTPUT PERFORMANCE BY USING GRADED-CHANNEL SOI NMOSFETS

IMPROVED CURRENT MIRROR OUTPUT PERFORMANCE BY USING GRADED-CHANNEL SOI NMOSFETS IMPROVED CURRENT MIRROR OUTPUT PERFORMANCE BY USING GRADED-CHANNEL SOI NMOSFETS Marcelo Antonio Pavanello *, João Antonio Martino and Denis Flandre 1 Laboratório de Sistemas Integráveis Escola Politécnica

More information

An introduction to Depletion-mode MOSFETs By Linden Harrison

An introduction to Depletion-mode MOSFETs By Linden Harrison An introduction to Depletion-mode MOSFETs By Linden Harrison Since the mid-nineteen seventies the enhancement-mode MOSFET has been the subject of almost continuous global research, development, and refinement

More information

Course Number Section. Electronics I ELEC 311 BB Examination Date Time # of pages. Final August 12, 2005 Three hours 3 Instructor

Course Number Section. Electronics I ELEC 311 BB Examination Date Time # of pages. Final August 12, 2005 Three hours 3 Instructor Course Number Section Electronics ELEC 311 BB Examination Date Time # of pages Final August 12, 2005 Three hours 3 nstructor Dr. R. Raut M aterials allowed: No Yes X (Please specify) Calculators allowed:

More information

A Low Voltage, Low Quiescent Current, Low Drop-out Regulator

A Low Voltage, Low Quiescent Current, Low Drop-out Regulator Rincon-Mora and Allen 1 A Low Voltage, Low Quiescent Current, Low Drop-out Regulator Gabriel Alfonso Rincon-Mora and Phillip E. Allen School of Electrical and Computer Engineering Georgia Institute of

More information

Analysis and Design of Analog Integrated Circuits Lecture 20. Advanced Opamp Topologies (Part II)

Analysis and Design of Analog Integrated Circuits Lecture 20. Advanced Opamp Topologies (Part II) Analysis and Design of Analog Integrated Circuits Lecture 20 Advanced Opamp Topologies (Part II) Michael H. Perrott April 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Outline of Lecture

More information

Q.1: Power factor of a linear circuit is defined as the:

Q.1: Power factor of a linear circuit is defined as the: Q.1: Power factor of a linear circuit is defined as the: a. Ratio of real power to reactive power b. Ratio of real power to apparent power c. Ratio of reactive power to apparent power d. Ratio of resistance

More information