# 6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain- Bandwidth Issue for Broadband Amplifiers

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1 6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain- Bandwidth Issue for Broadband Amplifiers Massachusetts Institute of Technology February 17, 2005 Copyright 2005 by Hae-Seung Lee and Michael H. Perrott

2 Basics of MOS Large Signal Behavior (Qualitative) Triode I D V GS S G D V DS=0 Overall I-V Characteristic C channel = C ox (V GS -V T ) I D Pinch-off I D Pinch-off Saturation V GS S G D V D = V Triode Saturation I D V V DS V GS S G D V D > V

3 Basics of MOS Large Signal Behavior (Quantitative) V GS Triode G S D C channel = C ox (V GS -V T ) I D V DS=0 I D = µ n C ox W L (V GS - V T - V DS /2)V DS I D for V DS << V GS - V T µ n C ox W L (V GS - V T )V DS Pinch-off I D V GS S G D V D = V V = V GS -V T 2I V = D L µ n C ox W Saturation I D V GS S G D V D > V 1 I D = µ n C W ox (V 2 GS -V T ) 2 (1+λV DS ) L (where λ corresponds to channel length modulation)

4 Analysis of Amplifier Behavior Typically focus on small signal behavior - Work with a linearized model such as hybrid-π To do small signal analysis: Small Signal Analysis Steps I D R D 1) Solve for bias current I d v in V bias R G R S v out 2) Calculate small signal parameters (such as g m, r o ) 3) Solve for small signal response using transistor hybrid-π small signal model

5 MOS DC Small Signal Model Assume transistor in saturation: I D R D R D R G R G v gs g m v gs -g mb v s r o R S v s R S g m = µ n C ox (W/L)(V GS - V T )(1 + λv DS ) = 2µ n C ox (W/L)I D (assuming λv DS << 1) γg m g mb = where γ = 2 2 Φ p + V SB In practice: g mb = g m /5 to g m /3 2qε s N A C ox r o = 1 λi D

6 Capacitors For MOS Device In Saturation Top View Side View I D V GS E G S D W C jsb C ov S C gc C cb C ov D C jdb V D > V B L D L L D E E L junction bottom wall cap (per area) junction sidewall cap (per length) source to bulk cap: C jsb = C j (0) C jsw (0) WE V SB Φ B 1 + V SB Φ B (W + 2E) drain to bulk cap: C jdb = C j (0) C jsw (0) WE V DB Φ B 1 + V DB Φ B (W + 2E) overlap cap: C ov = WL D C ox + WC fringe 2 gate to channel cap: C gc = C ox W(L-2L D ) 3 (make 2W for "4 sided" perimeter in some cases) channel to bulk cap: C cb - ignore in this class

7 MOS AC Small Signal Model (Device in Saturation) R D R G R G I D R D v gs C gd C gs g m v gs -g mb v s r o C db C sb R S v s R S 2 C gs = C gc + C ov = C ox W(L-2L D ) + C 3 ov C gd = C ov C sb = C jsb C db = C jdb (area + perimeter junction capacitance) (area + perimeter junction capacitance)

8 Wiring Parasitics Capacitance - Gate: cap from poly to substrate and metal layers - Drain and source: cap from metal routing path to substrate and other metal layers Resistance - Gate: poly gate has resistance (reduce by silicide) long metal lines can add resistance - Drain and source: some resistance in diffusion region (reduce by silicide), and from routing long metal lines Inductance - Gate: poly gate has negligible inductance, but long wires can add inductance - Drain and source: becomes an issue for long wires Extract these parasitics from circuit layout

9 Frequency Performance of a CMOS Device Two figures of merit in common use - f t : frequency for which current gain is unity - f max : frequency for which power gain is unity Common intuition about f t - Gain, bandwidth product is conserved - We will see that MOS devices have an f t that is a function of bias This effect strongly impacts high frequency amplifier topology selection

10 Derivation of f t for MOS Device in Saturation i d R LARGE I D +i d i in v gs C gd C gs g m v gs -g mb v s r o C db V bias i in C sb Assumption is that input is current, output of device is short circuited to a supply voltage - Note that voltage bias is required at gate The calculated value of f t is a function of this bias voltage

11 Derivation of f t for MOS Device in Saturation i d R LARGE I D +i d i in v gs C gd C gs g m v gs -g mb v s r o C db V bias i in C sb

12 Derivation of f t for MOS Device in Saturation i d i in slope = -20 db/dec 1 f t f

13 Why is f t a Function of Voltage Bias? f t is a ratio of g m to gate capacitance - g m is a function of gate bias, while gate cap is not (in strong inversion) First order relationship between g m and gate bias: - The larger the gate bias, the higher the value for f t Alternately, f t is a function of current density - So f t maximized at max current density (and minimum L)

14 Unity Power Gain Frequency f max From pages (2 nd ed.) (1 st ed.) of text book for derivation on f max r g is the series parasitic gate resistance f max can be much higher than f T : make gate resistance small (by careful layout) Output capacitance has no effect (can be tuned out by inductor)

15 Speed of NMOS Versus PMOS Devices NMOS devices have much higher mobility than PMOS devices (in typical bulk CMOS processes) - NMOS devices provide approximately 2.5 x g m for a given amount of capacitance and gate bias voltage - Also, NMOS devices provide approximately 2.5 x I d for a given amount of capacitance and gate bias voltage

16 Integrated Passive Components for RF Circuits We will only consider passive components appropriate for RF use High Q, low parasitics, and good linearity are generally desired (bias circuit is an exception) Well resistors, diffused resistors, poly-n+ capacitors even poly-poly capacitors do not perform very well in these regards

17 Polysilicon Resistors Use unsilicided polysilicon to create resistor A A R poly B B Key parameters - Resistance (usually Ohms per square) - Parasitic capacitance (usually small) Appropriate for high speed amplifiers - Linearity (excellent) - Accuracy (usually can be set within ± 15%)

18 MOS Resistors Bias a MOS device in its triode region A R ds W/L B A B High resistance values can be achieved in a small area (MegaOhms within tens of square microns) Parasitic capacitance is large (gate capacitance!) Resistance is quite nonlinear - Appropriate for small swing circuits or DC (bias) circuits

19 High Density Capacitors (Biasing, Decoupling) MOS devices offer the highest capacitance per unit area - Voltage must be high enough to invert the channel A A C 1 =C ox WL W/L Key parameters - Capacitance value Raw cap value from MOS device is about ff/µ 2 for 0.18u CMOS - Q (i.e., amount of series resistance) Maximized with minimum L (tradeoff with area efficiency)

20 MOS Capacitors, Cnt d Putting NMOS capacitor in NWell allows operation at lower voltage C OX C + V NMOS in N-well NMOS on substrate - poly C OV V T V n+ n+ Nwell The non-linearity is often exploited in VCO designs as varactors

21 High Q Capacitors (Signal Path) Lateral metal capacitors offer high Q and reasonably large capacitance per unit area - Stack many levels of metal on top of each other (best layers are the top ones), via them at maximum density A A C 1 B - B Accuracy often better than ±10% - Parasitic cap is symmetric, typically less than 10% of cap value

22 Stacked Lateral Flux Capacitor Example: C = 1.5 ff/µm 2 for 0.24µm process with 7 T metals, L min = W min = 0.24µm, t metal = 0.53µm -See Capacity Limits and Matching Properties of Integrated Capacitors, Aparicio et. al., JSSC, Mar 2002

23 Fractal Capacitor Maximizes perimeter area: up to 10x increase in unit capacitance Limited by lithography Figure by. See A. Shanhani et. al., A 12 mw, Wdie Dynamic Range CMOS Fron-End Circuit for Portable GPS Receiver, Digest of Technical Papers, ISSCC 1997

24 Spiral Inductors Create integrated inductor using spiral shape on top level metals (may also want a patterned ground shield) A A B L m B - Key parameters are Q (< 10), L (1-10 nh), self resonant freq. - Usually implemented in top metal layers to minimize series resistance, coupling to substrate - See using Mohan et. al, Simple, Accurate Expressions for Planar Spiral Inductances, JSSC, Oct, 1999, pp Verify inductor parameters (L, Q, etc.) using ASITIC

25 Bondwire Inductors Used to bond from the package to die - Can be used to advantage Adjoining pins package die From board L bondwire To chip circuits C pin C bonding_pad Properties - Inductance ( 1 nh/mm usually achieve 1-5 nh) - Inductance value is difficult to control (chip-package alignment, bondwire height, etc.) - Q (much higher than spiral inductors typically > 40)

26 Integrated Transformers Utilize magnetic coupling between adjoining wires A B C par1 L 1 k L 2 C D C C par2 D Key parameters - L (self inductance for primary and secondary A B windings) - k (coupling coefficient between primary and secondary) Design ASITIC, other CAD packages

27 High Speed Transformer Example A T-Coil Network A T-coil consists of a center-tapped inductor with mutual coupling between each inductor half B L 2 C B X k L 1 X A A B Used for bandwidth enhancement - See S. Galal, B. Ravazi, 10 Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18u CMOS, ISSCC 2003, pp and Broadband ESD Protection, pp

29 High Frequency, Broadband Amplifiers The first thing that you typically do to the input signal is amplify it package Connector Adjoining pins Controlled Impedance PCB trace die Driving Source On-Chip Z 1 Delay = x Characteristic Impedance = Z o L 1 Amp V out V Transmission Line in C 1 C 2 R L V L Function - Boosts signal levels to acceptable values - Provides reverse isolation Key performance parameters - Gain, bandwidth, noise, linearity

30 Gain-bandwidth Trade-off Common-source amplifier example V dd R L vo v in V bias C tot C tot : total capacitance at output node DC gain 3 dbbandwidth Gain-bandwidth

31 Gain-bandwidth Trade-off Common-source amplifier example R L =R L1 R L =R L3 R L =R L3 Given the origin pole g m /C tot, higher bandwidth is achieved only at the expense of gain The origin pole g m /C tot must be improved for better GB

32 Gain-bandwidth Improvement How do we improve g m /C tot? Assume that amplifier is loaded by an identical amplifier and fixed wiring capacitance is negligible Since and To achieve maximum GB in a given technology, use minimum gate length, bias the transistor at maximum When velocity saturation is reached, higher does not yield higher g m In case fixed wiring capacitance is large, power consumption must be also considered

33 Gain-bandwidth Observations Constant gain-bandwidth is simply the result of singlepole role off it s not fundamental! It implies a single-pole frequency response may not be the best for obtaining gain and bandwidth simultaneously Single-pole role off is necessary for some circuits, e.g. for stability, but not for broad-band amplifiers

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