6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain- Bandwidth Issue for Broadband Amplifiers

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain- Bandwidth Issue for Broadband Amplifiers"

Transcription

1 6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain- Bandwidth Issue for Broadband Amplifiers Massachusetts Institute of Technology February 17, 2005 Copyright 2005 by Hae-Seung Lee and Michael H. Perrott

2 Basics of MOS Large Signal Behavior (Qualitative) Triode I D V GS S G D V DS=0 Overall I-V Characteristic C channel = C ox (V GS -V T ) I D Pinch-off I D Pinch-off Saturation V GS S G D V D = V Triode Saturation I D V V DS V GS S G D V D > V

3 Basics of MOS Large Signal Behavior (Quantitative) V GS Triode G S D C channel = C ox (V GS -V T ) I D V DS=0 I D = µ n C ox W L (V GS - V T - V DS /2)V DS I D for V DS << V GS - V T µ n C ox W L (V GS - V T )V DS Pinch-off I D V GS S G D V D = V V = V GS -V T 2I V = D L µ n C ox W Saturation I D V GS S G D V D > V 1 I D = µ n C W ox (V 2 GS -V T ) 2 (1+λV DS ) L (where λ corresponds to channel length modulation)

4 Analysis of Amplifier Behavior Typically focus on small signal behavior - Work with a linearized model such as hybrid-π To do small signal analysis: Small Signal Analysis Steps I D R D 1) Solve for bias current I d v in V bias R G R S v out 2) Calculate small signal parameters (such as g m, r o ) 3) Solve for small signal response using transistor hybrid-π small signal model

5 MOS DC Small Signal Model Assume transistor in saturation: I D R D R D R G R G v gs g m v gs -g mb v s r o R S v s R S g m = µ n C ox (W/L)(V GS - V T )(1 + λv DS ) = 2µ n C ox (W/L)I D (assuming λv DS << 1) γg m g mb = where γ = 2 2 Φ p + V SB In practice: g mb = g m /5 to g m /3 2qε s N A C ox r o = 1 λi D

6 Capacitors For MOS Device In Saturation Top View Side View I D V GS E G S D W C jsb C ov S C gc C cb C ov D C jdb V D > V B L D L L D E E L junction bottom wall cap (per area) junction sidewall cap (per length) source to bulk cap: C jsb = C j (0) C jsw (0) WE V SB Φ B 1 + V SB Φ B (W + 2E) drain to bulk cap: C jdb = C j (0) C jsw (0) WE V DB Φ B 1 + V DB Φ B (W + 2E) overlap cap: C ov = WL D C ox + WC fringe 2 gate to channel cap: C gc = C ox W(L-2L D ) 3 (make 2W for "4 sided" perimeter in some cases) channel to bulk cap: C cb - ignore in this class

7 MOS AC Small Signal Model (Device in Saturation) R D R G R G I D R D v gs C gd C gs g m v gs -g mb v s r o C db C sb R S v s R S 2 C gs = C gc + C ov = C ox W(L-2L D ) + C 3 ov C gd = C ov C sb = C jsb C db = C jdb (area + perimeter junction capacitance) (area + perimeter junction capacitance)

8 Wiring Parasitics Capacitance - Gate: cap from poly to substrate and metal layers - Drain and source: cap from metal routing path to substrate and other metal layers Resistance - Gate: poly gate has resistance (reduce by silicide) long metal lines can add resistance - Drain and source: some resistance in diffusion region (reduce by silicide), and from routing long metal lines Inductance - Gate: poly gate has negligible inductance, but long wires can add inductance - Drain and source: becomes an issue for long wires Extract these parasitics from circuit layout

9 Frequency Performance of a CMOS Device Two figures of merit in common use - f t : frequency for which current gain is unity - f max : frequency for which power gain is unity Common intuition about f t - Gain, bandwidth product is conserved - We will see that MOS devices have an f t that is a function of bias This effect strongly impacts high frequency amplifier topology selection

10 Derivation of f t for MOS Device in Saturation i d R LARGE I D +i d i in v gs C gd C gs g m v gs -g mb v s r o C db V bias i in C sb Assumption is that input is current, output of device is short circuited to a supply voltage - Note that voltage bias is required at gate The calculated value of f t is a function of this bias voltage

11 Derivation of f t for MOS Device in Saturation i d R LARGE I D +i d i in v gs C gd C gs g m v gs -g mb v s r o C db V bias i in C sb

12 Derivation of f t for MOS Device in Saturation i d i in slope = -20 db/dec 1 f t f

13 Why is f t a Function of Voltage Bias? f t is a ratio of g m to gate capacitance - g m is a function of gate bias, while gate cap is not (in strong inversion) First order relationship between g m and gate bias: - The larger the gate bias, the higher the value for f t Alternately, f t is a function of current density - So f t maximized at max current density (and minimum L)

14 Unity Power Gain Frequency f max From pages (2 nd ed.) (1 st ed.) of text book for derivation on f max r g is the series parasitic gate resistance f max can be much higher than f T : make gate resistance small (by careful layout) Output capacitance has no effect (can be tuned out by inductor)

15 Speed of NMOS Versus PMOS Devices NMOS devices have much higher mobility than PMOS devices (in typical bulk CMOS processes) - NMOS devices provide approximately 2.5 x g m for a given amount of capacitance and gate bias voltage - Also, NMOS devices provide approximately 2.5 x I d for a given amount of capacitance and gate bias voltage

16 Integrated Passive Components for RF Circuits We will only consider passive components appropriate for RF use High Q, low parasitics, and good linearity are generally desired (bias circuit is an exception) Well resistors, diffused resistors, poly-n+ capacitors even poly-poly capacitors do not perform very well in these regards

17 Polysilicon Resistors Use unsilicided polysilicon to create resistor A A R poly B B Key parameters - Resistance (usually Ohms per square) - Parasitic capacitance (usually small) Appropriate for high speed amplifiers - Linearity (excellent) - Accuracy (usually can be set within ± 15%)

18 MOS Resistors Bias a MOS device in its triode region A R ds W/L B A B High resistance values can be achieved in a small area (MegaOhms within tens of square microns) Parasitic capacitance is large (gate capacitance!) Resistance is quite nonlinear - Appropriate for small swing circuits or DC (bias) circuits

19 High Density Capacitors (Biasing, Decoupling) MOS devices offer the highest capacitance per unit area - Voltage must be high enough to invert the channel A A C 1 =C ox WL W/L Key parameters - Capacitance value Raw cap value from MOS device is about ff/µ 2 for 0.18u CMOS - Q (i.e., amount of series resistance) Maximized with minimum L (tradeoff with area efficiency)

20 MOS Capacitors, Cnt d Putting NMOS capacitor in NWell allows operation at lower voltage C OX C + V NMOS in N-well NMOS on substrate - poly C OV V T V n+ n+ Nwell The non-linearity is often exploited in VCO designs as varactors

21 High Q Capacitors (Signal Path) Lateral metal capacitors offer high Q and reasonably large capacitance per unit area - Stack many levels of metal on top of each other (best layers are the top ones), via them at maximum density A A C 1 B - B Accuracy often better than ±10% - Parasitic cap is symmetric, typically less than 10% of cap value

22 Stacked Lateral Flux Capacitor Example: C = 1.5 ff/µm 2 for 0.24µm process with 7 T metals, L min = W min = 0.24µm, t metal = 0.53µm -See Capacity Limits and Matching Properties of Integrated Capacitors, Aparicio et. al., JSSC, Mar 2002

23 Fractal Capacitor Maximizes perimeter area: up to 10x increase in unit capacitance Limited by lithography Figure by. See A. Shanhani et. al., A 12 mw, Wdie Dynamic Range CMOS Fron-End Circuit for Portable GPS Receiver, Digest of Technical Papers, ISSCC 1997

24 Spiral Inductors Create integrated inductor using spiral shape on top level metals (may also want a patterned ground shield) A A B L m B - Key parameters are Q (< 10), L (1-10 nh), self resonant freq. - Usually implemented in top metal layers to minimize series resistance, coupling to substrate - See using Mohan et. al, Simple, Accurate Expressions for Planar Spiral Inductances, JSSC, Oct, 1999, pp Verify inductor parameters (L, Q, etc.) using ASITIC

25 Bondwire Inductors Used to bond from the package to die - Can be used to advantage Adjoining pins package die From board L bondwire To chip circuits C pin C bonding_pad Properties - Inductance ( 1 nh/mm usually achieve 1-5 nh) - Inductance value is difficult to control (chip-package alignment, bondwire height, etc.) - Q (much higher than spiral inductors typically > 40)

26 Integrated Transformers Utilize magnetic coupling between adjoining wires A B C par1 L 1 k L 2 C D C C par2 D Key parameters - L (self inductance for primary and secondary A B windings) - k (coupling coefficient between primary and secondary) Design ASITIC, other CAD packages

27 High Speed Transformer Example A T-Coil Network A T-coil consists of a center-tapped inductor with mutual coupling between each inductor half B L 2 C B X k L 1 X A A B Used for bandwidth enhancement - See S. Galal, B. Ravazi, 10 Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18u CMOS, ISSCC 2003, pp and Broadband ESD Protection, pp

28 Broadband Amplifiers

29 High Frequency, Broadband Amplifiers The first thing that you typically do to the input signal is amplify it package Connector Adjoining pins Controlled Impedance PCB trace die Driving Source On-Chip Z 1 Delay = x Characteristic Impedance = Z o L 1 Amp V out V Transmission Line in C 1 C 2 R L V L Function - Boosts signal levels to acceptable values - Provides reverse isolation Key performance parameters - Gain, bandwidth, noise, linearity

30 Gain-bandwidth Trade-off Common-source amplifier example V dd R L vo v in V bias C tot C tot : total capacitance at output node DC gain 3 dbbandwidth Gain-bandwidth

31 Gain-bandwidth Trade-off Common-source amplifier example R L =R L1 R L =R L3 R L =R L3 Given the origin pole g m /C tot, higher bandwidth is achieved only at the expense of gain The origin pole g m /C tot must be improved for better GB

32 Gain-bandwidth Improvement How do we improve g m /C tot? Assume that amplifier is loaded by an identical amplifier and fixed wiring capacitance is negligible Since and To achieve maximum GB in a given technology, use minimum gate length, bias the transistor at maximum When velocity saturation is reached, higher does not yield higher g m In case fixed wiring capacitance is large, power consumption must be also considered

33 Gain-bandwidth Observations Constant gain-bandwidth is simply the result of singlepole role off it s not fundamental! It implies a single-pole frequency response may not be the best for obtaining gain and bandwidth simultaneously Single-pole role off is necessary for some circuits, e.g. for stability, but not for broad-band amplifiers

6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers

6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers 6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott Broadband Communication

More information

Lecture 16: MOS Transistor models: Linear models, SPICE models. Context. In the last lecture, we discussed the MOS transistor, and

Lecture 16: MOS Transistor models: Linear models, SPICE models. Context. In the last lecture, we discussed the MOS transistor, and Lecture 16: MOS Transistor models: Linear models, SPICE models Context In the last lecture, we discussed the MOS transistor, and added a correction due to the changing depletion region, called the body

More information

6.776 High Speed Communication Circuits and Systems Lecture 14 Voltage Controlled Oscillators

6.776 High Speed Communication Circuits and Systems Lecture 14 Voltage Controlled Oscillators 6.776 High Speed Communication Circuits and Systems Lecture 14 Voltage Controlled Oscillators Massachusetts Institute of Technology March 29, 2005 Copyright 2005 by Michael H. Perrott VCO Design for Narrowband

More information

MOS Field Effect Transistors

MOS Field Effect Transistors MOS Field Effect Transistors A gate contact gate interconnect n polysilicon gate source contacts W active area (thin oxide area) polysilicon gate contact metal interconnect drain contacts A bulk contact

More information

6.976 High Speed Communication Circuits and Systems Lecture 11 Voltage Controlled Oscillators

6.976 High Speed Communication Circuits and Systems Lecture 11 Voltage Controlled Oscillators 6.976 High Speed Communication Circuits and Systems Lecture 11 Voltage Controlled Oscillators Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott VCO Design for Wireless

More information

Lecture 20: Passive Mixers

Lecture 20: Passive Mixers EECS 142 Lecture 20: Passive Mixers Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California, Berkeley EECS 142 Lecture 20 p.

More information

Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier

Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in double-ended

More information

High Speed Communication Circuits and Systems Lecture 11 Voltage Controlled Oscillators

High Speed Communication Circuits and Systems Lecture 11 Voltage Controlled Oscillators High Speed Communication Circuits and Systems Lecture 11 Voltage Controlled Oscillators Michael H. Perrott March 10, 2004 Copyright 2004 by Michael H. Perrott All rights reserved. 1 VCO Design for Wireless

More information

Chapter 4. CMOS Cascode Amplifiers. 4.1 Introduction. 4.2 CMOS Cascode Amplifiers

Chapter 4. CMOS Cascode Amplifiers. 4.1 Introduction. 4.2 CMOS Cascode Amplifiers Chapter 4 CMOS Cascode Amplifiers 4.1 Introduction A single stage CMOS amplifier cannot give desired dc voltage gain, output resistance and transconductance. The voltage gain can be made to attain higher

More information

SP 22.3: A 12mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver

SP 22.3: A 12mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver SP 22.3: A 12mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver Arvin R. Shahani, Derek K. Shaeffer, Thomas H. Lee Stanford University, Stanford, CA At submicron channel lengths, CMOS is

More information

ISSCC 2006 / SESSION 11 / RF BUILDING BLOCKS AND PLLS / 11.9

ISSCC 2006 / SESSION 11 / RF BUILDING BLOCKS AND PLLS / 11.9 ISSCC 2006 / SESSION 11 / RF BUILDING BLOCKS AND PLLS / 11.9 11.9 A Single-Chip Linear CMOS Power Amplifier for 2.4 GHz WLAN Jongchan Kang 1, Ali Hajimiri 2, Bumman Kim 1 1 Pohang University of Science

More information

Basic Fabrication Steps

Basic Fabrication Steps Basic Fabrication Steps and Layout Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author Outline Fabrication steps Transistor structures Transistor

More information

Advanced Operational Amplifiers

Advanced Operational Amplifiers IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage

More information

Common-Source Amplifiers

Common-Source Amplifiers Lab 2: Common-Source Amplifiers Introduction The common-source stage is the most basic amplifier stage encountered in CMOS analog circuits. Because of its very high input impedance, moderate-to-high gain,

More information

95GHz Receiver with Fundamental Frequency VCO and Static Frequency Divider in 65nm Digital CMOS

95GHz Receiver with Fundamental Frequency VCO and Static Frequency Divider in 65nm Digital CMOS 95GHz Receiver with Fundamental Frequency VCO and Static Frequency Divider in 65nm Digital CMOS Ekaterina Laskin, Mehdi Khanpour, Ricardo Aroca, Keith W. Tang, Patrice Garcia 1, Sorin P. Voinigescu University

More information

Analysis and Design of Analog Integrated Circuits Lecture 20. Advanced Opamp Topologies (Part II)

Analysis and Design of Analog Integrated Circuits Lecture 20. Advanced Opamp Topologies (Part II) Analysis and Design of Analog Integrated Circuits Lecture 20 Advanced Opamp Topologies (Part II) Michael H. Perrott April 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Outline of Lecture

More information

COMPARISON OF THE MOSFET AND THE BJT:

COMPARISON OF THE MOSFET AND THE BJT: COMPARISON OF THE MOSFET AND THE BJT: In this section we present a comparison of the characteristics of the two major electronic devices: the MOSFET and the BJT. To facilitate this comparison, typical

More information

Design of a Low Power 5GHz CMOS Radio Frequency Low Noise Amplifier Rakshith Venkatesh

Design of a Low Power 5GHz CMOS Radio Frequency Low Noise Amplifier Rakshith Venkatesh Design of a Low Power 5GHz CMOS Radio Frequency Low Noise Amplifier Rakshith Venkatesh Abstract A 5GHz low power consumption LNA has been designed here for the receiver front end using 90nm CMOS technology.

More information

Fully Integrated Low Phase Noise LC VCO. Desired Characteristics of VCOs

Fully Integrated Low Phase Noise LC VCO. Desired Characteristics of VCOs Fully Integrated ow Phase Noise C VCO AGENDA Comparison with other types of VCOs. Analysis of two common C VCO topologies. Design procedure for the cross-coupled C VCO. Phase noise reduction techniques.

More information

INTRODUCTION TO ELECTRONICS EHB 222E

INTRODUCTION TO ELECTRONICS EHB 222E INTRODUCTION TO ELECTRONICS EHB 222E MOS Field Effect Transistors (MOSFETS II) MOSFETS 1/ INTRODUCTION TO ELECTRONICS 1 MOSFETS Amplifiers Cut off when v GS < V t v DS decreases starting point A, once

More information

CHAPTER 4 ULTRA WIDE BAND LOW NOISE AMPLIFIER DESIGN

CHAPTER 4 ULTRA WIDE BAND LOW NOISE AMPLIFIER DESIGN 93 CHAPTER 4 ULTRA WIDE BAND LOW NOISE AMPLIFIER DESIGN 4.1 INTRODUCTION Ultra Wide Band (UWB) system is capable of transmitting data over a wide spectrum of frequency bands with low power and high data

More information

Design and power optimization of CMOS RF blocks operating in the moderate inversion region

Design and power optimization of CMOS RF blocks operating in the moderate inversion region Design and power optimization of CMOS RF blocks operating in the moderate inversion region Leonardo Barboni, Rafaella Fiorelli, Fernando Silveira Instituto de Ingeniería Eléctrica Facultad de Ingeniería

More information

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 Lecture 5: Termination, TX Driver, & Multiplexer Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements

More information

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor

More information

EE105 Fall 2015 Microelectronic Devices and Circuits

EE105 Fall 2015 Microelectronic Devices and Circuits EE105 Fall 2015 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 11-1 Transistor Operating Mode in Amplifiers Transistors are biased in flat part of

More information

55:041 Electronic Circuits

55:041 Electronic Circuits 55:041 Electronic Circuits Mosfet Review Sections of Chapter 3 &4 A. Kruger Mosfet Review, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width 1 10-6 m or less Thickness 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor

More information

DESIGN OF 3 TO 5 GHz CMOS LOW NOISE AMPLIFIER FOR ULTRA-WIDEBAND (UWB) SYSTEM

DESIGN OF 3 TO 5 GHz CMOS LOW NOISE AMPLIFIER FOR ULTRA-WIDEBAND (UWB) SYSTEM Progress In Electromagnetics Research C, Vol. 9, 25 34, 2009 DESIGN OF 3 TO 5 GHz CMOS LOW NOISE AMPLIFIER FOR ULTRA-WIDEBAND (UWB) SYSTEM S.-K. Wong and F. Kung Faculty of Engineering Multimedia University

More information

Active Technology for Communication Circuits

Active Technology for Communication Circuits EECS 242: Active Technology for Communication Circuits UC Berkeley EECS 242 Copyright Prof. Ali M Niknejad Outline Comparison of technology choices for communication circuits Si npn, Si NMOS, SiGe HBT,

More information

55:041 Electronic Circuits

55:041 Electronic Circuits 55:041 Electronic Circuits MOSFETs Sections of Chapter 3 &4 A. Kruger MOSFETs, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width = 1 10-6 m or less Thickness = 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor

More information

Chapter 13: Introduction to Switched- Capacitor Circuits

Chapter 13: Introduction to Switched- Capacitor Circuits Chapter 13: Introduction to Switched- Capacitor Circuits 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4 Switched-Capacitor Integrator 13.5 Switched-Capacitor

More information

Design and Simulation of Voltage-Mode and Current-Mode Class-D Power Amplifiers for 2.4 GHz Applications

Design and Simulation of Voltage-Mode and Current-Mode Class-D Power Amplifiers for 2.4 GHz Applications Design and Simulation of Voltage-Mode and Current-Mode Class-D Power Amplifiers for 2.4 GHz Applications Armindo António Barão da Silva Pontes Abstract This paper presents the design and simulations of

More information

Design cycle for MEMS

Design cycle for MEMS Design cycle for MEMS Design cycle for ICs IC Process Selection nmos CMOS BiCMOS ECL for logic for I/O and driver circuit for critical high speed parts of the system The Real Estate of a Wafer MOS Transistor

More information

Case Study: Osc2 Design of a C-Band VCO

Case Study: Osc2 Design of a C-Band VCO MICROWAVE AND RF DESIGN Case Study: Osc2 Design of a C-Band VCO Presented by Michael Steer Reading: Chapter 20, 20.5,6 Index: CS_Osc2 Based on material in Microwave and RF Design: A Systems Approach, 2

More information

Metal-Oxide-Silicon (MOS) devices PMOS. n-type

Metal-Oxide-Silicon (MOS) devices PMOS. n-type Metal-Oxide-Silicon (MOS devices Principle of MOS Field Effect Transistor transistor operation Metal (poly gate on oxide between source and drain Source and drain implants of opposite type to substrate.

More information

Week 7: Common-Collector Amplifier, MOS Field Effect Transistor

Week 7: Common-Collector Amplifier, MOS Field Effect Transistor EE 2110A Electronic Circuits Week 7: Common-Collector Amplifier, MOS Field Effect Transistor ecture 07-1 Topics to coer Common-Collector Amplifier MOS Field Effect Transistor Physical Operation and I-V

More information

A 2.6GHz/5.2GHz CMOS Voltage-Controlled Oscillator*

A 2.6GHz/5.2GHz CMOS Voltage-Controlled Oscillator* WP 23.6 A 2.6GHz/5.2GHz CMOS Voltage-Controlled Oscillator* Christopher Lam, Behzad Razavi University of California, Los Angeles, CA New wireless local area network (WLAN) standards have recently emerged

More information

Experiment #7 MOSFET Dynamic Circuits II

Experiment #7 MOSFET Dynamic Circuits II Experiment #7 MOSFET Dynamic Circuits II Jonathan Roderick Introduction The previous experiment introduced the canonic cells for MOSFETs. The small signal model was presented and was used to discuss the

More information

Integrated Circuit Amplifiers. Comparison of MOSFETs and BJTs

Integrated Circuit Amplifiers. Comparison of MOSFETs and BJTs Integrated Circuit Amplifiers Comparison of MOSFETs and BJTs 17 Typical CMOS Device Parameters 0.8 µm 0.25 µm 0.13 µm Parameter NMOS PMOS NMOS PMOS NMOS PMOS t ox (nm) 15 15 6 6 2.7 2.7 C ox (ff/µm 2 )

More information

BJT Amplifier. Superposition principle (linear amplifier)

BJT Amplifier. Superposition principle (linear amplifier) BJT Amplifier Two types analysis DC analysis Applied DC voltage source AC analysis Time varying signal source Superposition principle (linear amplifier) The response of a linear amplifier circuit excited

More information

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic

More information

A 20GHz Class-C VCO Using Noise Sensitivity Mitigation Technique

A 20GHz Class-C VCO Using Noise Sensitivity Mitigation Technique Matsuzawa Lab. Matsuzawa & Okada Lab. Tokyo Institute of Technology A 20GHz Class-C VCO Using Noise Sensitivity Mitigation Technique Kento Kimura, Kenichi Okada and Akira Matsuzawa (WE2C-2) Matsuzawa &

More information

EE105 Fall 2015 Microelectronic Devices and Circuits: MOSFET Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)

EE105 Fall 2015 Microelectronic Devices and Circuits: MOSFET Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH) EE105 Fall 2015 Microelectronic Devices and Circuits: MOSFET Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 7-1 Simplest Model of MOSFET (from EE16B) 7-2 CMOS Inverter 7-3 CMOS NAND

More information

ISSCC 2003 / SESSION 10 / HIGH SPEED BUILDING BLOCKS / PAPER 10.8

ISSCC 2003 / SESSION 10 / HIGH SPEED BUILDING BLOCKS / PAPER 10.8 ISSCC 2003 / SESSION 10 / HIGH SPEED BUILDING BLOCKS / PAPER 10.8 10.8 10Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18µm CMOS Technology Sherif Galal, Behzad Razavi Electrical Engineering

More information

Field Effect Transistors (FET s) University of Connecticut 136

Field Effect Transistors (FET s) University of Connecticut 136 Field Effect Transistors (FET s) University of Connecticut 136 Field Effect Transistors (FET s) FET s are classified three ways: by conduction type n-channel - conduction by electrons p-channel - conduction

More information

Course Outline. 4. Chapter 5: MOS Field Effect Transistors (MOSFET) 5. Chapter 6: Bipolar Junction Transistors (BJT)

Course Outline. 4. Chapter 5: MOS Field Effect Transistors (MOSFET) 5. Chapter 6: Bipolar Junction Transistors (BJT) Course Outline 1. Chapter 1: Signals and Amplifiers 1 2. Chapter 3: Semiconductors 3. Chapter 4: Diodes 4. Chapter 5: MOS Field Effect Transistors (MOSFET) 5. Chapter 6: Bipolar Junction Transistors (BJT)

More information

MOS IC Amplifiers. Token Ring LAN JSSC 12/89

MOS IC Amplifiers. Token Ring LAN JSSC 12/89 MO IC Amplifiers MOFETs are inferior to BJTs for analog design in terms of quality per silicon area But MO is the technology of choice for digital applications Therefore, most analog portions of mixed-signal

More information

ECE 546 Lecture 12 Integrated Circuits

ECE 546 Lecture 12 Integrated Circuits ECE 546 Lecture 12 Integrated Circuits Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine 1 Integrated Circuits IC Requirements

More information

Analysis and Design of Analog Integrated Circuits Lecture 18. Key Opamp Specifications

Analysis and Design of Analog Integrated Circuits Lecture 18. Key Opamp Specifications Analysis and Design of Analog Integrated Circuits Lecture 8 Key Opamp Specifications Michael H. Perrott April 8, 0 Copyright 0 by Michael H. Perrott All rights reserved. Recall: Key Specifications of Opamps

More information

Session 10: Solid State Physics MOSFET

Session 10: Solid State Physics MOSFET Session 10: Solid State Physics MOSFET 1 Outline A B C D E F G H I J 2 MOSCap MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor: Al (metal) SiO2 (oxide) High k ~0.1 ~5 A SiO2 A n+ n+ p-type Si (bulk)

More information

Gechstudentszone.wordpress.com

Gechstudentszone.wordpress.com UNIT 4: Small Signal Analysis of Amplifiers 4.1 Basic FET Amplifiers In the last chapter, we described the operation of the FET, in particular the MOSFET, and analyzed and designed the dc response of circuits

More information

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2010

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2010 ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2010 Lecture 10: Termination & Transmitter Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Exam

More information

MOSFET & IC Basics - GATE Problems (Part - I)

MOSFET & IC Basics - GATE Problems (Part - I) MOSFET & IC Basics - GATE Problems (Part - I) 1. Channel current is reduced on application of a more positive voltage to the GATE of the depletion mode n channel MOSFET. (True/False) [GATE 1994: 1 Mark]

More information

EE 501 Lab 4 Design of two stage op amp with miller compensation

EE 501 Lab 4 Design of two stage op amp with miller compensation EE 501 Lab 4 Design of two stage op amp with miller compensation Objectives: 1. Design a two stage op amp 2. Investigate how to miller compensate a two-stage operational amplifier. Tasks: 1. Build a two-stage

More information

EECE2412 Final Exam. with Solutions

EECE2412 Final Exam. with Solutions EECE2412 Final Exam with Solutions Prof. Charles A. DiMarzio Department of Electrical and Computer Engineering Northeastern University Fall Semester 2010 My file 11480/exams/final General Instructions:

More information

65-GHz Receiver in SiGe BiCMOS Using Monolithic Inductors and Transformers

65-GHz Receiver in SiGe BiCMOS Using Monolithic Inductors and Transformers 65-GHz Receiver in SiGe BiCMOS Using Monolithic Inductors and Transformers Michael Gordon, Terry Yao, Sorin P. Voinigescu University of Toronto March 10 2006, UBC, Vancouver Outline Motivation mm-wave

More information

A 2.4-GHz 24-dBm SOI CMOS Power Amplifier with Fully Integrated Output Balun and Switched Capacitors for Load Line Adaptation

A 2.4-GHz 24-dBm SOI CMOS Power Amplifier with Fully Integrated Output Balun and Switched Capacitors for Load Line Adaptation A 2.4-GHz 24-dBm SOI CMOS Power Amplifier with Fully Integrated Output Balun and Switched Capacitors for Load Line Adaptation Francesco Carrara 1, Calogero D. Presti 2,1, Fausto Pappalardo 1, and Giuseppe

More information

Lecture 24 - The Si surface and the Metal-Oxide-Semiconductor Structure (cont.) The Long Metal-Oxide-Semiconductor Field-Effect Transistor

Lecture 24 - The Si surface and the Metal-Oxide-Semiconductor Structure (cont.) The Long Metal-Oxide-Semiconductor Field-Effect Transistor 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-1 Lecture 24 - The Si surface and the Metal-Oxide-Semiconductor Structure (cont.) The Long Metal-Oxide-Semiconductor Field-Effect

More information

Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1

Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Lecture 16 Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Outline Complementary metal oxide semiconductor (CMOS) Inverting circuit Properties Operating points Propagation delay Power dissipation

More information

Low voltage, low power, bulk-driven amplifier

Low voltage, low power, bulk-driven amplifier University of Arkansas, Fayetteville ScholarWorks@UARK Electrical Engineering Undergraduate Honors Theses Electrical Engineering 5-2009 Low voltage, low power, bulk-driven amplifier Shama Huda University

More information

Lecture 240 Cascode Op Amps (3/28/10) Page 240-1

Lecture 240 Cascode Op Amps (3/28/10) Page 240-1 Lecture 240 Cascode Op Amps (3/28/10) Page 2401 LECTURE 240 CASCODE OP AMPS LECTURE ORGANIZATION Outline Lecture Organization Single Stage Cascode Op Amps Two Stage Cascode Op Amps Summary CMOS Analog

More information

Fully-Integrated Low Phase Noise Bipolar Differential VCOs at 2.9 and 4.4 GHz

Fully-Integrated Low Phase Noise Bipolar Differential VCOs at 2.9 and 4.4 GHz Fully-Integrated Low Phase Noise Bipolar Differential VCOs at 2.9 and 4.4 GHz Ali M. Niknejad Robert G. Meyer Electronics Research Laboratory University of California at Berkeley Joo Leong Tham 1 Conexant

More information

MOSFET Amplifier Configuration. MOSFET Amplifier Configuration

MOSFET Amplifier Configuration. MOSFET Amplifier Configuration MOSFET Amplifier Configuration Single stage The signal is fed to the amplifier represented as sig with an internal resistance sig. MOSFET is represented by its small signal model. Generally interested

More information

SP 23.6: A 1.8GHz CMOS Voltage-Controlled Oscillator

SP 23.6: A 1.8GHz CMOS Voltage-Controlled Oscillator SP 23.6: A 1.8GHz CMOS Voltage-Controlled Oscillator Behzad Razavi University of California, Los Angeles, CA Formerly with Hewlett-Packard Laboratories, Palo Alto, CA This paper describes the factors that

More information

Lecture 26 - Design Problems & Wrap-Up. May 15, 2003

Lecture 26 - Design Problems & Wrap-Up. May 15, 2003 6.012 Microelectronic Devices and Circuits - Spring 2003 Lecture 26-1 Lecture 26 - Design Problems & 6.012 Wrap-Up May 15, 2003 Contents: 1. Design process 2. Design project pitfalls 3. Lessons learned

More information

MOSFET FUNDAMENTALS OPERATION & MODELING

MOSFET FUNDAMENTALS OPERATION & MODELING MOSFET FUNDAMENTALS OPERATION & MODELING MOSFET MODELING AND OPERATION MOSFET Fundamentals MOSFET Physical Structure and Operation MOSFET Large Signal I-V Characteristics Subthreshold Triode Saturation

More information

Signal Integrity Design of TSV-Based 3D IC

Signal Integrity Design of TSV-Based 3D IC Signal Integrity Design of TSV-Based 3D IC October 24, 21 Joungho Kim at KAIST joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr 1 Contents 1) Driving Forces of TSV based 3D IC 2) Signal Integrity Issues

More information

DESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER

DESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER DESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER Mayank Gupta mayank@ee.ucla.edu N. V. Girish envy@ee.ucla.edu Design I. Design II. University of California, Los Angeles EE215A Term Project

More information

Due to the absence of internal nodes, inverter-based Gm-C filters [1,2] allow achieving bandwidths beyond what is possible

Due to the absence of internal nodes, inverter-based Gm-C filters [1,2] allow achieving bandwidths beyond what is possible A Forward-Body-Bias Tuned 450MHz Gm-C 3 rd -Order Low-Pass Filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V Supply Joeri Lechevallier 1,2, Remko Struiksma 1, Hani Sherry 2, Andreia Cathelin

More information

ISSCC 2004 / SESSION 21/ 21.1

ISSCC 2004 / SESSION 21/ 21.1 ISSCC 2004 / SESSION 21/ 21.1 21.1 Circular-Geometry Oscillators R. Aparicio, A. Hajimiri California Institute of Technology, Pasadena, CA Demand for faster data rates in wireline and wireless markets

More information

Lecture 3 Switched-Capacitor Circuits Trevor Caldwell

Lecture 3 Switched-Capacitor Circuits Trevor Caldwell Advanced Analog Circuits Lecture 3 Switched-Capacitor Circuits Trevor Caldwell trevor.caldwell@analog.com Lecture Plan Date Lecture (Wednesday 2-4pm) Reference Homework 2017-01-11 1 MOD1 & MOD2 ST 2, 3,

More information

RF Solid State Driver for Argonne Light Source

RF Solid State Driver for Argonne Light Source RF olid tate Driver for Argonne Light ource Branko Popovic Lee Teng Internship University of Iowa Goeff Waldschmidt Argonne National Laboratory Argonne, IL August 13, 2010 Abstract Currently, power to

More information

A 2.4 GHZ RECEIVER IN SILICON-ON-SAPPHIRE MICHAEL PETERS. B.S., Kansas State University, 2009 A REPORT

A 2.4 GHZ RECEIVER IN SILICON-ON-SAPPHIRE MICHAEL PETERS. B.S., Kansas State University, 2009 A REPORT A 2.4 GHZ RECEIVER IN SILICON-ON-SAPPHIRE by MICHAEL PETERS B.S., Kansas State University, 2009 A REPORT submitted in partial fulfillment of the requirements for the degree MASTER OF SCIENCE Department

More information

Low-Noise Amplifiers

Low-Noise Amplifiers 007/Oct 4, 31 1 General Considerations Noise Figure Low-Noise Amplifiers Table 6.1 Typical LNA characteristics in heterodyne systems. NF IIP 3 db 10 dbm Gain 15 db Input and Output Impedance 50 Ω Input

More information

Design of a Low Noise Amplifier using 0.18µm CMOS technology

Design of a Low Noise Amplifier using 0.18µm CMOS technology The International Journal Of Engineering And Science (IJES) Volume 4 Issue 6 Pages PP.11-16 June - 2015 ISSN (e): 2319 1813 ISSN (p): 2319 1805 Design of a Low Noise Amplifier using 0.18µm CMOS technology

More information

Course Number Section. Electronics I ELEC 311 BB Examination Date Time # of pages. Final August 12, 2005 Three hours 3 Instructor

Course Number Section. Electronics I ELEC 311 BB Examination Date Time # of pages. Final August 12, 2005 Three hours 3 Instructor Course Number Section Electronics ELEC 311 BB Examination Date Time # of pages Final August 12, 2005 Three hours 3 nstructor Dr. R. Raut M aterials allowed: No Yes X (Please specify) Calculators allowed:

More information

High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers

High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers Michael H. Perrott March 19, 2004 Copyright 2004 by Michael H. Perrott All rights reserved. 1 High Speed Frequency

More information

ECE/CoE 0132: FETs and Gates

ECE/CoE 0132: FETs and Gates ECE/CoE 0132: FETs and Gates Kartik Mohanram September 6, 2017 1 Physical properties of gates Over the next 2 lectures, we will discuss some of the physical characteristics of integrated circuits. We will

More information

A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions

A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions Brigham Young University BYU ScholarsArchive All Theses and Dissertations 2012-01-28 A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions Taylor Matt Waddel

More information

Microelectronics, BSc course

Microelectronics, BSc course Microelectronics, BSc course MOS circuits: CMOS circuits, construction http://www.eet.bme.hu/~poppe/miel/en/14-cmos.pptx http://www.eet.bme.hu The abstraction level of our study: SYSTEM + MODULE GATE CIRCUIT

More information

INF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation

INF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation INF3410 Fall 2013 Compensation content Introduction Two Stage Opamps Compensation Slew Rate Systematic Offset Advanced Current Mirrors Operational Transconductance Amplifiers Current Mirror Opamps Folded

More information

DAT175: Topics in Electronic System Design

DAT175: Topics in Electronic System Design DAT175: Topics in Electronic System Design Analog Readout Circuitry for Hearing Aid in STM90nm 21 February 2010 Remzi Yagiz Mungan v1.10 1. Introduction In this project, the aim is to design an adjustable

More information

EEC 210 Fall 2008 Design Project. Rajeevan Amirtharajah Dept. of Electrical and Computer Engineering University of California, Davis

EEC 210 Fall 2008 Design Project. Rajeevan Amirtharajah Dept. of Electrical and Computer Engineering University of California, Davis EEC 210 Fall 2008 Design Project Rajeevan Amirtharajah Dept. of Electrical and Computer Engineering University of California, Davis Issued: November 18, 2008 Due: December 5, 2008, 5:00 PM in my office.

More information

ESE 372 / Spring 2011 / Lecture 19 Common Base Biased by current source

ESE 372 / Spring 2011 / Lecture 19 Common Base Biased by current source ESE 372 / Spring 2011 / Lecture 19 Common Base Biased by current source Output from Collector Start with bias DC analysis make sure BJT is in FA, then calculate small signal parameters for AC analysis.

More information

Unit 3: Integrated-circuit amplifiers (contd.)

Unit 3: Integrated-circuit amplifiers (contd.) Unit 3: Integrated-circuit amplifiers (contd.) COMMON-SOURCE AND COMMON-EMITTER AMPLIFIERS The Common-Source Circuit The most basic IC MOS amplifier is shown in fig.(1). The source of MOS transistor is

More information

1 Introduction to analog CMOS design

1 Introduction to analog CMOS design 1 Introduction to analog CMOS design This chapter begins by explaining briefly why there is still a need for analog design and introduces its main tradeoffs. The need for accurate component modeling follows.

More information

Bluetooth Receiver. Ryan Rogel, Kevin Owen I. INTRODUCTION

Bluetooth Receiver. Ryan Rogel, Kevin Owen I. INTRODUCTION 1 Bluetooth Receiver Ryan Rogel, Kevin Owen Abstract A Bluetooth radio front end is developed and each block is characterized. Bits are generated in MATLAB, GFSK endcoded, and used as the input to this

More information

In Search of Powerful Circuits: Developments in Very High Frequency Power Conversion

In Search of Powerful Circuits: Developments in Very High Frequency Power Conversion Massachusetts Institute of Technology Laboratory for Electromagnetic and Electronic Systems In Search of Powerful Circuits: Developments in Very High Frequency Power Conversion David J. Perreault Princeton

More information

K-Band Low-Noise Amplifier Design in CMOS Technology

K-Band Low-Noise Amplifier Design in CMOS Technology K-Band Low-Noise Amplifier Design in CMOS Technology by Dustin Dunwell A thesis submitted to the Department of Electrical and Computer Engineering in conformity with the requirements for the degree of

More information

LC VCO Design Procedure

LC VCO Design Procedure L VO Design Procedure 116 UMTS VO VO design parameters Design requirement Oscillating frequency 2.1GHz Tuning range 400MHz Voltage swing 0.7V Phase noise -110dBc@1MHz Supply voltage 3V Power consumption

More information

ECE 340 Lecture 40 : MOSFET I

ECE 340 Lecture 40 : MOSFET I ECE 340 Lecture 40 : MOSFET I Class Outline: MOS Capacitance-Voltage Analysis MOSFET - Output Characteristics MOSFET - Transfer Characteristics Things you should know when you leave Key Questions How do

More information

Negative high voltage DC-DC converter using a New Cross-coupled Structure

Negative high voltage DC-DC converter using a New Cross-coupled Structure Negative high voltage DC-DC converter using a New Cross-coupled Structure Jun Zhao 1, Kyung Ki Kim 2 and Yong-Bin Kim 3 1 Marvell Technology, USA 2 Department of Electronic Engineering, Daegu University,

More information

CMOS Operational Amplifier

CMOS Operational Amplifier The George Washington University Department of Electrical and Computer Engineering Course: ECE218 Instructor: Mona E. Zaghloul Students: Shunping Wang Yiping (Neil) Tsai Data: 05/14/07 Introduction In

More information

Application Note A008

Application Note A008 Microwave Oscillator Design Application Note A008 Introduction This application note describes a method of designing oscillators using small signal S-parameters. The background theory is first developed

More information

Lecture 330 Low Power Op Amps (3/27/02) Page 330-1

Lecture 330 Low Power Op Amps (3/27/02) Page 330-1 Lecture 33 Low Power Op Amps (3/27/2) Page 33 LECTURE 33 LOW POWER OP AMPS (READING: AH 39342) Objective The objective of this presentation is:.) Examine op amps that have minimum static power Minimize

More information

A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage

A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage EEE 523 Advanced Analog Integrated Circuits Project Report Fuding Ge You are an engineer who is assigned the project to design

More information

2.8 - CMOS TECHNOLOGY

2.8 - CMOS TECHNOLOGY CMOS Technology (6/7/00) Page 1 2.8 - CMOS TECHNOLOGY INTRODUCTION Objective The objective of this presentation is: 1.) Illustrate the fabrication sequence for a typical MOS transistor 2.) Show the physical

More information

Lecture 350 Low Voltage Op Amps (3/26/02) Page 350-1

Lecture 350 Low Voltage Op Amps (3/26/02) Page 350-1 Lecture 350 Low Voltage Op Amps (3/26/02) Page 3501 LECTURE 350 LOW VOLTAGE OP AMPS (READING: AH 415432) Objective The objective of this presentation is: 1.) How to design standard circuit blocks with

More information

Technology-Independent CMOS Op Amp in Minimum Channel Length

Technology-Independent CMOS Op Amp in Minimum Channel Length Technology-Independent CMOS Op Amp in Minimum Channel Length A Thesis Presented to The Academic Faculty by Susanta Sengupta In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy

More information

Georgia Institute of Technology School of Electrical and Computer Engineering. Midterm Exam

Georgia Institute of Technology School of Electrical and Computer Engineering. Midterm Exam Georgia Institute of Technology School of Electrical and Computer Engineering Midterm Exam ECE-3400 Fall 2013 Tue, September 24, 2013 Duration: 80min First name Solutions Last name Solutions ID number

More information

Nonlinear Macromodeling of Amplifiers and Applications to Filter Design.

Nonlinear Macromodeling of Amplifiers and Applications to Filter Design. ECEN 622(ESS) Nonlinear Macromodeling of Amplifiers and Applications to Filter Design. By Edgar Sanchez-Sinencio Thanks to Heng Zhang for part of the material OP AMP MACROMODELS Systems containing a significant

More information