Difference between BJTs and FETs. Junction Field Effect Transistors (JFET)

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1 Difference between BJTs and FETs Transistors can be categorized according to their structure, and two of the more commonly known transistor structures, are the BJT and FET. The comparison between BJTs and FETs is given below. Junction Field Effect Transistors (JFET) The junction field effect transistor or JFET is one of the simplest transistors from the structural point of view. It is a voltage controlled semiconductor device. In this, the current is carried by only one type of carriers. So, it is a unipolar device. 1

2 JFET consists of a doped Si or GaAs bar. There are ohmic contacts, the two ends of the bar and semiconductor junction on its two sides. If the semiconductor bar is n-type, the two sides of the bar is heavily doped with p - type impurities and this is known as n - channel JFET. On the other hand if the semiconductor bar is p- type, the two sides of the bar is heavily doped with n - type impurities and this is known as p- channel JFET. When a voltage is applied between the two ends, a current which is carried by the majority carriers of the bar flows along the length of the bar. There are several terminals in JFET. The terminal through which the majority carrier enter the bar and the terminal through which they leave are known as source (s) and drain (D) respectively. The heavily doped region on the two sides is known as the gate (G). In junction field effect transistor, the junction is a reverse biased. As a result, depletion regions form, which extend to the bar. By changing gate to source voltage, the depletion width can be controlled. So, the effective cross section area decreased with increasing reverse bias. So, the drain current is a function of the gate to the source voltage. The circuit symbol for the JFETs are shown below for both N-channel and P- channel JFET. Operation of N-channel JFET: The circuit connection for understanding the operation of JFET is shown below. 2

3 If an n-channel JFET is biased as explained above and the gate to source voltage is kept zero, due to the positive drain to source voltage few electrons which are available for conduction in the n-type material will start flowing from the narrow passage (channel) from source to drain. This current is called as drain current. As the channel has some finite resistance it will cause some voltage drop across the channel. Hence the depletion region of the p-n junction starts increasing and penetrates more into the n-type material as it is lightly doped. Due to this the width of the channel available for conduction is reduced. The penetration of the depletion region into the n-type region depends on the reverse bias voltage. Maximum drain current I DSS will flow through the device when the channel is widest i.e. when V GS is zero. The corresponding characteristic curve is shown below. Operation with negative gate to source voltage: As a negative voltage is applied to the gate to source p-n junction the depletion region increases and penetration of the depletion region into the n-type channel further increases. If the negative gate to source voltage is further increased the depletion region spreads more and more inside the n-type bar. Due to this less and less number of charge carries (electrons) can pass through the channel and the drain current reduces. Hence, with increase in negative gate to source voltage drain current reduces. At a certain value of this voltage the depletion region from both the ends will increase and touch each other and the drain current will become zero. This gate to source voltage at which drain current is cutoff is called as V GS(OFF). As seen the V GS controls I D. Hence, JFET is a voltage controlled device. The relationship between I D and V GS is given by Shockley s equation. Where, V P is the pinch off voltage which is the value of drain to source V DS at which drain current reaches its constant saturation value. Any further increase in V DS does not affect I D. 3

4 The overall output characteristic curves for different values of V GS are shown below. It has three regions of operation: ohmic region, saturation region and avalanche region as shown. Ohmic region: Here the drain to source voltage is small and drain current in nearly proportional to the drain to source voltage. When a positive drain to source voltage is applied, this voltage increases from zero to a small value, the depletion region width remain very small and under this condition the semi conductor bar behaves just like a resistor. So, drain current increases almost linearly with drain to source voltage. The value of resistance is given by where r 0 is the resistance at V GS =0V. Saturation region: Here the drain current is almost constant and it is not dependent on the drain to source voltage actually. When the drain to source voltage continuous to increase the channel resistance increases and at some point, the depletion regions meet near the drain to pinch off the channel. Beyond that pinch off voltage, the drain, current attains saturation. Breakdown region: Here the drain current increases rapidly with a small increase of the drain to source voltage. Actually for large value of drain to source voltage, a breakdown of the gate junction takes place which results a sharp increase of the drain current. Transfer characteristics: The graphical characteristics plot of the saturation drain current against the gate to source voltage is known as the transfer characteristics of JFET. It can be obtained from output characteristics very easily. The transfer characteristics of an n- channel JFET are shown below. 4

5 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) MOSFET is a four terminal device. The drain and source terminals are connected to the heavily doped regions. The gate terminal is connected top on the oxide layer and the substrate or body terminal is connected to the intrinsic semiconductor. MOSFETs are enhancement type or depletion type MOSFETs. In enhancement mode, these are normally off and turned on by applying gate voltage. The opposite phenomenon happens in depletion type MOSFETs. Two basic types of MOSFETs are N-channel and P-channel MOSFETs. In n channel MOSFET is current is due to the flow of electrons in inversion layer and in p channel current is due to the flow of holes. The construction and symbols of enhancement type MOSFETs are shown below. 5

6 Principle of operation: The metal of the gate terminal and the substrate contact act like parallel plates and the oxide layer acts as insulator, thus forming a MOS capacitor. The semiconductor surface at below the oxide layer and between the drain and source terminal can be inverted from p-type to n-type by applying a positive or negative gate voltages respectively. When we apply positive gate voltage the holes present beneath the oxide layer experience repulsive force and the holes are pushed downward with the substrate. The depletion region is populated by the bound negative charges, which are associated with the acceptor atoms. The positive voltage also attracts electrons from the n+ source and drain regions in to the channel. The electron reach channel is formed. Now, if a voltage is applied between the source and the drain, current flows freely between the source and drain gate voltage controls the electrons concentration the channel. Instead of positive if apply negative voltage a hole channel will be formed beneath the oxide layer. Now, the controlling of source to gate voltage is responsible for the conduction of current between source and the drain. If the gate voltage exceeds a given value, called the threshold voltage, only then the conduction begins. The output characteristic curves and the transfer characteristics of a n-channel enhancement MOSFET are shown below. Depletion MOSFET: The construction and symbol of Depletion type MOSFETs are shown below. These devices are are normally on and turned off by applying gate voltage. 6

7 The corresponding output characteristic curves and transfer curves are also shown below. The only difference from enhancement type is that, this device can work in both depletion mode (V GS < 0V) as well as in enhancement mode (V GS > 0V). Differences between JFETs and MOSFETs Both JFETs and MOSFETs are unipolar devices which work on the principle of controlling output current through input voltage. The table below compares the two types of FETs. JFETs Depletion mode only MOSFETs D-MOSFETs both Depletion and Enhancement mode High input resistance (10 9 Ω) Very High input resistance (10 13 Ω) High drain resistance Low drain resistance (100 kω - 1MΩ) (1 Ω - 50 kω ) High Gate leakage current (100 μa - 10 Negligible Gate leakage current (100 na - na) 10 pa) Slightly more complex than MOSFET to Easier to construct and used more widely construct 7

8 Biasing MOSFETs One of the most widely used configurations of MOSFETs is as amplifiers. In order to function as a linear amplifier, the device has to be biased by an external DC voltage which ensures that it operates in the saturation region for the entire input signal swing (AC). There are two methods of biasing depletion MOSFETs: Self Bias and Voltage Divider bias. The latter one is more suited since it is more stable and experiences little drift in Q-point with variations in temperature and process. The examples below detail the design and usage of both biasing techniques for Depletion MOSFETs. 8

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10 Biasing Enhancement MOSFETs: There are two methods of biasing Enhancement MOSFETs: feedback Bias and Voltage Divider bias. The latter one is more suited since it is more stable and experiences little drift in Q-point with variations in temperature and process. The examples below detail the design and usage of both biasing techniques. 10

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15 FET Applications The JFETs are used in a variety of applications in electronics; some of them are listed below. Amplifier: Noise is an undesirable disturbance which interferes with the signals information - greater the noise less the information. Energy electronics device cause some amount of noise. If FET s is used at the front end, we get less amount of amplified noise at the output. Now, it has very high input impedance. So, it can be used in high input impedance amplifier. Buffer amplifier should have very high input impedance and low output impedance. Because of high i / p impedance and low output impedance, FET acts as great buffer amplifier, the common drain mode can be used in this purpose. Analog Switch: JFET may be used as an on / off switch controlling electrical power to load. JFET s are normally ON devices. They are normally saturated devices. When a reverse bias is applied between gate and source, the depletion regions of that junction expand and pinching off the channel through which current flowing takes place. If the channel is pinched the current does not flow the device will be in switched off condition. By this process junction field effect transistor can be used as switches. 15

16 Multiplexers: An analog multiplexer, a circuit that steers one of the input signals to the output line, is shown in figure below. In this circuit each JFET acts as a single-pole single-throw switch. When the control signals (input 1, input 2,... input n) are more negative than V GS(0FF) all input signals are blocked. By making any control voltage equal to zero, one of the inputs can be transmitted to the output. For instance, when input 1 is zero, the signal obtained at the output will be V in1. Similarly when input 2 is zero, the signal obtained at the output will be V in2 and so on. Normally, only one of the control signals is zero. Current Limiters: JFET current limiting circuit is shown in figure below. Almost all the supply voltage therefore appears across the load. When the load current tries to increase to an excessive level (may be due to short-circuit or any other reason), the excessive load current forces the JFET into saturation region, where it limits the current to I DSS. The JFET now acts as a current source and prevents excessive load current. Voltage-Variable Resistors (VVRs): FET is a device that is usually operated in the constant-current portion of its output characteristics. But if it is operated on the region prior to pinch-off (that is where V DS is small, say below 100 mv), it will behave as a voltage-variable resistor (VVR). It is due to the fact that in this region drain-to-source resistance R DS can be controlled by varying the bias voltage V GS. As seen in the figure below, The slope of the curve for V GS =0V is the highest, while it is lowest for V GS =-3V. Since slope (ΔI/ΔV) is the inverse of resistance (r 0 =ΔV/ΔI) the resistance is lowest at V GS =0V and highest at V GS =-3V. 16

17 Phase Shift Oscillator: The circuit below shows the amplifier and feedback network configuration for a RC phase shift oscillator. The circuit consists of a common source FET amplifier followed by a three section R-C phase shift network. The amplifier stage is self-biased with a capacitor bypassed source resistor R S and a drain bias resistance R D. The output of the last section is supplied back to the gate. If the loading of the phase-shift network on the amplifier can be assumed to be negligible, a phase shift of 180 between the amplified output voltage V o and the input voltage V in at the gate is produced by the amplifier itself. The three-section R-C phase shift network produces an additional phase shift, which is a function of frequency and equals 180 at some frequency of operation. At this frequency the total phase shift from the gate around the circuit and back to gate will be exactly zero. This particular frequency will be the one at which the circuit will oscillate provided that the magnitude of the amplification is sufficiently large. CMOS Devices Complementary MOS, or CMOS, circuits contain both n-channel and p-channel MOSFETs. The figure below shows a simplified cross section of a CMOS inverter. In this process, a separate p-well region is formed within the starting n-substrate. The n- 17

18 channel device is fabricated in the p-well region and the p-channel device is fabricated in n-substrate. Although other approaches, such as an n-well in a p-substrate, are also used to fabricate CMOS circuits, the important point is that the processing is more complicated for CMOS circuits than for NMOS circuits. However, the advantages of CMOS digital logic circuits over NMOS circuits justify their use. The circuit configuration is also shown below. When the input is LOW, only PMOS is ON, and output is HIGH. Next, when input is HIGH, only NMOS is ON, and the output is LOW. Thus we have a inverting logic, which we call as NOT gate in digital circuits. Integrated Circuit(IC) Multivibrators. Astable Multivibrator: The 555 timer IC can be used in astable mode to produce a very stable Oscillator circuit for generating highly accurate free running waveforms whose output frequency can be adjusted by means of an externally connected RC tank circuit consisting of just two resistors and a capacitor. The circuit diagram is shown below along with the relevant waveforms. In the 555 Oscillator circuit, pin 2 and pin 6 are connected together allowing the circuit to re-trigger itself on each and every cycle allowing it to operate as a free running oscillator. During each cycle capacitor, C charges up through both timing resistors, R 1 and R 2 but discharges itself only through resistor, R 2 as the other side of R 2 is connected to the discharge terminal, pin 7. Then the capacitor charges up to 2/3V cc (the upper comparator limit) which is determined by the 0.69(R 1 +R 2 )C combination and discharges itself down to 1/3V cc (the lower comparator limit) determined by the 0.69(R 2 C) 18

19 combination. This results in an output waveform whose voltage level is approximately equal to V cc V and whose output ON and OFF time periods are determined by the capacitor and resistors combinations. The individual times required to complete one charge and discharge cycle of the output is therefore given as: t ON =0.69(R 1 +R 2 )C and t OFF =0.69(R 2 C) The duration of one full timing cycle is therefore equal to the sum of the two individual times that the capacitor charges and discharges added together and is given as: T = t ON + t OFF = 0.69(R 1 +2R 2 )C Monostable Multivibrator: These have only ONE stable state and produce a single output pulse when it is triggered externally. Monostable multivibrators only return back to their first original and stable state after a period of time determined by the time constant of the RC coupled circuit. The circuit configuration is shown below with relevant waveforms. When a negative pulse is applied to the trigger input (pin 2) of the Monostable configured 555 Timer oscillator, the lower comparator, detects this input and sets the state of the flip-flop, changing the output from a LOW state to a HIGH state. This 19

20 action in turn turns OFF the discharge transistor connected to pin 7, thereby removing the short circuit across the external timing capacitor (C). This action allows the timing capacitor to start to charge up through resistor(r) until the voltage across the capacitor reaches the threshold (pin 6) voltage of 2/3Vcc set up by the internal voltage divider network. At this point the comparators output goes HIGH and resets the flip-flop back to its original state which in turn turns ON the transistor and discharges the capacitor to ground through pin 7. This causes the output to change its state back to the original stable LOW value awaiting another trigger pulse to start the timing process over again. Then as before, the Monostable Multivibrator has only ONE stable state. The Monostable 555 Timer circuit triggers on a negative-going pulse applied to pin 2 and this trigger pulse must be much shorter than the output pulse width allowing time for the timing capacitor to charge and then discharge fully. Once triggered, the 555 Monostable will remain in this HIGH unstable output state until the time period set up by the RC network has elapsed. The amount of time that the output voltage remains HIGH or at a logic 1 level, is given by the equation T = 1.1 RC. Introduction to Operational Amplifier Operational amplifiers are linear devices that have all the properties required for nearly ideal DC amplification and are therefore used extensively in signal conditioning, filtering or to perform mathematical operations such as add, subtract, integration and differentiation. An Operational Amplifier, or op-amp for short, is fundamentally a voltage amplifying device designed to be used with external feedback components such as resistors and capacitors between its output and input terminals. These feedback components determine the resulting function or operation of the amplifier and by virtue of the different feedback configurations whether resistive, capacitive or both, the amplifier can perform a variety of different operations, giving rise to its name of Operational Amplifier. Equivalent Circuit of a practical Operational Amplifier: The figure below shows the equivalent circuit of practical opamp. Equivalent Circuit of an Ideal Operational Amplifier: The figure below shows the equivalent circuit of an ideal opamp. 20

21 Comparison between ideal and practical opamp: The table below summarizes the important comparisons between ideal and practical opamp. Parameter Ideal Practical (IC741) Bandwidth 1 MHz Slew Rate 0.5 V/μs Open-loop gain 200 V/mV CMRR 90 db PSRR 96 db Input Impedance 2 MΩ Output Impedance Ω Settling time μs Input Offset Voltage 0 2 mv 21

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23 Opamp Applications Peak Detector: The peak detector is a circuit that "remembers" the peak value of a signal. The circuit diagram is shown below. When a positive voltage is fed to the non-inverting input after the capacitor has been momentarily shorted (reset), the output voltage of the op-amp forward biases the diode and charges up the capacitor. This charging last until the inverting and noninverting inputs are at the same voltage, which is equal to the input voltage. When the non-inverting input voltage exceeds the voltage at the inverting input, which is also the voltage across the capacitor, the capacitor will charge up to the new peak value. Consequently, the capacitor voltage will always be equal to the greatest positive voltage applied to the non-inverting input. Once charged, the time that the peak detector "remembers" this peak value is typically several minutes and depends on the impedance of the load that is connected to the circuit. Consequently, the capacitor will slowly discharge towards zero. To minimize this rate of discharge, a voltage follower can be used to buffer the detector's output from any external load, as shown in figure. Comparator as Zero Crossing Detector: In opamp zero crossing detectors the output responds almost discontinuously every time the input passes through zero. It consists of a comparator circuit with diode arrangement. The circuit diagram is shown below. A signal is applied to non-inverting input of opamp. Since the opamp is in open loop configuration, Vo will be at positive saturation voltage +V SAT whenever Vi > 0 V and is at negative saturation voltage -V SAT when Vi < 0 V. The diode is kept to bypass any large 23

24 signal which may damage the opamp. These diodes conduct whenever V i > +/- 0.7V, thus preventing any signal from reaching the opamp. Active Filters: Active Filters contain active components such as operational amplifiers within their circuit design. They draw their power from an external power source and use it to boost or amplify the output signal. The first-order low pass and high pass active filter, consists simply of a passive RC filter stage providing a low frequency path or a high frequency path respectively, to the input of a non-inverting operational amplifier, as shown below. The amplifier is configured as a voltage-follower (Buffer) giving it a DC gain of unity. The cut-off frequency is governed by the equation f c = 1/(2πRC). Active Low Pass Filter with Amplification: The frequency response of the circuit will be the same as that for the passive RC filter, except that the amplitude of the output is increased by the pass band gain, A v of the amplifier. The circuit configurations are shown below. For a non-inverting amplifier circuit, the magnitude of the voltage gain for the filter is given as a function of the feedback resistor (R 3 ) divided by its corresponding input resistor (R 2 ) value and is given as: A v =(1+R 3 /R 2 ). The cut-off frequency is then given by the equation f c = 1/(2πR 1 C 1 ). 24

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26 Relaxation Oscillator: The circuit diagram for the oscillator is shown below along with relevant waveforms. Firstly assume that the capacitor is fully discharged and the output of the op-amp is saturated at the positive supply rail. The capacitor, C starts to charge up from the output voltage, V o through resistor, R at a rate determined by their RC time constant. However, as soon as the capacitors charging voltage at the op-amps inverting terminal is equal to or greater than the voltage at the non-inverting terminal (the op-amps output voltage fraction divided between resistors R 1 and R 2 ), the output will change state and be driven to the opposing negative supply rail. But the capacitor, which has been happily charging towards the positive supply rail (+V SAT ), now sees a negative voltage, (-V SAT ) across its plates. This sudden reversal of the output voltage causes the capacitor to discharge toward the new value of V o at a rate dictated again by their RC time constant. Thus we get continuous waveform of square type at the output. The time period of the resulting waveform is given by: T=2RC ln((1+b)/(1-b)), where B=R 1 /(R 1 +R 2 ) 26

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