Lecture 350 Low Voltage Op Amps (3/26/02) Page 350-1
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1 Lecture 350 Low Voltage Op Amps (3/26/02) Page 3501 LECTURE 350 LOW VOLTAGE OP AMPS (READING: AH ) Objective The objective of this presentation is: 1.) How to design standard circuit blocks with reduced power supply voltage 2.) Introduce new methods of designing low voltage circuits Outline Low voltage input stages Low voltage bias circuits Low voltage op amps Examples Summary Lecture 350 Low Voltage Op Amps (3/26/02) Page 3502 Introduction While low voltage op amps can be easily designed in weak inversion, strong inversion leads to higher performance and is the focus of this section. Semiconductor Industry Associates Roadmap for Power Supplies: Feature Size 0.35µm 0.25µm 0.18µm 0.13µm 0.10µm 0.07µm Power Supply Voltage 3.0V 2.5V 2.0V 1.5V 1.0V Desktop Systems Portable Systems Year Single Cell Voltage Fig Threshold voltages will remain about 0.5 to 0.7V in order to allow the MOSFET to be turned off.
2 Lecture 350 Low Voltage Op Amps (3/26/02) Page 3503 Implications of LowVoltage, StrongInversion Operation Reduced power supply means decreased dynamic range Nonlinearity will increase because the transistor is working close to V DS (sat) Large values of λ because the transistor is working close to V DS (sat) Increased drainbulk and sourcebulk capacitances because they are less reverse biased. Large values of currents and W/L ratios to get high transconductance Small values of currents and large values of W/L will give smallv DS (sat) Severely reduced input common mode range Switches will require charge pumps Approach Low voltage input stages with reasonable ICMR Low voltage bias and load circuits Low voltage op amps Lecture 350 Low Voltage Op Amps (3/26/02) Page 3504 Differential Amplifier with Current Source Loads Minimum power supply (ICMR = 0): (min) = V SD3 (sat)v T1 V GS1 V DS5 (sat) = V SD3 (sat)v DS1 (sat)v DS5 (sat) V SD3 (sat) M3 M4 VBias Input commonmode range: V icm (upper) = V SD3 (sat) V T1 V icm (lower) = V DS5 (sat) V GS1 V T1 v icm V GS1 M1 M2 V DS5 (sat) VBias Example: If the threshold magnitudes are 0.7V, = 1.5V and the saturation voltages are 0.3V, then V icm (upper) = = 1.9V and V icm (lower) = = 1.3V giving an ICMR of 0.6V. M5 Fig. 7.63
3 Lecture 350 Low Voltage Op Amps (3/26/02) Page 3505 Increasing ICMR using Parallel Input Stages Turnon voltage for the nchannel input: M6 V onn = V DSN5 (sat) V GSN1 Turnon voltage for the pchannel input: I Bias V onp = V SDP5 (sat) V SGP1 The sum of V onn and V onp equals the minimum M7 power supply. Regions of operation: > V icm > V onp : (nchannel on and pchannel off) V onp V icm V onn : (nchannel on and pchannel on) V onn > V icm > 0 : (nchannel off and pchannel on) g m (eq) = g mn g m (eq) = g mn g mp g m (eq) = g mp where g m (eq) is the equivalent input transconductance of the above input stage, g mn is the input transconductance for the nchannel input and g mp is the input transconductance for the pchannel g m (eff) input. g mn g mp V icm MN3 MN1 MP1 MP3 MP5 MN5 MP2 MN2 MP4 MN4 V icm Fig g mp nchannel off V onn nchannel on V onp nchannel on pchannel on pchannel on pchannel off 0 V SDP5 (sat)v GSN1 V SDP5 (sat)v GSN1 g mn V icm Fig Lecture 350 Low Voltage Op Amps (3/26/02) Page 3506 Removing the Nonlinearity in Transconductances as a Function of ICMR Increase the bias current in the differential amplifier that is on when the other I b differential amplifier is off. 3:1 Three regions of operation depending on V MP1 MP2 B2 V icm the value of V icm : MB2 1.) V icm < V onn : nchannel diff. amp. MN1 off and pchannel on with I p = 4I b : I n K P W P g m (eff) = L 2 I P b I b 2.) V onn < V icm < V onp : both on with 1:3 I n = I p = I b : g m (eff) = K N W N L N I b K P W P L P I b 3.) V icm > V onp : pchannel diff. amp. off and nchannel on with I n = 4I b : g m (eff) = K N W N L N 2 I b I nn I p MN2 V icm MB1 I pp V B1 Fig. 7.66
4 Lecture 350 Low Voltage Op Amps (3/26/02) Page 3507 How Does the Current Compensation Work? Set V B1 = V onn and V B2 = V onp. Result: v icm MN1 I n v icm MB1 MN2 I pp V onn I b If v icm >V onn then I n = I b and I pp =0 If v icm <V onn then I n = 0 and I pp =I b g m (eff) If v icm <V onp then I p = I b and I nn =0 If v icm >V onp then I p = 0 and I nn =I b V onp I nn v MP1 icm MB2 I b I p MP2 v icm Fig. 7.66A g mn =g mp 0 0 V onn V onp VDD V icm Fig The above techniques and many similar ones are good for power supply values down to about 1.5V. Below than, different techniques must be used or the technology must be modified (natural devices). Lecture 350 Low Voltage Op Amps (3/26/02) Page 3508 BulkDriven MOSFET A depletion device would permit large ICMR even with very small power supply voltages because V GS is zero or negative. When a MOSFET is driven from the bulk with the gate held constant, it acts like a depletion transistor. Crosssection of an nchannel v BS V DS V GS bulkdriven MOSFET: Large signal equation: i D = K N W 2L V GS V T0 γ 2 φ F v BS γ 2 φ F 2 Smallsignal transconductance: g mbs = γ (2K N W/L)I D 2 2 φ F V BS ;; Bulk Drain Gate Source Substrate ;; p ;;; n Channel ;; n ; ;; n Depletion Region pwell n substrate QP QV Fig. 7.68
5 Lecture 350 Low Voltage Op Amps (3/26/02) Page 3509 BulkDriven MOSFET Continued Transconductance characteristics: 2000 Bulksource driven Saturation: V DS > V BS V P gives, V BS = V P V ON Drain Current (µa) i D = I DSS 1 V BS 2 I DSS Gatesource V P driven Comments: g m (bulk) > g m (gate) if V BS > 0 GateSource or BulkSource Voltage (Volts) (forward biased ) Noise of both configurations are the same (any differences comes from the gate versus bulk noise) Bulkdriven MOSFET tends to be more linear at lower currents than the gatedriven MOSFET Very useful for generation of I DSS floating current sources. Fig Lecture 350 Low Voltage Op Amps (3/26/02) Page BulkDriven, nchannel Differential Amplifier What is the ICMR? V icm (min) = V SS V DS5 (sat) V BS1 = V SS V DS5 (sat) V P1 V DS1 (sat) Note that V icm can be less than V SS if V P1 > V DS5 (sat) V DS1 (sat) V icm (max) =? As V icm increases, the current through M1 and M2 is constant so the source M3 M4 increases. However, the gate voltage stays M7 constant so that V GS1 decreases. Since the current must remain constant through M1 and M2 because of M5, the bulksource voltage becomes less negative Bias v i1 v I i2 causing V TN1 to decrease and maintain V BS1 M1V GS M2V BS2 the currents through M1 and M2 constant. If V icm is increased sufficiently, the bulksource voltage will become positive. M6 M5 However, current does not start to flow until V BS is greater than 0.3 volts so the V SS effective V icm (max) is V icm (max) V SD3 (sat) V DS1 (sat) V BS1. Fig
6 Lecture 350 Low Voltage Op Amps (3/26/02) Page Illustration of the ICMR of the BulkDriven, Differential Amplifier 250nA 200nA BulkSource Current 150nA 100nA 50nA 0 Comments: Effective ICMR is from V SS to 0.3V 50nA 0.50V 0.25V 0.00V 0.25V 0.50V Input CommonMode Voltage Fig A The transconductance of the input stage can vary as much as 100% over the ICMR which makes it very difficult to compensate Lecture 350 Low Voltage Op Amps (3/26/02) Page LowVoltage Current Mirrors using the BulkDriven MOSFET The biggest problem with current mirrors is the large minimum input voltage required for previously examined current mirrors. If the bulkdriven MOSFET is biased with a current that exceeds I DSS then it is enhancement and can be used as a current mirror. i in i out M1 M2 V GS V BS V GS Simple bulkdriven current mirror i in i out M3 M4 V GS3 V BS3 V GS4 M1 M2 V GS1 V BS1 V GS2 Cascodebulkdriven current mirror. Fig Vout (V) Fig The cascode current mirror gives a minimum input voltage of less than 0.5V for currents less than 100µA Iout (A) Cascode Current Mirror All W/L's = 200µm/4µm 2µm CMOS Iin=50µA Iin=40µA Iin=30µA Iin=20µA Iin=10µA
7 Lecture 350 Low Voltage Op Amps (3/26/02) Page Simple Current Mirror with Level Shifting Since the drain can be V T less than the gate, the drain could be biased to reduce the minimum input voltage as illustrated. i in I Bias V EB Q3 i out M1 M2 Fig Lecture 350 Low Voltage Op Amps (3/26/02) Page A LowVoltage Current Mirror with Wide Input and Output Swings The current mirror below requires a power supply of V T 3V ON and has a V in (min) = V ON and a V out (min) = 2V ON (less for the regulated cascode output mirror). I 1 I B I B I B I 2 I 1 I B1 I B2 I B1 I 2 i in i out i in i out M3 M4 M6 M7 or M3 M4 M6 M5 M7 M1 M2 M1 M5 I B2 M2 Fig A
8 Lecture 350 Low Voltage Op Amps (3/26/02) Page Bandgap Topologies Compatible with Low Voltage Power Supply I PTAT V Ref IV BE I NL I PTAT IV BE V Ref V PTAT V Ref I PTAT R2 V BE I NL R3 R1 Voltagemode bandgap topology. Currentmode bandgap topology. Voltagecurrent mode bandgap topology. Fig Lecture 350 Low Voltage Op Amps (3/26/02) Page Method of Generating Currents with VBE and PTAT Temperature Coefficients M7 M8 I VBE M6 M3 Q1 V BE R 3 M4 Q2 I VBE Buss I PTAT Buss I PTAT R 1 V PTAT R 2 M5 I PTAT R 4 V out1 M9 I VBE V out2 Figure 7.615A V out1 = I PTAT R 2 = V PTAT V BE R 1 R 2 = V PTAT R 2 R V out2 = I VBE R 4 = 4 R 3 R 4 = V BE R 3 R 1
9 Lecture 350 Low Voltage Op Amps (3/26/02) Page Technique for Canceling the Bandgap Curvature 1:K 2 1:K 3 M1 M2 M3 M4 I 2 I NL K 3 I NL Current M2 active M3 off K 2 I VBE M2 sat. M3 on K 1 I PTAT I I VBE K 1 I NL PTAT Temperature Circuit to generate nonlinear correction term, I NL. Illustration of the various currents. Fig , K 2 I VBE > K 1 I PTAT I NL = K 1 I PTAT K 2 I VBE, K 2 I VBE < K 1 I PTAT The combination of the above concept with the previous slide yielded a curvaturecorrected bandgap reference of 0.596V with a TC of 20ppm/C from 15C to 90C using a 1.1V power supply. In addition, the line regulation was 408 ppm/v for V and 2000 ppm/v for V. The quiescent current was 14µA. G.A. RinconMora and P.E. Allen, A 1.1V CurrentMode and PiecewiseLinear CurvatureCorrected Bandgap Reference, J. of SolidState Circuits, vol. 33, no. 10, October 1998, pp Lecture 350 Low Voltage Op Amps (3/26/02) Page LowVoltage Op Amp using Classical Techniques ( 2V T ) M3 M4 V T V ON M15 V ON V T 2V ON M13 M12 V T V ON M7 M11 R I Bias M1 M2 M6 1 V ON v C c in M5 M8 M9 M14 M16 M10 C L v out Clever use of classical techniques. Balanced inputs. Fig
10 Lecture 350 Low Voltage Op Amps (3/26/02) Page Example 7.61 Design of a LowVoltage Op Amp using the Previous Topology Use the parameters of Table 3.12 to design the op amp above to meet the specifications given below. = 2V V icm (max) = 2.5V V icm (min) = 1V V out (max) = 1.75V V out (min) = 0.5V GB = 10MHz Slew rate = ±10V/µs Phase margin = 60 for C L = 10pF Solution Assuming the conditions for a twostage op amp necessary to achieve 60 phase margin and that the RHP zero is at least 10GB gives C c = 0.2C L = 2pF The slew rate is directly related to the current in M5 and gives I 5 = C c SR = 2x = 20µA We also know the input transconductances from GB and C c. They are given as g m1 = g m2 = GB C c = 20πx10 6 2x1012 = µS Knowing the current flow in M1 and M2 gives the W/L ratios as W 1 L 1 = W 2 g m1 2 L 2 = 2K N (I 1 /2) = (125.67x106) x106 10x106 = 7.18 Lecture 350 Low Voltage Op Amps (3/26/02) Page Example 7.61 Continued Next, we find the W/L of M5 that will satisfy V icm (min) specification. V icm (min) = V DS5 (sat) V GS1 (10µA) = 1V This gives V DS5 (sat) = 1 V DS5 (sat) = = = = V 2 I 5 K N (W 5 /L 5 ) W 5 L 5 = (0.0909)2 = 44 The design of M3 and M4 is accomplished from the upper input common mode voltage: V icm (max) = V SD3 (sat)v TN = 2V SD3 (sat)0.75 = 2.5V Solving for V SD3 (sat) gives 0.25V. Assume that the currents in M6 and M7 are 20µA. This gives a current of 30µA in M3 and M4. Knowing the current in M3 (M4) gives 2 30 V SD3 (sat) 50 (W 3 /L 3 ) W 3 L = W L 4 (0.25) = Next, using the V SD (sat) = V ON of M3 and M4, design M10 through M12. Let us assume that I 10 = I 5 = 20µA which gives W 10 /L 10 = 44. R 1 is designed as R 1 = 0.25V/20µA = 12.5kΩ. The W/L ratios of M11 and M12 can be expressed as W 11 L 11 = W 12 2 I 11 L 12 = K P V SD11 (sat) 2 = (0.25) 2 = 12.8
11 Lecture 350 Low Voltage Op Amps (3/26/02) Page Example 7.61 Continued Since the sourcegate voltages and currents of M6 and M7 are the same as M11 and M12 then the W/L values are equal. Thus W 6 /L 6 = W 7 /L 7 = 12.8 M8 and M9 should be as small as possible to reduce the parasitic (mirror) pole. However, the voltage drop across M4, M6 and M8 must be less than the power supply. Using this to design the gatesource voltage of M8 gives V GS8 = 2V ON = 2V = 1.5V Thus, W 8 L 8 = W 9 L 9 = 2 I 8 K N V DS8 (sat)2 = (0.75) 2 = Because M8 and M9 are small, the mirror pole will be insignificant. The next poles of interest would be those at the sources of M6 and M7. Assuming the channel length is 1µm, these poles are given as p 6 g m6 C GS6 = 2K P ' (W 6 /L 6 ) I x10 (2/3) W 6 L 6 C ox = 6 (2/3) x10 15 = 7.59x10 9 rads/sec which is about 100 times greater than GB. Finally, the W/L ratios of the second stage must be designed. We can either use the relationship for 60 phase margin of g m14 = 10g m1 = µS or consider proper mirroring between M9 and M14. Lecture 350 Low Voltage Op Amps (3/26/02) Page Example 7.61 Continued Substituting µS for g m14 and 0.5V for V DS14 in W/L = g m /(K N ' V DS (sat)) gives W 14 /L 14 = which gives I 14 = 314µA. The W/L of M13 is designed by the necessary current ratio desired between the two transistors and is W 13 L 13 = I 13 I 12 I 12 = = 201 Now, check to make sure that the V out (max) is satisfied. The saturation voltage of M13 is 2 I 13 V SD13 (sat) = K P ' (W 13 /L 13 ) = = 0.25V which exactly meets the specification. For proper mirroring, the W/L ratio of M14 is, W 9 L 9 = I 9 W 14 I 14 L 14 = 1.46 Since W 9 /L 9 was selected as 1, this is close enough. The parameters are g ds7 = 1µS, g ds8 = 0.8µS, g ds13 = 15.7µS and g ds14 = 12.56µS. Therefore small signal voltage gain is (R I r ds9 because M7 is part of a cascode conf.) v out v in g m1 g ds9 g m g ds13 g ds14 = = = 3,103V/V The power dissipation, including I bias of 20µA, is 708µW. The minimum power supply voltage is V T 3 V 1.5V if V T = 0.7V and V 0.25V.
12 Lecture 350 Low Voltage Op Amps (3/26/02) Page A 1Volt, TwoStage Op Amp Uses a bulkdriven differential input amplifier. IBias =1V 6000/6 6000/6 3000/6 6000/6 M8 M9 M10 M /2 v in v in C c =30pF M1 M2 R z =1kΩ Q5 Q6 M3 M4 400/2 400/2 400/2 M12 v out C L M7 Fig Lecture 350 Low Voltage Op Amps (3/26/02) Page Performance of the 1Volt, TwoStage Op Amp Specification ( =0.5V, V SS =0.5V) Measured Performance (C L = 22pF) DC openloop gain 49dB (V icm mid range) Power supply current 300µA Unitygainbandwidth (GB) 1.3MHz (V icm mid range) Phase margin 57 (V icm mid range) Input offset voltage ±3mV Input common mode voltage range 0.475V to 0.450V Output swing 0.475V to 0.491V Positive slew rate 0.7V/µsec Negative slew rate 1.6V/µsec THD, closed loop gain of 1V/V 60dB (0.75Vpp, 1kHz sinewave) 59dB (0.75Vpp, 10kHz sinewave) THD, closed loop gain of 1V/V 59dB (0.75Vpp, 1kHz sinewave) 57dB (0.75Vpp, 10kHz sinewave) Spectral noise voltage density 367nV/ 1kHz 181nV/ 10kHz, 81nV/ 100kHz 444nV/ 1MHz Positive Power Supply Rejection 61dB at 10kHz, 55dB at 100kHz, 22dB at 1MHz Negative Power Supply Rejection 45dB at 10kHz, 27dB at 100kHz, 5dB at 1MHz
13 Lecture 350 Low Voltage Op Amps (3/26/02) Page Further Considerations of the using the Bulk Current Driven Bulk The bulk can be used to reduce the threshold sufficiently to permit low voltage applications. The key is to keep the substrate current confined. One possible technique is: G S B G S B I E Gate n;; p p D I BB Reduced Threshold MOSFET D I BB I CD Parasitic BJT Problem: Want to limit the BJT current to some value called, I max. Therefore, I max I BB = β CS β CD 1 I CS nwell Source Drain p substrate Layout Fig T. Lehmann and M. Cassia, 1V Power Supply CMOS Cascode Amplifier, IEEE J. of SolidState Circuits, Vol. 36, No. 7, 2001 Lecture 350 Low Voltage Op Amps (3/26/02) Page CurrentDriven Bulk Technique Continued Bias circuit for keeping the I max defined independent of BJT betas. VBias1 M7 I S,E M3 Note: I D,C = I DC I D I S,E = I D I E I R M6 M8 I D,C M5 R I BB M1 M4 M2 VBias2 The circuit feedback causes a bulk bias current V SS I BB and hence a bias voltage V BIAS such that I S,E = I D I BB (1β CS β CD ) I R regardless of the actual values of the β s. Use V Bias1 and V Bias2 to set I D,C 1.1I D, I S,E 1.3I D and I R 0.1I D which sets I max at 0.1I D. For the circuit to work, V BE < V TN I R R and V TP V DS (sat) < V TN I R R If V TP > V TN, then the level shifter I R R can be eliminated. I R VBias Fig
14 Lecture 350 Low Voltage Op Amps (3/26/02) Page A 1Volt, FoldedCascode OTA using the CurrentDriven Bulk Technique VBiasP M11 M12 M6 C x v in M1 M2 M13 M17 M9 M10 v out M7 M8 C L VBiasN M3 M5 M4 M14 M15 M16 V SS Fig Transistors with forwardbiased bulks are in a shaded box. For large common mode input changes, C x, is necessary to avoid slewing in the input stage. To get more voltage headroom at the output, the transistors of the cascode mirror have their bulks current driven. Lecture 350 Low Voltage Op Amps (3/26/02) Page A 1Volt, FoldedCascode OTA using the CurrentDriven Bulk Technique Continued Experimental results: 0.5µm CMOS, 40µA total bias current (C x = 10pF) Supply Voltage 1.0V 0.8V 0.7V Commonmode input range 0.0V0.65V 0.0V0.4V 0.0V0.3V High gain output range 0.35V 0.75V 0.25V0.5V 0.2V0.4V Output saturation limits 0.1V0.9V 0.15V 0.65V 0.1V0.6V DC gain 62dB69dB 46dB53dB 33dB36dB GainBandwidth 2.0MHz 0.8MHz 1.3MHz SlewRate 0.5V/µs 0.4V/µs 0.1V/µs (C L =20pF) Phase margin (C L =20pF) The nominal value of bulk current is 10nA gives a 10% increase in differential pair quiescent current assuming a BJT β of 100.
15 Lecture 350 Low Voltage Op Amps (3/26/02) Page SUMMARY Integrated circuit power supplies are rapidly decreasing (today 23Volts) Classical analog circuit design techniques begin to deteriorate at 1.52 Volts Approaches for lower voltage circuits: Use natural NMOS transistors (V T 0.1V) Drive the bulk terminal Forward bias the bulk Use depeletion devices The dynamic range will be compressed if the noise is not also reduced Fortunately, the threshold reduction continues to allow the techniques of this section to be used in today s technology
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