Solid State Devices & Circuits. 18. Advanced Techniques

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1 ECE 442 Solid State Devices & Circuits 18. Advanced Techniques Jose E. Schutt-Aine Electrical l&c Computer Engineering i University of Illinois jschutt@emlab.uiuc.edu 1

2 Darlington Configuration - Popular BJT combination - Composite transistor with = Can be used as the cascade of two CC 2

3 Darlington Voltage Follower R 1 r 1 r R in e1 2 e2 E / 1 e1 sig 1 Rout R E // re v v out sig R E r e2 r r R R E R e1 sig / 1 3

4 Darlington Voltage Follower Darlington follower presents high input impedance 4

5 Darlington Voltage Follower Input impedance R 1 r1 2 1 r 2 R in e e E Output t impedance R R // r Voltage gain: A MB out E e 2 R r R /( 1) 1 e1 sig RE re2 re 1Rsig /( 1 1) /( 2 1) E 5

6 Op Amp Architecture Concepts - Many op amps consist of 3 amplifying stages - The first stage is always a high-gain differential stage - The second stage has moderate value of voltage gain - The last stage is often a buffer stage with high current gain and voltage gain near unity - The high-frequency poles of each stage introduce phase shift at higher frequenciesmay lead to oscillations 6

7 Op Amp Specifications Specifications - Input Offset Voltage (V os ) - Input Offset Voltage Drift (TCV os ) - Input Bias Current (I B ) - Input Offset Current (I os ) - Common-Mode Input Voltage Range (CMVR) - Common-Mode Rejection Ratio (CMRR) - Power Supply Rejection Ratio (PSRR) 7

8 CMOS OP Amp Example In the differential amplifier shown, Q 1 and Q 2 form the differential pair while the current source transistors Q 4 and Q 5 form the active loads for Q 1 and Q 2 respectively. The dc bias circuit that establishes an appropriate dc voltage at the drains of Q 1 and Q 2 is not shown. The following specifications are desired: differential gain A d = 80V/V, I REF = 100 A, the dc voltage at the gates of Q 6 and Q 3 is +1.5V; the dc voltage at the gates of Q 7, Q 4 and Q 5 is 1.5V. The technology available is specified as follows: n C ox =3 p C ox = 90A/V 2 ; V tn = V tp =0.7V, V An = V Ap = 20V. Specify the required value of R and the W/L ratios for all transistors. Also, specify I D and V GS at which each transistor is operating. For dc bias calculations, you may neglect channel-length modulation. Fill in the entries in the table provided to show your results. 8

9 CMOS OP Amp Example 9

10 CMOS OP Amp Example 1.5 ( 1.5) 3V I REF 100 A R 30k R 0.1mA Drain currents are determined by symmetry and inspection V GS values are also determined by inspection for all transistors except Q 1 and Q 2. To determine V GS for Q 1 and Q 2, we do the following: the equivalent load resistance will consist of r o1 in parallel with r o4 for Q 1 and r o2 in parallel with r o5 for Q 5. Since the r o s are equal, this corresponds to r o /2. We have: ro 2Ad 280 gm Ad gm 0.4 ma / V 2 r 400 k o 10

11 CMOS OP Amp Example g m 2ID 2ID Vov V g 0.4 ov Take polarity into account for PMOS m 0.25 VGS1, VT 0.95V To find W/L ratios, use 2 2 D I W ( ) W I D Cox VGS VT 2 2 L L C ( V V ) ox GS T taking into account PMOS and NMOS devices separately 11

12 CMOS OP-AMP DESIGN TABLE Q Units 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 C ox A/V 2 I D A V GS V W/L

13 2-Stage CMOS Op Amp 13

14 2-Stage CMOS Op Amp Two-stage configuration with two power supplies which can range from +/- 2.5 V for 0.5 m technology to +/- 0.9 V for 0.18 m technology. I REF is generated either externally or using on-chip CKT. Current mirror formed by Q 5 -Q 8 supplies differential pair Q 1 -Q 2 with bias current. The W/L of Q 5 is selected to control I. The diff pair is actively loaded by current mirror Q 3 -Q 4 14

15 2-Stage CMOS Op Amp Second stage is Q 6 which is a CS amplifier for which Q 7 is the current source. A capacitor C C is included for negative feedback to enhance the Miller effect through Q 6 compensation This op amp does not have a low output impedance and is thus not suited for driving a lowimpedance load Let I 90 A, V V, V V REF tn tp C 160 A/ V, C 40 A/ V 2 2 n ox p ox 15

16 2-Stage CMOS Op Amp V for all devices 10 V, V V 2.5V A DD SS Voltage Gain A g r r 1 g m 1 o 2 // o 4 First stage: Since Q 8 and Q 5 are matched, I = I REF, Q 1, Q 2, Q 3 and Q 4 will have I/2 =45 A. A I Q7 =I REF = 90 A = I Q6 Let V GS -V T = V ov (overdrive voltage) 16

17 2-Stage CMOS Op Amp 1 2 From I C W / L V 2 D ox ov We find V ov for each transistor. Transconductance is: g m 2 I D V ov r o V I A D 17

18 2-Stage CMOS Op Amp Voltage Gain A g r r 1 m 1 o 2 // o 4 Gain for first stage: A // / V V A g r r 2 m 6 o 6 // o 7 Gain for second stage: A // / V V Overall dc open loop gain is (-33.3)(-33.3) 3)( 3) = 1109 V/V 20 log(1109) = 61 db 18

19 2-Stage Op Amp Design Table Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 20/0.8 20/0.8 5/0.8 5/0.8 40/0.8 W/L 10/0.8 40/0.8 40/0.8 I D (A) V ov (v) V GS (v) g m (ma/v) r o (k)

20 2-Stage Op Amp Frequency Response Incremental Circuit G m1 g m1 g m2 R r // r, C C C C C C 1 o 2 o 4 1 gd 4 db 4 gd 2 db 2 gs 6 20

21 2-Stage Op Amp Frequency Response G g m2 m6 R r // r, C C C C C 2 o6 o7 2 db6 db7 gd7 L C is the load capacitance (usually large) C C L 2 1 G G sc RR Vo V 1sAs B id m1 m2 C

22 Cascode Current Mirror In addition to diode- connected transistor Q 1, Q 4 is used to provide suitable bias gate voltage for Q 3 Ro gm3ro3ro2 The cascode mirror current has a very high output impedance 22

23 MOS Folded Cascode Amp 23

24 MOS Folded Cascode 1. CS transistor with CG transistor of opposite polarity 2. Q 1 and Q 2 for the differential input pair and act as CS amplifiers 3. Q 3 and Q 4 are the cascode transistors with their gates tied to incremental ground 4. Output resistance of current source needed to be high use cascode current mirror 5. Transistors Q 5 -Q 8 make up cascode current mirror 6. Selecting I B =I forces all transistors to operate at current I/2 24

25 MOS Folded Cascode Amp 25

26 Input Common-Mode Range Connect both input together to a source V ICM. Q 1 and Q 2 operate in saturation at all timesv ICMmax should be V tn above voltage at drains of Q 1 -Q 2 V V V V ICM max DD OV 9 tn This value can be larger than V DD significant improvement over the case of the 2-stage circuit. Minimum value of V ICM is V V V V V ICM min SS OV11 OV1 tn 26

27 Input Common-Mode Range Value of V ICMmin is not sufficiently low. V BIAS3 should be selected to provide required current I while operating Q 11 at low overdrive voltage V V V V V V V V SS OV 11 OV 1 tn ICM DD OV 9 tn To maximize the allowable positive swing of v o (and V ICMmax ), select the value of V BIAS1 so that Q 10 operates at the edge of saturation V V V V BIAS1 DD 0V 10 SG4 27

28 Output Voltage Swing The upper limit of v o will be v V V V omax DD OV 10 OV 4 This is two overdrive voltages below V DD not good. However, lowest possible v o is when Q 6 reaches the edge of saturation v V V V V omin SS OV7 OV5 tn This is two overdrive voltages plus a threshold h voltage above V SS. Can be alleviated by using modified mirror circuit. 28

29 MOS Folded Cascode Amp Small-Signal Incremental Circuit 29

30 Voltage Gain Amp is a transconductance amplifier with an infinite input resistance a transconductance G m and an output resistance R o 2( I / 2) Gm gm 1 gm 2 V Output resistance is R R // R o o4 o6 I V OV1 OV1 R o4 is the output resistance of the CG transistor Q 4 R g r r // r o4 m4 o4 o2 o10 30

31 Voltage Gain R g r r R o6 is given by o6 m6 o6 o8 From which R g r r // r // g r r o m 4 o 4 o 2 o 10 m 6 o 6 o 8 The DC open-loop gain is A v = G m R o A g g r r // r // g r r v m 1 m 4 o 4 o 2 o 10 m 6 o 6 o 8 31

32 Output Impedance Output impedance of folded cascode amp is in the order of R o g r 2 m o This is high. However, with negative feedback using voltage sampling, it becomes R of 1/ g m1 which is much lower 32

33 Frequency Dependence 1. Cascode configuration has excellent highfrequency response 2. The first two poles are at very high frequencies 3. Primary purpose of op amp is to feed highly capacitive loads pole at the output becomes dominant. V V G R 1 sc R o m o id L o 33

34 Frequency Dependence The dominant pole has a frequency f P given by f P 1 2C R C L o And the unity-gain frequency f t is given by f G R f t m o P G m 2C L 34

35 Folded Cascode Design Design a folded with I = 200 A, I B = 250 A, and V ov = 0.25 V for all devices. Use k n =100 A/V 2, k p =40 A/V/ 2, V A = 20 V/m, V DD = V SS = 2.5 V, and V t =0.75 V. All devices have L=1 m. use C L = 5 pf. Find I D, g m, r o and W/L for all transistors From I and I B, we can determine I D for each B, D transistor.the transconductance is given by: g m 2I D 2I D V 0.25 ov 35

36 Folded-Cascode Amp Design and the output resistance from r o V I A D 20 I The W/L ratio for the devices is given by: D W L i 2 I Di 2 ' ov k V 36

37 Folded-Cascode Amp Design Table Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 Q 9 Q 10 Q 11 ID (A) g m (ma/v) r o (k) W/L

38 Folded-Cascode Amp Design Note that for all transistors, gmro V GS 160 V / V V Input common-mode range is 1.25V V 3V ICM Output voltage swing is 1.25V v 2 V o 38

39 Folded-Cascode Amp Design Calculate R o4 R o // M Calculate l R o6 Ro6 gm6 ro6 ro M The output resistance R o can then be found as R R // R 6.4 M o o 4 o 6 39

40 Folded-Cascode Amp Design Voltage gain is 3 6 A 08 v GmRo V / V Unity gain bandwidth f t 3 Gm C C L Dominant-pole frequency is 25.5 MHz f P ft 25.5 MHz A 5120 A v 5 khz 40

41 Widlar Current Source A resistor R E is included in the emitter lead of Q 2 I R O E T I REF V ln IO The Widlar circuit provides small constant current using relatively small resistors savings in chip area 41

42 Design of Op Amps 1. Designer starts with building blocks whose performance can be analyzed to a first order approximation by hand 2. This step provides insight to the designer as the design of the circuit develops 3. At some point designer must turn to computer analysis programs such as SPICE. This will provide speed and accuracy to the design process 42

43 The 741 Op Amp 1. Three-stage amplifier: differential input, single-ended high-gain stage and output buffering stage 2. Several transistors, t few resistors and only one capacitor 3. General-purpose op amp that requires two power supplies 43

44 741 Op Amp 44

45 General Strategy for Analyzing the Identify the individual stages with their respective transistors. For each stage determine the role of the transistors 2. Perform a stage by stage DC analysis of the circuit. Determine the bias points and mode of operation o for each transistor. sto 3. Perform the small-signal analysis of each stage. Develop an incremental model model and find the parameters of the model 45

46 General Strategy for Analyzing the 741 (cont ) 1. For each equivalent circuit, calculate gain, input and output resistances. 2. Determine overall gain of circuit as well as input and output t impedance 3. Perform high-frequency analysis of circuit to get an estimate for the poles. 4. Use SPICE to fine tune analysis 46

47 741 Op Amp 47

48 741 Op Amp Bias Strategy I REF is generated by mirror Q 11 -Q 12 and R 5 Q 8 -Q 9 current mirror Q 13 double-collector lateral pnp ppdevice; Q 12 and Q 13 form a two-output current mirror Q 13B provides bias current Q 17 Q 13A provides bias current for the output stage Q 18 and Q 19 provide V BE drops to Q 14 and Q 20 48

49 741 Op Amp Input Stage Input Stage Transistors Q 1 through Q 7 make up the input stage Bias is performed by transistors Q 8, Q 9 and Q 10 Q 1 and Q 2 form a differential emitter-follower pair Q 3 and Q 4 form a differential common-base pair Q 5, Q 6 and Q 7 form the load/current mirror to the input stage Q 3 and Q 4 also perform dc level shifting to allow both positive and negative swings 49

50 741 Op Amp Second Stage Second Stage Transistors Q 16, Q 17 and Q 13B make up the intermediate stage Q 16 acts as an emitter follower Q 17 is a common emitter amplifier Output of second stage is at collector of Q 17 Capacitor C C provides Miller compensation Capacitor C C occupies large area in chip 50

51 Amplifier - Class B Operation Class B Amp Arrangement saves power Transistors turn on only when signal is applied npn sources current and pnp sinks current Both transistors are cutoff when v I = 0crossover distortion 51

52 741 Op Amp Output Stage Output Stage Class AB operation that reduces crossover distortion Transistors Q 14 and Q 20 make up output t stage Q 18 and Q 19 provide bias to Q 14 and Q 20 52

53 741 Op Amp DC Analysis NPN I A V V 14 : S 10, 200, A 125 PNP I A V V 14 : S 10, 50, A 50 Q 13, Q 14 and Q 20 are nonstandard devices. Q 13 has Q 13A and Q 13B I A, I A SA SB I REF VCC VEB 12 VBE11 ( VEE ) R R ma 53

54 741 Op Amp Input Stage DC Analysis Input Stage Q 11 & Q 10 are a Widlar current source V V I R BE11 BE10 C10 4 ( Assume I S 10 IS 11 ) I V ln REF T IC10R4 I I C10 C10 19 A Transistors Q 1 through Q 4, Q 8 and Q 9 form a negative feedback loop that stabilizes the value of I 54

55 741 Op Amp Input Stage DC Analysis I C 6 I I C5 I 2I V IR 6 2 I 7 7 BE C IE R N 3 V BE 6 VT ln I I S 55

56 741 Op Amp Output Stage DC Bias Output Stage Q 13 delivers a current of 0.25 I REF Class AB operation IC23 IE IREF 180 A I E A I C A IC A 56

57 i e Small-Signal Analysis Input Stage vi 4r e r e is the emitter resistance of Q 1 -Q 4 r e VT 25 mv k I 9.5 A R 4 1 r id N e For N = 200, we obtain R id = 2.1 M 57

58 Small-Signal Analysis Input Stage i o G m1 2 i i v o i e 2r e re 2.63 k 1 Gm1 1/ 5.26 ma/ V 58

59 Small-Signal Analysis Input Stage Output resistance of input stage. Seen from collector of Q 6 1 // R r 1 g R // r o o m E R E =r e =2.63 k and r o =V A /I where V A =50 V and I=9.5 Ar o =5.26 M 59

60 Input Stage Incremental Model Develop equivalent circuit for input stage 60

61 Small-Signal Analysis Second Stage 61

62 Second Stage Incremental Model Develop equivalent circuit for second stage 62

63 Small-Signal Analysis Second Stage Input Resistance R i2 is found by inspection: Ri 1 r e R 1 re R Ri2 4 M 63

64 Small-Signal Analysis Second Stage Transconductance i c17 The transconductance G m2 is the output current to input voltage v vb7 r R e17 8 v v b17 12 R 9// R i 17 R // R r 9 i17 e16 R 1 r R i17 17 e17 8 G m2 i c17 v i ma/ V 64

65 Small-Signal Analysis Second Stage Output Resistance Find resistance looking into into output terminal R R // R o2 o13b o17 First component R r k o13b o13b 90.9 Second component is found looking into collector of Q 17 R 787 k R 2 81 o o k 65

66 Small-Signal Analysis Output Stage Characteristics AB class circuit Driven by Q 17 Q 23 is follower Q 18 & Q 19 providing bias Q 14 & Q 20 are output transistors 66

67 Output Voltage Limits Output Stage Maximum positive voltage limited by saturation of Q 13 v V V V omax CC CEsat BE14 About 1V below V CC Minimum output voltage limited by saturation of Q 17 v V V V V o min EE CEsat EB 23 EB 20 About 1.5 V above -V EE 67

68 Output Stage Incremental Circuit Construct model v G R v o2 m2 o2 i2 G m2 =6.5 ma/v and R o2 =81 k 68

69 Output Stage Incremental Model Finding R in3 Assume Q 20 to have 5 ma Resistance looking into base of Q 20 is about 20 R L Assume 20 =50 and R L =2 kresistance into Q 20 =100 k Q 18 &Q 19 providing bias Place above resistance in parallel with resistance of Q 13A (about 280 k) [resistance of Q 18 -Q 19 network small and can be neglected] Assuming 23 =50 R 100 k // 280 k M in

70 Output Stage Incremental Model Looking into emitter of Q 23 R R r o2 o23 e Using R o2 =81 k, 23 =50, r e23 =25/0.18 = 139 gives R o23 = k R out R o23 re For = 50, R out=34 70

71 Overall Gain vo vi2 vo2 vo vi vi vi2 vo2 vo R L Gm 1 Ro 1// R12 Gm2Ro2 Gvo3 vi RL Rout vo A o ,147 V / V vi v o Ao db v i 71

72 741 Op Amp - Frequency Response Miller capacitance due to C C between the base of Q 16 and ground is C C 1 A in C Resistance between the base of Q 16 and ground is R R // R 6.7 M// 4 M t o1 i2 2 Dominant pole is at Unity gain-bandwith is f P 1 2C R in t 4.1 Hz f A0 f3 243, MHz t db 72

73 Conclusion - Design of Op Amps 1. Designer starts with building blocks whose performance can be analyzed to a first order approximation by hand 2. This step provides insight to the designer as the design of the circuit develops 3. At some point designer must turn to computer analysis programs such as SPICE. This will provide speed and accuracy to the design process 73

ECE 442 Solid State Devices & Circuits. 15. Differential Amplifiers

ECE 442 Solid State Devices & Circuits 15. Differential Amplifiers Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 442 Jose Schutt Aine 1 Background