ECEN474: (Analog) VLSI Circuit Design Fall 2011

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Phoebe Greer
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1 ECEN474: (Analog) VLSI Circuit Design Fall 20 Lecture 22: Output Stages Sebastian Hoyos Analog & Mixed-Signal Center Texas A&M University

2 Agenda Output Stages Source Follower (Class A) Push-Pull (Class B) Push-Pull w/ Small Quiescent Current (Class AB) 2

3 OpAmps and OTAs OpAmp OTA High voltage gain High input impedance Voltage source output (low impedance) High voltage gain High input impedance Current source output (high impedance) 3

4 Three-Stage OpAmp i- i+ o Differential input stage Amplifies differential input Sets specs such as G m, CMRR, and slew rate Second gain stage Provides additional gain Often used to provide Miller compensation Output stage Power Amplifier Large current gain and near unity voltage gain Small output impedance 4

5 Buffered OTA = Operational Voltage Amplifier (OPAMP) ELEN-474 M 2 M 2 M 3 i02 i 0 M M 2i 0 VDD i0 i0 R C CM v d -v d A VDC M 4 v 0 v + v - g m (v + -v - ) SIMPLE MACROMODEL: O R v y C+(+g m3 r o3 )CM r 0 A 2 A 3 (v y ) IB IB2 IB3 Internal pole 2 nd Stage & Buffer AVDC g mr A2 A VSS 3 A2 g m 3ro 3 A 0. p GBW p2 3 5 GBW g C m M 0 / g m 4 v out R out r Notice that load capacitors must satisfy the following condition, otherwise phase margin is not good enough GBW r 0 C L Jose Silva-Martinez -5- Texas A&M University

6 Source Follower (Class A) Output Stage [Gray] Voltage gain close to Low output resistance DC level shift of V GS Class A output stage transistors conduct current over an entire input cycle A dc m m L (Optimisti gm go gmb go2 g L gm R c) L R out g g g g g g R g m o mb o2 m 6

7 Source Follower (Class A) Transfer Characteristic V o V i V T 2 I C n Q ox Vo R L W L [Gray] Maximum V o If V in V DD, then Maximum V o = V DD -V GS Output transistors remain in saturation up to V o = V DD -V DSAT if V in swings up to V DD +V T Minimum V o For small R L (heavy load), M gets cutoff and V o -I Q R L For large R L (light load), M2 will go into triode region at V DD +V DSAT2 7

8 Source Follower (Class A) Power Efficiency Assuming a sinusoidal output voltage V o V m sint The power delivered to the load at the signal frequency is Vm 2 2 Vm Pac RL 2RL The average power consumed by the source follower is Pav IQ VDD I Q V DD 2IQVDD The output stage power efficiency i is 2 Pac Vm Peff Pav 4RLIQVDD Maximum m power efficiency is achieveded when the output t VDD amplitude approaches VDD and IQ is designed to be R L Max Peff or 25% (not that good!) 4 2 8

9 Super Buffer Output Stage [Silva] R out g m2 A v 9

10 Push-Pull Source Follower (Class B) Output Stage Class B output stages improve power efficiency by operating at zero quiescent current However, if - V TP V in V TN, then no output signal 0

11 Push-Pull Source Follower (Class B) Crossover Distortion [Sedra]

12 Push-Pull Source Follower (Class B) Power Efficiency Assuming a sinusoidal output voltage V o V m sint The power delivered to the load at the signal frequency is Vm 2 2 Vm Pac RL 2RL The current consumed by the push - pull stage from the two supplies Vm consists of half - sine wave of peak amplitude R L Vm The average current will be RL V 2 m Vm VmVDD P av VDD VDD RL RL RL The output stage power efficiency is Pac Vm Peff Pav 4V DD Maximum power efficiency is achieved when the output amplitude approaches V DD Max Peff or 78.5% (much better!) 4 2 2

13 Push-Pull w/ Small Quiescent Current (Class AB) Output Stage [Gray] Power efficiency of the Class-B output stage is great, but the crossover distortion is a major issue Solution to the crossover distortion is to bias the transistors into conduction at a low quiescent current Level-shift transistors M4 and M5 are sized such that VGS and VGS2 are slightly l larger than their threshold voltages 3

14 Push-Pull w/ Small Quiescent Current (Class AB) Output Swing Range A drawback of the CMOS Class AB output stage is the limited output swing range Maximum V o set by M source follower V o V DD - V DSAT3 -V GS Minimum Vo set by M2 source follower V o -V SS +V DSAT6 +V SG2 4

15 Next Time Analog Applications OTA-C Filters Variable-Gain Amplifiers Switch-Cap Filters, Broadband Amplifiers Bandgap Reference Circuits Distortion 5

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018 ECEN474/704: (Analo) VLSI Circuit Desin Sprin 08 Lecture 6: Output Staes Sam Palermo Analo & Mixed-Sinal Center Texas A&M University Announcements Project eport Due May Email it to me by 5PM Exam 3 is