Lecture 14. FET Current and Voltage Sources and Current Mirrors. The Building Blocks of Analog Circuits - IV

Transcription

1 Lecture 4 FET Current and oltage s and Current Mirrors The Building Blocks of Analog Circuits n this lecture you will learn: Current and voltage sources using FETs FET current mirrors Cascode current mirror Double Wilson current mirror Active biasing schemes Questions: Motivation Are there better ways to realize onchip current sources to bias circuits? Are there good ways to generate onchip voltage levels to bias circuits? Using large resistors too often is not a good idea in integrated chips BAS B B

2 Characteristics of deal Current s and Sinks deal Current s: = One can have any voltage at the at the output terminals of an ideal current source and the current delivered will remain constant The output resistance of an ideal current source is infinity deal Current Sinks: = One can have any voltage at the at the output terminals of an ideal current sink and the current sinked will remain constant The output resistance of an ideal current sink is infinity Characteristics of deal oltage s deal oltage s: r ov =0 r ov One can draw any current from an ideal voltage source and the voltage at the output terminals will remain constant The output resistance of an ideal voltage source is zero Nondeal oltage s: r ov r ov 0 slope = r ov

3 A FET oltage : Large Signal Analysis Assume for the moment that we have a current source f > TN : REF D REF D TN k n REF k n Slope d d TN g m if n k n n TN TN The line can be made more vertical and the voltage source more ideal by increasing the value of g m Nondeal oltage slope = r ov A FET oltage : Large Signal Analysis REF TN W LnCox d d gm W ncox TN L D ncreasing (W/L) TN f the (W/L) ratio of the FET is made very large, the output voltage is fixed at approximately TN for all values of the current drawn from the source (provided < ) 3

4 A FET oltage : Small Signal Analysis (deal) Small signal Small signal model Need to find the resistance r ov the output terminals looking into from r ov A FET oltage : Small Signal Analysis i g i d v gs g m v gs 0 g mb v bs r o Base v bs Small signal model Need to find the resistance r ov the output terminals looking into from r ov 4

5 A FET oltage : Small Signal Analysis i g i d g m r o r ov Small signal resistance looking into the voltage source is: rov gm ro roc gm Base v bs Generally small if g m is large We have a voltage source that: Gives a DC voltage adjustable by changing the value of, and Has an incremental or small signal resistance r ov approximately equal to /g m (which can be pretty small) R D A FET oltage : Simplest mplementation of f > TN : DD k n D TN R R DD TN TN k R kn knr n R Slope when R is much larger than /g m d gm kn TN d Slope d d R TN f the (W/L) ratio of the FET is made very large and R is much larger than /g m, the output voltage is fixed at approximately TN for all values of the current drawn from the source provided < ( TN )/R 5

6 FET oltage s One can produce multiple voltage levels from the same structure using NMOS FETs, PMOS FETs, and combination of both NMOS and PMOS FETs M 3 REF TN kn REF TN kn But need to be careful about the small signal resistances associated with each voltage output! FET oltage s: Small Signal Analysis i d v gs g m v gs r o r ov r ov v gs g m v gs r o i d Find the resistance looking into the first voltage source assuming the second one is incrementally open (why?) 6

7 FET oltage s: Small Signal Analysis i d g m r o r ov r ov g m r o Find the resistance looking into the first voltage source assuming the second one is incrementally open (why?) FET oltage s: Small Signal Analysis i d g m r o r ov g m r ov rov gm gm Small Find the resistance looking into the first voltage source assuming the second one is incrementally open (why?) 7

8 FET oltage s: Small Signal Analysis i d v gs g m v gs r o r ov r ov Then find the resistance looking into the second voltage source assuming the first one is incrementally open (why?) v gs g m v gs r o i d rov Small gm D REF A FET Current Sink: Large Signal Analysis Assume that we have a single current source M D GS D W L REF W L but we want more GS k k n W L D D W L W L REF W L n Assuming is in saturation Slope d d ro n saturation: k n D GS TN W kn ncox L n Small DS Not exactly the horizontal line of an ideal current source but good enough for many practical applications 8

9 A FET Current Mirror A ideal current mirror duplicates the current: GS GS W L W L Matched Transistors REF D M D Slope d d r o A matched transistor pair GS A FET Current Sink: Small Signal Analysis rocref v gs g m v gs r o i d i d v gs g m v gs r o rocref roc ro go We have a current sink that: Provides a DC current adjustable by changing the value of, and Has an incremental or small signal resistance approximately equal to r o (which can be pretty large) The resistance will become small if goes into the linear region 9

10 Multiple NFET Current Sinks D D D3 D4 D5 M M5 One can realize multiple current sinks for biasing applications from the same structure using NMOS devices with different (W/L) ratios: Dk W Lk REF W L Note that k needs to be always large enough such that Mk remains in saturation A PFET Current and Current Mirror A current mirror duplicates the current: GS GS W L W L Matched Transistors M D D Slope d d ro A matched transistor pair SG GS DD 0

11 Multiple PFET Current s DD DD DD DD M M5 D D D3 D4 D One can realize multiple current sources for biasing applications from the same structure using PMOS devices with different (W/L) ratios: k W Lk REF W L Note that k needs to be always small enough such that Mk remains in saturation A Current Sink with Large Output Resistance: The Cascode Design REF REF D D D D3 M M D D4 r oc r o g o r oc r r gm3ro3 gm3ro3r 4 o3 o4 o

12 A Current Sink with Large Output Resistance: The Cascode Design Usually the substrate contact of all NFETs in the stack are tied to the ground in CMOS technologies in which all NFETs share the same substrate D REF D3 Need to account for the body effect (due to nonzero SB ) in M D D4 The Double Wilson Current Mirror More immune to systemic errors in the fabrication process than the cascode design REF D D3 M D D4

13 A PFET Current : The Cascode Design M D D D M D4 r oc r o g o D D3 r oc r r gm3ro3 gm3ro3r 4 o3 o4 o A PFET Current : The Cascode Design Usually the substrate contact of all PFETs in the stack are tied to in CMOS technologies in which all PFETs share the same substrate Need to account for the body effect (due to nonzero SB ) in D M D4 D D3 3

14 Biasing the PFET Loaded NFET CS Amplifier Current source BAS PFET cascode load B3 B v s BAS R S D v out v s BAS R S D v out Biasing the PFET Loaded NFET CS Amplifier oltage biasing network f and M5 are identical and and M6 are identical (matched pairs) then D7 will equal and the gate voltages needed for M5 and M6 will be automatically generated on the chip without exact knowledge of the k p and TP of the PFETs Matched pairs Matched pairs R S v s BAS M5 M6 M7 D7 PFET cascode load v out 4

15 Biasing the PFET Loaded NFET CS Amplifier Matched pairs M5 PFET cascode load Matched pairs M6 D M D D7 v s BAS R S M7 D7 v out NFET current sink Biasing the PFET Loaded NFET CS Amplifier Matched pairs M5 PFET cascode load Matched pairs R M6 D M v s BAS R S M7 D7 v out NFET current sink 5

16 Biasing the PFET Loaded NFET CS Amplifier PFET cascode current source Matched pairs M5 Matched pairs M6 REF D7 v s BAS R S M7 D7 v out Biasing the PFET Loaded NFET CS Amplifier So we implemented a current source load using the PFETs in a cascode configuration Current source BAS v s BAS R S M7 D7 v out 6

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