Lecture 4: Voltage References

Transcription

1 EE6378 Power Management Circuits Lecture 4: oltage References Instructor: t Prof. Hoi Lee Mixed-Signal & Power IC Laboratory Department of Electrical Engineering The University of Texas at Dallas Introduction Here, we will learn to build a reference voltage to provide a stable and accurate supply voltage. The voltage reference is an electronic circuit to provide an accurate and stable DC voltage that is very insensitive to the change in supply voltage and temperature How accurate is a voltage reference? E.g. Weston cell is an electrochemical device which provides a reproducible voltage of at 20 o C with a small temperature coefficient of 40 ppm/ o C. For integrated circuit implementation, active solid-state devices can achieve e a tempco of 1-4 ppm/ o C if appropriate compensation technique is employed Note To minimize error due to self-heating, voltage reference usually operates with modest current (e.g. < 1mA) Tempco temperature coefficient, usually expressed in ppm/ o C (parts per million/ o C or 10-6 / o C EE6378 Lecture H. Lee pg. 2

2 Overview Performance Requirements Zener Diode oltage Reference Bandgap oltage References Bandgap oltage References Implemented in CMOS technologies EE6378 Lecture H. Lee pg. 3 Performance Parameters (1) The primary requirements of a voltage reference are accuracy and stability. Some qualitative parameters are: Load Regulation Δ o /ΔI o (usually expressed in m/ma or m/a) or Load Regulation 100(Δ o /ΔI o ) (in %/ma or %/A) Line Regulation Δ o /Δ in (usually expressed in m/) or Line Regulation 100(Δ o /Δ in ) (in %/) Power Supply Rejection Ratio (PSRR) is a measure of the ripple in the reference voltage due to the ripples in the supply voltage ri (in db) ro PSRR 20log10 EE6378 Lecture H. Lee pg. 4

3 Performance Parameters (2) Example of line regulation / supply-voltage dependence at DD 3.3, 4.15 and 5 (step size of 0.85) DD 5 DD 4.15 DD 3.3 o Line regulation at T 27 C is ref ( DD 5 ) ref ( DD 3.3 ) m / EE6378 Lecture H. Lee pg. 5 Performance Parameters (3) The maximum ( ref(max) ) and minimum ( ref(min) ) reference voltages are and , respectively. The reference voltage at T 27 o C ( ref ) is The tempco in ppm/ o C can be found by 6 6 ref (max) ref (min) O Tempco 25.5ppm / C ref ( T max T min) ) (100 0) EE6378 Lecture H. Lee pg. 6

4 Overview Performance Requirements Zener Diode oltage Reference Bandgap oltage References Bandgap oltage References Implemented in CMOS technologies EE6378 Lecture H. Lee pg. 7 Review on Zener Diode oltage Reference The Zener diode described in Lecture 2 can be considered as a voltage reference. Since the breakdown voltage due to Zener breakdown mechanism has a negative temperature coefficient, and the breakdown voltage due to the avalanche multiplication has a positive coefficient, the reference voltage is somewhat independent of the change of temperature o rz R + r s z in Rs + R + r s z ZK Rsrz R + r s z I L Δ Line Regulation Δ o in Δo Load Regulation ΔI L rz R + r s s z Rsrz - R + r z EE6378 Lecture H. Lee pg. 8

5 Improved Zener Diode Reference (1) In the case of Zener diode, the output voltage o heavily depends on the load current I L, which in most cases are not good. It would be better if we could shield the z from the influence of the load. This can be done with the help of an op amp as shown below. This method refers to self regulation which shifts the burden of line and load regulations from the diode to the op amp EE6378 Lecture H. Lee pg. 9 By inspection, Improved Zener Diode Reference (2) R 24 (1 2 k o + ) z (1+ ) R 1 39 k The output voltage is also adjustable via R 2 The load current I L is supplied from the opamp such that the current flowing through the Zener diode is almost constant at k o z z R3 I 1.15mA. Since the diode current is independent of the load current, the diode voltage is insensitive to the load R 3 can be raised to avoid unnecessary power wastage and self-heating effects R2 24k (1 + ) z (1 + ) R 39k o 1 EE6378 Lecture H. Lee pg. 10

6 Load Regulation (1) The load regulation is directly related to the output impedance. To find R o, we suppress the input source z and apply the test-voltage technique. By voltage divider formula: vn R1 // r in v R1 // rin + R2 Summing currents at the output node v N v Av N v i + + R2 r o 0 Eliminating v N and solving for the R o v/i, we obtain r R o o 1+ [( A + ro / R1 + ro / rin) /(1+ R2 / R1 + R2 / rin)] ro R where b 1 1+ Ab R1 + R2 EE6378 Lecture H. Lee pg. 11 Load Regulation (2) Typically r in is in the MΩ range or greater, R 1 and R 2 are in kω range and r o is on the order of 10 2 Ω. The terms r o /R 1, r o /r in, and dr/ 2 /r in can thus be ignored to yield R o r o /(1+Ab) The load regulation R o rr o /(1+Ab) which is much smaller than the Zener diode voltage reference without opamp p Since r o and A are frequency dependent, so are the load regulation. In general, load regulation tends to degrade with frequency EE6378 Lecture H. Lee pg. 12

7 Thermal Stability (1) Thermal stability is one of the most demanding performance requirement of voltage references due to the fact that semiconductor components are strongly influenced by temperature The forward-bias voltage D and current I D of a silicon pn junction, which forms the basis of the diodes and BJTs, are related as D T ln(i D /I S ), where T is the thermal voltage and I S is the saturation current. Their expressions are T kt / q and IS BT exp( G0 3 / T ) where k is Boltzmann s constant q C is the electron charge T is the absolute temperature B is a proportionality constant G is the bandgap voltage for silicon EE6378 Lecture H. Lee pg. 13 Thermal Stability (2) The temperature coefficient (TC) of the thermal voltage: T k TC( T ) m/ 0862m/ T q ID G 0 [ln ] (3lnT ) ID IS D T G 0 TC( ) ln( ) + T T -( T I T T T T D T D + S Assume D 650m at 25 o C, we get TC( D ) -2.1m/ o C. o C 3k ) q TC( T ) have a positive tempco and TC( D ) have a negative tempco, so these two equations form the basis of two common approaches to thermal stabilization, namely, thermal compensated Zener diode references and bandgap references EE6378 Lecture H. Lee pg. 14

8 Thermally Compensated Zener Diode Reference Idea of thermally compensated Zener diode is to connect a forwardbiased diode in series with a Zener diode having an equal but opposing tempco as shown below Since TC( z ) is a function of z and I z. We can fine tune I z to drive the tempco of the composite device to zero. In this case, a 7.5mA is used to give a reference voltage of z with tempco ranging from 100ppm/ o C to 5ppm/ o C EE6378 Lecture H. Lee pg. 15 Overview Performance Requirements Zener Diode oltage Reference Bandgap oltage References Bandgap oltage References Implemented in CMOS technologies EE6378 Lecture H. Lee pg. 16

9 Bandgap oltage Reference (1) Since the best breakdown voltages of the Zener diode references range from 6 to 7, they usually require supply voltages on the order of 10 to operate. This can be a drawback in systems powered from lower supplies, such as 5. This limitation i i is overcome by bandgap voltage references, so called because their output is determined primarily by the bandgap voltage of silicon G EE6378 Lecture H. Lee pg. 17 Bandgap oltage Reference (2) Addition of the voltage drop BE of a base-emitter junction, which has a negative tempco, to a voltage proportional to the thermal voltage T, which has a positive tempco, to generate a reference voltage, which h is independent of temperature EE6378 Lecture H. Lee pg. 18

10 Fundamentals As TC( BE ) -2.1m/ C and TC( T ) m/ C, then zero tempco is achieved at a particular temperature (e.g. T300K): BG BE + KT i.e. TC( BG) 300K TC( BE ) + K TC( TC ( ) 2.1 K BE 24.4 TC( ) T T ) 0 If for a particular transistor with certain bias current such that BE 650m, then BG BE + KT (0.0259) Note that T kt/q T, i.e. T is proportional to absolute temperature. We call T a Proportional To Absolute Temperature voltage, or in short, PTAT voltage EE6378 Lecture H. Lee pg. 19 Bandgap oltage Reference Circuit (1) From the figure, the emitter area of Q1 is n times as large as the emitter area of Q2, then I s1 /I s2 n By op amp action with identical collector resistances, the collector currents are also identical, i.e. I C1 I C2. Ignore the base currents, we have K T R(I 4 C1 +I C2 ) 2R 4 I IC 2I S1 IR3 BE 2 BE1 T ln( ) T ln( n) I I C1 S1 I ln( 2I IR C S BE BE T ) T ln( n) IC1I S1 Combine two equations give 2 R4 T R 2 4 T R3 R3 K ln( n ) BG BE2 + K T BE2 R + (2 R 4 3 lnn) T EE6378 Lecture H. Lee pg. 20

11 Bandgap oltage Reference Circuit (2) From the previous discussion, i for a zero tempco voltage reference BG, K 24, with n 4, then R R K 2ln2 2ln Note that I T ln(n)/r 3 T, I is a PTAT current EE6378 Lecture H. Lee pg. 21 Brokaw Cell Brokaw cell is commonly used bandgap-cell realization circuit it and is shown in the figure The function of op amp is replaced by Q 3, Q 4 and Q 5. Q 3 and Q 4 form a current mirror to enforce the collector currents of Q 1 and Q 2 are identical The emitter follower Q 5 raises the reference voltage to ref (1+R 1 /R 2 ) BG EE6378 Lecture H. Lee pg. 22

12 Stability of a Bandgap Reference In a bandgap reference, there exists 2 feedback loops, 1 positive loop and 1 negative loop. For the negative loop (the outer loop), R 1/ e + Negative Loop Gain 2 g m 1 A ( s ) R1 + R2 + 1/ gm1 For the positive loop (the inner loop), R + 1/ gm 1 Negative Loop Gain R + R + 1/ g 1 2 m1 A( ) 2 s 1/ g Positive Loop Gain m1 A( s) R1 + 1/ gm1 For stability, we must have a negative loop gain magnitude > positive loop gain magnitude. This is true as ((a+c)/(b+c))>(a/b) for b>a EE6378 Lecture H. Lee pg. 23 Stability of Simple Brokaw Cell (1) If we neglect R 3, then clearly Q1 and Q2 form a differential pair with positive and negative terminals tied together Above is the way to break the loop for measuring loop gain. The circuit should have a DC closed loop and AC open loop. The DC closed loop is for biasing and the AC loop is to measure loop gain EE6378 Lecture H. Lee pg. 24

13 Stability of Simple Brokaw Cell (2) With the presence of R 3, the positive loop looks like an amplifier with degenerated emitter the gain is smaller than that with R 3. Therefore, negative loop gain magnitude > positive loop gain magnitude, i.e. stability requirement is satisfied C c is the compensation capacitor. Here, dominant pole compensation is employed EE6378 Lecture H. Lee pg. 25 Overview Performance Requirements Zener Diode oltage Reference Bandgap oltage References Bandgap oltage References Implemented in CMOS technologies EE6378 Lecture H. Lee pg. 26

14 CMOS Bandgap References (1) CMOS is the dominant technology for both digital and analog circuit design nowadays Independent bipolar transistors are not available in CMOS technology CMOS voltage reference, however, can be achieved by making use of the concept of voltage reference. These CMOS circuits rely on using well transistors. These devices are vertical bipolar transistors that use wells as their bases and the substrate as their collectors EE6378 Lecture H. Lee pg. 27 CMOS Bandgap References (2) These vertical bipolar well transistors have reasonable current gain ( 25), but very high series base resistance ( 1kΩ/ ) due to the fact that the base contact is far away from the base The maximum collector current is thus limited to less than 0.1mA to minimize errors due to the base resistance EE6378 Lecture H. Lee pg. 28

15 CMOS Bandgap References (3) Two possible implementations: For example, in the n-well CMOS implementation, ti what is BG of fthe reference circuit? EE6378 Lecture H. Lee pg. 29 CMOS Bandgap References (4) BG EB2 + R 2 Assume the op amp has very large gain and very small input currents such that its input terminals are at the same voltage, then Δ R3 EB2 EB1 EB R3 EB2 EB 1 Δ EB Since the current through R 1 is the same as in R 3 R 1 R 3 R1 R1 or 1 3 Δ R R R R R R EB R Δ 1 BG EB2 EB R3 EE6378 Lecture H. Lee pg. 30

16 In CMOS realization, the bipolar transistors are often taken the same size, and different current densities (I C /I S ) are realized by taking R 1 greater than R 2, which causes I 2 to be greater than I 1 : CMOS oltage References (5) I R R1 R2 IR 1 1 I2R2 or I R kt Δ EB EB 2 EB1 q I I 2 ln( ) R1 kt R1 R1 R1 BG EB2 + ln( ) with K ln( ) R q R R R EE6378 Lecture H. Lee pg. 31 Example Find the resistances of a bandgap voltage reference based on the CMOS n-well process where I 1 5μA, I 2 40μA and EB 0.65 at T 300K. Assume BG Ans. R 1 118kΩ, R kΩ and R kΩ EE6378 Lecture H. Lee pg. 32

17 Other CMOS References Current mirror enforces equal currents at M1, M2 and M3 oltage clamping by M4 and M5 to enforce 12 PTAT loop formed by Q1, Q2 and R1 I T ln( N )/ R1 R2 ref EB 3 + ln( N) T R1 Cascode current mirror or other forms for better current matching at different supply voltages EE6378 Lecture H. Lee pg. 33 Current Mirror with Op Amp In CMOS reference using current mirror with op amp, an op amp is used to enforce the drain voltage of M 1 the same as of M 2. This allows a better current matching of drain currents of M 1 and M 2 EE6378 Lecture H. Lee pg. 34

18 Error Sources in oltage-reference Design Current mirror oltage-clamping circuit BJT emitter area ratio (BJT matching) Resistor ratio (resistor matching) Base current Base resistance Systematic offset at different supply voltages Random offset of devices Temperature gradient within a chip EE6378 Lecture H. Lee pg. 35 Design Considerations: BJTs Closely packed common-centroid layout Large N does not provide significant ifi change due to the logarithm relation Generally, N8 is chosen based on chip area consideration EE6378 Lecture H. Lee pg. 36

19 Design Considerations: Resistors Matching is important to obtain an accurate resistance ratio Square-like common-centroid layout EE6378 Lecture H. Lee pg. 37 Typical Low-oltage Implementation Error-amplifier current mirror enforces A B Min DD REF + ov,m2 Offset voltage error Offset voltage function of TH, mobility and transistor size temperature dependent Use simple amplifier Reduce both systematic and random offset EE6378 Lecture H. Lee pg. 38

20 Offset oltage Consideration T ln( N) + I R 1 OFF R + N + 2 ref EB2 ( )[ T ln( ) OFF ] R1 Al larger Nis used dto minimize i i the required R 2 /R 1, and the effect of the amplifier offset Increase chip area EE6378 Lecture H. Lee pg. 39 Base Resistance Consideration Large base resistance of parasitic vertical BJT Diode-connected BJT EB As mentioned before, I < 0.1mA Not due to low-power design, but due to reduce voltage across R B On layout, more N-well contacts to reduce R B EE6378 Lecture H. Lee pg. 40

21 β is small in CMOS technology I C I E and I C is a function of β Introduced β in I C causes extra errors and temperature dependence Base current compensation by a dummy transistor Q1D I E of Q1 I + I/β I C of Q1 I Q1D must match with Q1 Base Current Compensation EE6378 Lecture H. Lee pg. 41 Resistor Trimming Resistor ratio can be fine-tuned dby using a series of resistor network associated with fuse By burning the fuse, the resistor value can be adjusted to fine-tune the reference voltage and the temperature with zero tempco to a particular value EE6378 Lecture H. Lee pg. 42

22 Buffered oltage Reference Series-shunt shunt feedback High output current to drive resistive load Low output resistance Isolation to reduce cross-talk through reference circuit EE6378 Lecture H. Lee pg. 43 Current Source Generated by a oltage Reference Series-series feedback I REF /R MIN ov + REF EE6378 Lecture H. Lee pg. 44

23 R R ( )( + ( )ln( N) ) 3 2 REF EB2 T R2 R1 R 1, R 2 &R 3 of same material CMOS Bandgap Reference with Sub-1- Operation (1) Good matching R 1 and R 2 for optimizing tempco Good matching R 2 and R 3 for dj ti th l f adjusting the value of REF M1, M2 & M3 of equal W, L REF for matching DS of M1-M3 at different DD EE6378 Lecture H. Lee pg. 45 CMOS Bandgap Reference with Sub-1- Operation (2) Native NMOST : THN Not available in standard CMOS technologies EE6378 Lecture H. Lee pg. 46

24 Low-oltage Design Problem of Error Amplifier Worst case (smallest) EB at maximum operational temperature EB > THN + 2 ov Low- THN (<0.4) technology Body effect increases THN Worst case (largest) EB and THP at minimum temperature EB < DD - thp - 2 ov DD(min) EB + THP + 2 ov EE6378 Lecture H. Lee pg. 47 References H. Banba, et. al. A CMOS bandgap reference circuit with sub-1- operation, IEEE Journal of Solid-State Circuits, vol. 34, pp , May K. N. Leung, et. al. A sub-1-15-ppm/ C CMOS bandgap voltage reference without requiring low threshold voltage device, IEEE Journal of Solid-State Circuits, vol. 37, pp , Apr P. K. T. Mok, et. al. Design considerations of recent advanced lowvoltage low-temperature-coefficient CMOS bandgap voltage reference, IEEE Custom Integrated Circuits Conference, Sep. 2004, pp EE6378 Lecture H. Lee pg. 48