ECE 546 Lecture 12 Integrated Circuits

Transcription

1 ECE 546 Lecture 12 Integrated Circuits Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois ECE 546 Jose Schutt Aine 1

2 Integrated Circuits IC Requirements Biasing of ICs is based on the use of constant current sources Use current mirrors Source circuits are used as loads ECE 546 Jose Schutt Aine 2

3 Integrated Circuits Analog Design Requirements Analog ICs may need resistors and capacitors for the design of amplifiers Resistors and capacitors occupy the space of tens or hundreds of MOS devices It is important to minimize their use ECE 546 Jose Schutt Aine 3

4 Transistor Biasing ECE 546 Jose Schutt Aine 4

5 Transistor Biasing ECE 546 Jose Schutt Aine 5

6 Current Mirrors A current mirror will reproduce a reference current to the output while allowing the output voltage to assume any value within a specified range. I o =KI in where K is a factor that can be less than or equal or greater than 1 ECE 546 Jose Schutt Aine 6

7 MOS Current Mirror 1 W I k V V 2 ' D1 n GS Tn 2 L 1 I D1 I REF V DD V R GS 1 W I I k V V 2 ' o D2 n GS Tn 2 L 2 R is usually external to IC ECE 546 Jose Schutt Aine 7

8 MOS Current Mirror Assuming that the transistors are using the same process I W / L o 2 WL I W / L WL REF Can be limited by Channel length modulation () Threshold voltage mismatch Imperfect geometrical matching ECE 546 Jose Schutt Aine 8

9 MOS Current Mirror I WL1V V I WL V V o 2 1 DS 2 DSP2 REF DS1 DSP1 Some Properties 1. MOS current mirrors draw zero control currentbetter than BJT s 2. Matching of threshold voltages harder than in BJT s ECE 546 Jose Schutt Aine 9

10 Example A matched pair of MOSFETs are used in a current mirror witl = V -1, C ox =70 A/V 2, W/2L =10, and V T = 0.9 V. Find the value of R to create an input current of 100 A. Calculate the output current when V o = 3 V. Use drain current equation in active region to calculate C W I V V V 2L ox 2 D1 GS T DS1 1 2 D GS GS I V * V We can now solve for the value of V GS ECE 546 Jose Schutt Aine 10

11 Example MOS Current Mirror ECE 546 Jose Schutt Aine 11

12 R Example V GS = V The resistance needed is: 5V DS k I D1 0.1 The output current is calculated from: CoxW 2 I D2 VGS VT 1VDS1 2L 2 I D A ID2 106 A ECE 546 Jose Schutt Aine 12

13 Ideal MOS Common Source CKT R, A g r, R r i vo m ds o ds Intrinsic gain is gmrds ECE 546 Jose Schutt Aine 13

14 PMOS Implementation of Active Load Let r r for Q ds1 o1 1 r r forq ds2 o2 2 then, R r r out o1 o2 AMB gm 1Rout 1 Let go g ro 1 1 go g r 1 ds1 2 ds2 o2 ECE 546 Jose Schutt Aine 14

15 PMOS Implementation of Active Load Can show that the 3dB point is given: f 2o g g C C C C db1 db2 gd1 gd 2 Large incremental load leads to high gain while maintaining acceptable DC current (resistor would not work) ECE 546 Jose Schutt Aine 15

16 Background Differential Amplifiers The input stage of every op amp is a differential amplifier Immunity to temperature effects Ability to amplify dc signals Well-suited for IC fabrication because (a) they depend on matching of elements (b) they use more components Less sensitive to noise and interference Enable to bias amplifier and connect to other stage without the use of coupling capacitors ECE 546 Jose Schutt Aine 16

17 Differential Amplifiers Practical Considerations Both inputs to a differential amplifier may have different voltages applied to them In the ideal situation with perfectly symmetric stages, the common-mode input would lead to zero output Temperature drifts in each stage are often common-mode signals Power supply noise is a common-mode signal and has little effect on the output signal ECE 546 Jose Schutt Aine 17

18 MOS Differential Pair Assume current source is ideal Transistors should not enter triode region

19 Common-Mode Operation Input voltage v cm to both gates Difference in voltage between the two drains is zero

20 Differential pair responds to differntial input signals by providing corresponding differential output signal between the two drains. Differential Input Voltage

21 MOS Differential Pair Assume current source is ideal v ID =v gs1 -v gs2 Output is collected as v D2 -v D1 ECE 546 Jose Schutt Aine 21

22 MOS Differential Pair - If v ID is positive, v D2 -v D1 is positive v ID >0 v gs1 >v gs2 I D1 > I D2 v D1 lower voltage point than v D2 For proper operation, MOSFETS should not enter triode region ECE 546 Jose Schutt Aine 22

23 DC Analysis IRD VD 1 VDD 2 VD2 VDD I CoxW 2 I D ID VGS VT 2 2L IR 2 D V GS LI VT VSQ VT CoxW LI C W ox ECE 546 Jose Schutt Aine 23

24 Incremental Analysis 1 1 vg1 vcm v v id 2 v v 2 2 v g R ' o1 m D Neglecting the body effect v 2 in v g R ' o2 m D g cm id v 2 in R R r ' D D out A v v g R o2 o1 ' D m D vin ECE 546 Jose Schutt Aine 24

25 Frequency Response When driven by a low-impedance signal source, the upper corner frequency is determined by the output circuit f high 1 2C R out ' D ECE 546 Jose Schutt Aine 25

26 Common-Mode Rejection Ratio vo 1 vo2 RD v 1 icm vicm 2R g m SS Assume R SS >> 1/g m ECE 546 Jose Schutt Aine 26

27 Common-Mode Rejection Ratio (a) For single-ended output: v v R v v 2R o1 o2 D icm icm SS RD 1 A, A g R 2R 2 cm d m D SS CMRR A A d cm g R m SS ECE 546 Jose Schutt Aine 27

28 Common-Mode Rejection Ratio (b) For differential output: A cm v v o2 o1 0 icm v A v v g R o2 o1 d m D vid CMRR ECE 546 Jose Schutt Aine 28

29 Differential Amplifiers - Observations Observations The differential pair attenuates the input signal of each stage by a factor of one-half cutting the gain of each stage by one-half The double-ended output causes the two singleended gains to be additive Thus, the voltage gain of a perfectly matched differential stage is equal to that of a single stage ECE 546 Jose Schutt Aine 29

30 MOS Differential Amp with Active Load Replacing drain resistances with current sources, results in much higher voltage gain and savings in chip area in diff amp ECE 546 Jose Schutt Aine 30

31 MOS Differential Amp - Equilibrium

32 MOS Differential Amp with Active Load Current mirror action makes it possible to convert the signal to single-ended form without loss of gain. The differential gain is: v A g r r o d m o2 o4 vid If r r r o2 o4 o A d 1 2 g r m o ECE 546 Jose Schutt Aine 32

33 MOS Differential Amp with Active Load The active-loaded MOS differential amplifier has a low common-mode gain high CMRR The common-mode gain is: A cm vo 1 ro4 v 2R 1 g r icm SS m3 o3 Usually, g r 1 and r r A cm m3 o3 o3 o4 2g 1 R m3 SS R SS is internal impedance of current source ECE 546 Jose Schutt Aine 33

34 MOS Differential Amp with Active Load Since R SS is large, A cm will be small A 2 d CMRR gm ro2 ro4 gm3rss A cm If r r r and g g o2 o4 o m3 m CMRR g mro gmrss ECE 546 Jose Schutt Aine 34

35 CMOS OP Amp Example In the differential amplifier shown, Q 1 and Q 2 form the differential pair while the current source transistors Q 4 and Q 5 form the active loads for Q 1 and Q 2 respectively. The dc bias circuit that establishes an appropriate dc voltage at the drains of Q 1 and Q 2 is not shown. The following specifications are desired: differential gain A d = 80V/V, I REF = 100 A, the dc voltage at the gates of Q 6 and Q 3 is +1.5V; the dc voltage at the gates of Q 7, Q 4 and Q 5 is 1.5V. The technology available is specified as follows: n C ox =3 p C ox = 90A/V 2 ; V tn = V tp =0.7V, V An = V Ap = 20V. Specify the required value of R and the W/L ratios for all transistors. Also, specify I D and V GS at which each transistor is operating. For dc bias calculations, you may neglect channel-length modulation. Fill in the entries in the table provided to show your results. ECE 546 Jose Schutt Aine 35

36 CMOS OP Amp Example ECE 546 Jose Schutt Aine 36

37 CMOS OP Amp Example 1.5 ( 1.5) 3V I REF 100 A R 30k R 0.1mA Drain currents are determined by symmetry and inspection V GS values are also determined by inspection for all transistors except Q 1 and Q 2. To determine V GS for Q 1 and Q 2, we do the following: the equivalent load resistance will consist of r o1 in parallel with r o4 for Q 1 and r o2 in parallel with r o5 for Q 5. Since the r o s are equal, this corresponds to r o /2. We have: ro 2Ad 280 gm Ad gm 0.4 ma / V 2 r 400k o ECE 546 Jose Schutt Aine 37

38 CMOS OP Amp Example g m 2ID 2ID Vov V g 0.4 ov Take polarity into account for PMOS m 0.25 V GS 1, VT 0.95 To find W/L ratios, use W 2 W 2I D ID Cox ( VGS VT) 2 L L C ( V V ) ox GS T taking into account PMOS and NMOS devices separately 2 ECE 546 Jose Schutt Aine 38

39 CMOS OP-AMP DESIGN TABLE Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Units C ox A/ V 2 I D A V GS V W/L ECE 546 Jose Schutt Aine 39