6.776 High Speed Communication Circuits Lecture 7 High Freqeuncy, Broadband Amplifiers
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1 6.776 High Speed Communication Circuits Lecture 7 High Freqeuncy, Broadband Amplifiers Massachusetts Institute of Technology February 24, 2005 Copyright 2005 by Hae-Seung Lee and Michael H. Perrott
2 High Frequency, Broadband Amplifiers The first thing that you typically do to the input signal is amplify it package Connector Adjoining pins Controlled Impedance PCB trace die Driving Source On-Chip Z Delay = x Characteristic Impedance = Z o L Amp V out V Transmission Line in C C 2 L V L Function - Boosts signal levels to acceptable values - Provides reverse isolation Key performance parameters - Gain, bandwidth, noise, linearity
3 Gain-bandwidth Trade-off Common-source amplifier example V dd L v o V bias - - C tot Ctot : total capacitance at output node DC gain 3 dbbandwidth Gain-bandwidth
4 Gain-bandwidth Trade-off Common-source amplifier example L = L L = L3 L = L3 Given the origin pole g m /C tot, higher bandwidth is achieved only at the expense of gain The origin pole g m /C tot must be improved for better GB
5 Gain-bandwidth Improvement How do we improve g m /C tot? Assume that amplifier is loaded by an identical amplifier and fixed wiring capacitance is negligible Since and To achieve maximum GB in a given technology, use minimum gate length, bias the transistor at maximum When velocity saturation is reached, higher does not give higher g m In case fixed wiring capacitance is large, power consumption must be also considered
6 Gain-bandwidth Observations Constant gain-bandwidth is simply the result of singlepole role off it s not fundamental! It implies a single-pole frequency response may not be the best for obtaining gain and bandwidth simultaneously Single-pole role off is necessary for some circuits, e.g. for stability, but not for broad-band amplifiers
7 Assumptions (for now) for Bandwidth Analysis Assume for now that amplifier is loaded by an identical amplifier and by fixed wiring capacitance Assume amplifier is driven by an ideal voltage source for now C tot = C out C in C fixed C in C out C in Amp Amp C fixed Intrinsic performance - Defined as the bandwidth achieved for a given gain when C fixed is negligible - Amplifier approaches intrinsic performance as its device sizes (and current) are increased In practice, point of diminishing return for bandwidth vs. size (and power) of amplifier is roughly where C in C out = C fixed
8 The Miller Effect Concerns impedances that connect from input to output of an amplifier Z in Z f Z out V in Input impedance: A v Amp V out Z L Output impedance:
9 Example: Miller Capacitance Consider C gd in the MOS device as C f - Assume gain is negative C f Z in Z out V in Input capacitance: A v Amp V out Z L Looks like much larger capacitance by A v
10 Example: Miller Capacitance C f Z in Z out V in A v Amp V out Z L Output impedance: This makes sense because the input of the amplifier is virtual ground if gain is large
11 Amplifier Example CMOS Inverter The Miller effect gives a quick way to estimate the bandwidth of an amplifer without solving node equations: intuition! Assume that we set V bias the amplifier nominal output is such that NMOS and PMOS transistors are all in saturation - Note: this topology VEY sensitive to V bias : some feedback biasing would be required (6.30) M 2 M 4 v out M C fixed M 3 V bias C tot = C db C db2 C gs3 C gs4 K(C ov3 C ov4 ) C fixed (C ov C ov2 ) Miller multiplication factor
12 Transfer Function of CMOS Inverter v out (g m g m2 )(r o r o2 ) slope = -20 db/dec Low Bandwidth! g m g m2 2πC tot (r o r o2 ) 2πC tot f M 2 M 4 v out M C fixed M 3 V bias C tot = C db C db2 C gs3 C gs4 K(C ov3 C ov4 ) C fixed (C ov C ov2 ) Miller multiplication factor
13 Add esistive Feedback? v out (g m g m2 )(r o r o2 ) (g m g m2 ) f slope = -20 db/dec Bandwidth extended and less sensitivity to bias offset (does not improve GB, though) f g m g m2 2πC tot (r o r o2 ) 2πC tot 2πC tot f f M 2 v out M 4 M C fixed M 3 V bias C tot = C db C db2 C gs3 C gs4 K(C ov3 C ov4 ) C f /2 C fixed (C ov C ov2 ) Miller multiplication factor
14 We Can Still Do Better We are fundamentally looking for high g m to capacitance ratio to get the highest bandwidth - PMOS degrades this ratio - Gate bias voltage is constrained However, when C fixed is dominant and power consumption is important, the PMOS increases g m without additional power On the other hand, below velocity saturation, higher g m can be achieved by biasing the gate of M close to V dd instead of using PMOS M 2 M 4 f v out M C fixed M 3 V bias C tot = C db C db2 C gs3 C gs4 K(C ov3 C ov4 ) C f /2 C fixed (C ov C ov2 ) Miller multiplication factor
15 Take PMOS Out of the Signal Path Ibias V bias2 M 2 f v out f v out M C L M C L V bias V bias Advantages - PMOS gate no longer loads the signal - NMOS device can be biased at a higher voltage (higher g m up to velocity sat. limit) Issue - PMOS is not an efficient current provider (I d /drain cap C gd C db ) Drain cap close in value to C gs - Signal path is loaded by cap of f and drain cap of PMOS
16 Shunt-Series Amplifier s in I bias f out v out s in f out L v out M L M V bias V bias Use resistors to control the bias, gain, and input/output impedances - Improves accuracy over process and temp variations Issues - Degeneration of M lowers slew rate for large signal applications (such as limit amps) - There are better high speed approaches the advantage of this one is simply accuracy
17 Shunt-Series Amplifier Analysis Snapshot From Chapter 9 (8) of Tom Lee s book: - Gain s in v x f out L v out M V bias - Input resistance - Output resistance Same for s = L!
18 NMOS Load Amplifier V dd M 2 v out g m2 I d v out g m g m2 slope = -20 db/dec V bias M C fixed M 3 g m f Ctot = C db C sb2 C gs2 C gs3 KC ov3 C fixed g m2 2πC tot (C ov ) Miller multiplication factor 2πC tot Gain set by the relative sizing of M and M 2
19 Design of NMOS Load Amplifier V dd C tot = C db C sb2 C gs2 C gs3 KC ov3 C fixed g m2 M 2 I d v out (C ov ) Miller multiplication factor V bias M C fixed M 3 Size transistors for gain and speed - Choose minimum L for maximum speed - Choose ratio of W to W 2 to achieve appropriate gain
20 Advantage/Disadvantages of NMOS Load Amplifier Gain is well controlled despite process variations NMOS is not a low parasitic load - C gs of M2 loads the output Biasing Problem: V T of M 2 lowers the gate bias voltage of the next stage (thus lowering its achievable f t ) - Severely hampers performance when amplifier is cascaded - One paper addressed this issue by increasing V dd of NMOS load (see Sackinger et. al., A 3-GHz 32-dB CMOS Limiting Amplifier for SONET OC-48 receivers, JSSC, Dec 2000)
21 esistor Loaded Amplifier (Unsilicided Poly) V dd L v out V bias I d vout C fixed M M 2 C tot = C db C L /2 C gs2 KC ov2 C fixed (C ov ) Miller multiplication factor g m L 2π L C tot slope = -20 db/dec g m 2πC tot f This is the fastest non-enhanced amplifier topology - Unsilicided poly is a low parasitic load (i..e, has a good current to capacitance ratio) - Output can go near V dd Allows following stage to achieve high f t, but at the cost of gain (max gain V L ) - Linear settling behavior (in contrast to NMOS load)
22 Gain Limitations in esistor Loaded Amplifier Want high for high bandwidth, but this reduces gain. With low V dd gain is very limited.
23 Implementation of esistor Loaded Amplifier Typically implement using differential pairs V dd 2 V o V o- I bias /2 V in V in- C fixed C fixed αi bias M M 2 M 3 M 4 I bias M 5 M 6 M 7 Benefits - Bias stability without feedback - Common-mode rejection Negative - More power than single-ended version
24 Open-Circuit Time Constants The Miller capacitance analysis is a reasonably good method, but is somewhat limited in applicable topologies the OCT method is more general and often gives more insights Systematic, intuitive method to determine bandwidth of amplifiers Often gives fairly accurate estimates of bandwidth if there is a dominant pole Points to the bandwidth bottleneck: this is the real value of the OCT method! Limitation: fails in F circuits with zero enhancements or inductors In typical broadband amplifiers, the OCT estimate is too pessimistic due to multiple poles at around similar frequencies
25 Open Circuit Time Constant Method Assumptions: No zero near or ω h Zero well below wh is handled by treating corresponding capacitor as sort circuit Negative real poles only (complex conjugate poles with low Q reduces accuracy of estimation only moderately) No inductors Vo a0 A( s) = = V τ s τ s τ s = i ( )( ) ( ) a n ( τ τ τ ) s τ τ τ s If we ignore the higher order terms ωh = 2πf h = n τ τ 2 τ n 2 0 n i= τ i 2 2 n n
26 OCT Method, Continued It can be shown n τ i= i Thus = n τ j= ω h jo n τ jo j= where τ jo = jo C j :open-circuit time constants The open-circuit time constants can be found without node equations, often by inspection
27 OC Calculation Let s consider an arbitrary circuit with resistors, dependent sources, and n capacitors (no inductors!). edraw the circuit to pull capacitors out around the perimeter. C 2 2o C - o - C n no
28 OCT s for CS Amplifier 2o L C gd C L v o S 3o o C gs By inspection: It takes some work to figure
29 OCT s for CS Amplifier L i t v o S v gs - - v t g m v gs
30 OCT s for CS Amplifier If S =0, then τ o =0,τ 2o =C gd L, and τ 3o =C L L so L determines the bandwidth Having individual OCT values identifies the bandwidth bottleneck and suggests a game plan Note:for cascased amplifiers, C L does not include Miller cap of the next stage. Instead, τ 2o corresponding to the next stage Miller cap is separately calculated
31 Cascode to Improve Bandwidth L m v g a = Midband gain: by inspection V CC L v o v i S M M ,, mb m eff m eff L g g g = =, o eff S r = o S = ( ) 2 2,,, 2 mb m S m S eff L S m S S eff L eff L m o o g g g g g = = = 2 2 2,, 3 mb m eff m eff S o g g g L L eff S m eff L b o g r =,, 4
32 Cascode Improves bandwidth in a single-stage amplifier Problem in cascading: - Bias point: educes ω t of the next stage. PMOS SF is a possibility but low g m /C ratio is a drawback.
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