Analysis and Design of Analog Integrated Circuits Lecture 20. Advanced Opamp Topologies (Part II)


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1 Analysis and Design of Analog Integrated Circuits Lecture 20 Advanced Opamp Topologies (Part II) Michael H. Perrott April 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved.
2 Outline of Lecture Gain boosting technique Nested Miller technique Replica bias technique Improved slew rate opamp example 2
3 Recall the Folded Cascode Opamp Must set I bias2 > I bias1 /2 V bias4 I bias2 M 9 0 I bias2 I bias1 /2 I bias1 /2 V bias3 V out M 7 M 8 V out+ I ref V in M 2 V in+ V bias2 1 2 M 5 M 6 I bias2 I bias1 /2 Controlled by CMFB V bias1 M 3 Modified version of telescopic opamp  Significantly improved input/output swing  High BW (better than two stage, worse than telescopic)  Single stage of gain (lower than telescopic) I bias2 I bias1 /2 Can we further boost the DC gain? 3
4 Gain Boosting of Current Sources I out Rout DC Gain = K I out R out V ref DC Gain = K V ref v gs g m1 v gs g mb1 v s r o1 R ref v s R ref We can achieve increased output impedance of a current source with an amplifier  The amplifier essentially increases g m1 by factor K R out = (Kg m1 r o1 ) R ref Key issue: what is a convenient implementation of the above circuit? 4
5 A Simple Gain Boosting Amplifier V ref DC Gain = K I out Rout I ref I bias I out Rout I ref M 2 M 3 M 2 M 3 Common source amplifier utilized K = g m4 r o4,r ref = r o2 R out =(g m4 r o4 ) (g m1 r o1 ) r o2 (g m r o ) 2 r o2 Issue: current source requires significant headroom due to the fact that V ds2 = V gs4 5
6 Folded Cascode Gain Boosting Amplifier V bias4 M 8 I out Rout V bias3 V bias2 M 7 V bias5 I ref V bias1 M 6 M 2 M 3 M 5 Folded cascode yields K = g m4 (((g m6 r o6 )r o5 ) ((g m7 r o7 )r o8 )) R out (g m r o ) 3 r o2  Improved headroom and higher gain! Is there a convenient way to set V bias5? 6
7 Differential Version of Gain Boosting Amplifier V bias4 R out I out I out R out V bias4 V bias3 3 I bias 4 V bias3 1 M 2 2 V bias2 V bias0 V bias2 V bias1 M 9 M 5 M 3 M 6 0 V bias1 M 7 M 8 Leverage fully differential nature of current sources within the opamp  PMOS gain devices are now part of a differential pair  Need CMFB to set commonmode gate voltages of and M 2 7
8 Symbolic View of Folded Cascode Gain Boosting Amp R out I out I out R out V bias0 M 3 We can apply this to the overall folded cascode opamp 8
9 Folded Cascode with Gain Boosting V bias4 M 9 0 V out M 7 M 8 V out+ I ref V in M 2 V in+ M 5 M Controlled by CMFB V bias1 M 3 Gain boosting provides substantial increase of DC gain while maintaining good input and output swing  Gain is on the order of (g m r o ) 4 Issue very complex! 9
10 Recall Pole Splitting for Two Stage Compensation 20log V out /V id g m g m w (rad/s) w p1 w p2 w p1 w p2 Moves the dominant pole of the second stage to higher frequencies such that it becomes a parasitic pole Places the first stage pole as the dominant pole  Leverages the gain of the second stage to achieve capacitor multiplication using the Miller effect Can we extend the pole splitting technique to more than 2 gain stages? 10
11 Nested Miller Compensation 20log V out /V id g m g m g m Eschauzier, JSSC Dec 1992 Advantage: increased DC gain with high input and output swing Issue: more parasitic poles to deal with  Leads to lower unity gain bandwidth for reasonable phase margin w p1 w p3 w p2 w p1 w p2,w p3 w (rad/s) Proving to be a useful technique in advanced CMOS processes which offer fast speed (high g m /C) but low intrinsic gain (low g m r o ) 11
12 Nested Miller Example M 8 M 7 M 5 M 9 I ref V in V in+ M V bias Cc2 V out C c M M 6 Intermediate gain stages must be noninverting in order to achieve stable feedback Compensation resistors should also be included to eliminate the impact of RHP zeros  Not shown for simplicity 12
13 Recall the Telescopic Opamp Controlled by CMFB V bias3 V bias2 M 7 M 8 V out M 5 M 6 V out+ V bias1 I ref V in+ M 3 M 2 V in 0 M 9 Key issue is input swing  Can we improve this? 13
14 Replica Bias Technique Controlled by CMFB V bias3 V bias2 M 7 M 8 V out M 5 M 6 V out+ I ref K V bias1 V in+ V in V in+ M 3 M 2 V in M 9 Gulati, JSSC Dec, 1998 Allows current source to maintain its output current even for low V ds using dynamic bias of V gs  Allows extended input commonmode range 14
15 Recall: Slew Rate Issues for Opamps V dd V in V out ideal V in V ss V out slewrate limited Output currents of practical opamps have max limits  Impacts maximum rate of charging or discharging load capacitance,  For large step response, this leads to the output lagging behind the ideal response based on linear modeling We refer to this condition as being slewrate limited Where slewrate is of concern, the output stage of the opamp can be designed to help mitigate this issue  Will lead to extra complexity and perhaps other issues 15
16 Key Observations for Slew Rate Calculations I bias1 I bias2 V id /2 V id /2 V out M 2 R c C c M 3 M 6 Current Limits V id a vd1 I 1 C c a vd2 I 2 V out First stage  Max I 1 = I bias1  Min I 1 = I bias1 Second stage  Max I 2 = I bias2  Min I 2 = Large How can we improve opamp slew rate? 16
17 Class A and AB Amplifiers/Buffers Class A Amplifier Class AB Amplifier/Buffer V bias M 2 I bias M 2 I bias I bias V out V out V in V bias V out V in V in M 2 Class A  Maximum slew rate in one direction is set by the nominal bias current Class AB  Maximum slew rate is not set by the nominal bias current Goal: low nominal bias current 17
18 Class AB Opamp M 9 M 5 M 6 0 I bias I bias V in V in+ V out V bias M 2 V bias V out+ M 3 Costello, JSSC Dec 1985 Low bias current can be achieved for V in+ = V in  Must properly set V bias Much higher current when V in+ V in DC gain can be increased through cascoding of 1 M 7 M 8 2 output stage 18
19 Biasing Network for Class AB Opamp M 9 M 5 M 6 0 I bias I bias V in V in+ V out 3 M 2 5 V out+ 4 6 I ref M 3 I ref 1 M 7 M 8 2 Bias current set by  Ratio of device sizes of  versus I ref current 19
20 Summary Opamps invite a wide variety of techniques to address different application requirements  Cleverness can substantially improve performance and robustness  Changing of CMOS processes over time leads to new techniques which were previously unnecessary or unpractical Four techniques discussed today  Gain boosting  Nested Miller  Replica bias  Class AB stages 20
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