MOSFET Amplifier Design

Transcription

1 MOSFET Amplifier Design Introduction In this lab, you will design a basic 2-stage amplifier using the same 4007 chip as in lab 2. As a reminder, the PSpice model parameters are: NMOS: LEVEL=1, VTO=1.4, L=5e-6, W=124e-6, TOX=1080e-10, LAMBDA=0.01, KP=20e-6, PHI=0.6, GAMMA=1.5 PMOS: LEVEL=1, VTO=-1.4, L=5e-6, W=480e-6, TOX=1080e-10, LAMBDA=0.02, KP=6e-6, PHI=0.6, GAMMA=1.5 For this lab, the supply voltage is (instead of 5 V used in lab 2). Assignment Figure 1 shows the setup of the two-stage amplifier you will be designing. It consists of a gain stage, followed by a buffer stage. Capacitors and are large capacitors. In simulations, you may assume they are 1 F. We will design these stages step by step. v IN v OUT v OUT Figure 1. Two-stage amplifier Part 1 Design of the Gain Stage (a) First, we will design the gain stage by itself (see Figure 2) according to the following requirements: 1. The bias voltage at the source of the nmos, V S = 3 V. 2. The bias voltage at the drain of the nmos, V D = 6.5 V. 3. The bias voltage at the gate of the nmos, V G V D (i.e., the nmos is in saturation by some margin). 4. The V GS of the nmos, V GS 2.9 V. 5. The current through the nmos, I D 5 ma. 6. Select = 390 kω. 7. Maximize the small signal gain of the amplifier proper, i.e. maximize A vo. When doing your design, you may neglect r o in the equation of A vo (i.e., you may assume r o = for now). 1

2 The goal of this design is thus to select, and such that the design satisfies all the seven requirements. You do not want to try out different values of these resistors until you find a combination that works. Instead, write down all relevant equations and substitute. The key is to maximize the gain. Try to write this gain only as a function of known values and as few unknowns as possible (e.g., only I S or V GS ). The requirement to maximize the gain will then translate into a requirement on the remaining unknown (e.g. maximizing the current, maximizes the gain ). You can then use the inequalities to find the best selection, and this will determine your design. In the end, you also have to make sure all the other requirements are met. v IN1 v OUT1 Figure 2. Gain stage of the amplifier (b) Simulate your design of part (a) in PSpice. For now, just consider the bias conditions (i.e. no need to measure the small signal gain). Verify that your design meets all the bias specifications. Do not include these plots in your report. Instead, just give the bias values (bias voltages and currents) you find in simulation, and compare to your hand calculations and the specifications. (c) Now we need to match the design of part (a) to the limited set of resistor values that you have available in the lab (a list is available on the website, under lab 1). Do not use resistors in series or parallel. First, choose to be as close as possible to the value you found in part (a). Next, select that is as close as possible to your desired value, but make sure you do not violate the specifications. Finally select the same way. When choosing your values this way, you can use PSpice to verify in each step if the requirements still hold. Simulate your final design in PSpice, and verify all the bias condition requirements (no plot needs to be included). (d) For the design of part (c), calculate the small signal gain A vo, R in and R o. Do not neglect r o this time. You may use the bias current and voltage values you found from PSpice in part (c). Verify the small signal gain in PSpice, by attaching an AC voltage source at the input and doing a frequency domain simulation from 1 Hz to 1 GHz. Report the gain at low frequencies and compare to your calculations (you do not need to include the plot). 2

3 Part 2 Design of the Buffer Stage (a) Next, we will design the buffer stage of the amplifier (see Figure 3). For the current source, you will need to design it using a current mirror. The specifications for this stage are: 1. The bias voltage drop over the current source has to be such that is 1 V from going into triode region: i.e. for the MOSFET of the current mirror that carries the output current, V DS (= V OUT2 ) (V GS V thn ) + 1 V. 2. The current through the nmos N 1, I D 5 ma. 3. The bias input voltage V IN2 is defined by your final design of stage 1 (see also Figure 1). 4. Minimize the output resistance R o of the source follower. When you do your design, you may neglect r o when using the equation of R o (i.e., you may assume r o = for now). The key here, again is to write the parameter you need to optimize (i.e., R o ) as a function of other unknown elements. Note that since all MOSFETs in this lab are the same size, they will have the same V GS when they carry the same current, if we ignore channel length modulation. When doing your design, you may ignore channel length modulation (i.e., just assume λ = 0). In the end, this design boils down to finding the resistor used in the current source implementation (this is the only circuit element you can choose). v IN2 N 1 v OUT2 Figure 3. Buffer stage of the amplifier (b) Simulate your design of part (a) in PSpice. Just consider the bias conditions. Verify that your design meets all the bias specifications. Do not include plots. Instead, report the bias values you find in simulation, and compare to your hand calculations and the specifications. (c) Now select a resistor value for your design of part (a) that is available in the lab (do not use resistors in series or parallel). Choose one that is closest to your design value, and such that all specifications are met. To verify if the specifications are met, you can just use PSpice (no plots are needed in your report). (d) For the design of part (c), calculate the small signal gain A vo, R in and R o. Do not neglect r o or λ this time. You may use the bias current and voltage values you found from PSpice in part (c). Note that the amplifier has a non-ideal current source; you 3

4 will need to take this into account in your small signal models (i.e., you may have to modify the equations we saw in class). Verify the small signal gain in PSpice, by attaching an AC voltage source at the input and doing a frequency domain simulation from 1 Hz to 1 GHz. Report the gain at low frequencies and compare to your calculations (you do not need to include the plot). Part 3 Considering the Two-Stage Amplifier (a) Attach both stages together as in Figure 1. What do you expect the overall gain from v IN to v OUT to be, based on your earlier calculations of A vo, R in and R o? Verify the gain in PSpice, again by doing a frequency domain simulation over the same frequency range as before. This time, include the plot in your report (plot the voltage gain in db, so you get something similar to a Bode plot). (b) Now attach a load R L = 5 kω to the 2-stage amplifier using a coupling capacitor C 3 (of 1 F). At the input, the amplifier is driven by a non-ideal source with resistance R sig = 10 kω as shown in Figure 4. Calculate the overall gain (from v S to v OUT ) you expect now, based on A vo, R in and R o. Verify the gain in PSpice again in the frequency domain, and include the plot in your report (again in db). R sig C 3 v S R L v OUT Figure 4. Two-stage amplifier with non-ideal source and load (c) Calculate what the overall gain would have been if the load of 5 kω had been attached the first stage (with coupling capacitor), without the buffer stage. Again, we have the same non-ideal source. Verify in PSpice (again in the frequency domain no plot needed in the report). This illustrates the benefit of using such a buffer stage. 4

5 Part 4 Frequency Domain Analysis (a) Finally, we will try to create a well-defined first pole in our amplifier frequency response. For example, this is needed if we want to use our amplifier in a feedback configuration, and we desire a good phase margin (see also ECE100). We will place a capacitor C p between the G and D of the nmos in the first stage. The goal is to create a dominant pole. Based on calculations, find the capacitor value such that this dominant pole is at 430Hz. Assume the same non-ideal source and load as before. [Suggestion: You can look at the Thevenin model of the first stage with the non-ideal source and the input resistance of the second stage attached. When adding the capacitor C p, make sure you put it between the correct terminals. To find the dominant time constant, you can use the Miller theorem.] (b) Verify your design of part (a) in PSpice. Simulate your amplifier in the frequency domain for the same frequency range as before. Do not include the plot in your report. (c) Now select a capacitor value for your design of part (b) that is available in the lab. Just choose one that is closest to your design value. Redo you PSpice frequency domain simulation and include this plot in your report. Part 5 Breadboard The final part of this lab is to build and test a prototype of the circuit of part 4c. Choose realistic values for your large capacitors (large, but available). Verify the small signal gain at frequencies 100 Hz, 300 Hz, 430 Hz, 650 Hz, 1 KHz, 3 KHz and 10 KHz. Mark these points on the PSpice plot you generated in part 3f. 5