Lecture 3 Switched-Capacitor Circuits Trevor Caldwell

Transcription

1 Advanced Analog Circuits Lecture 3 Switched-Capacitor Circuits Trevor Caldwell trevor.caldwell@analog.com

2 Lecture Plan Date Lecture (Wednesday 2-4pm) Reference Homework MOD1 & MOD2 ST 2, 3, A 1: Matlab MOD1& MODN + Σ Toolbox ST 4, B 2: Σ Toolbox SC Circuits R 12, CCJM Comparator & Flash ADC CCJM 10 3: Comparator Example Design 1 ST 9.1, CCJM Example Design 2 CCJM 18 4: SC MOD Reading Week Amplifier Design Amplifier Design Noise in SC Circuits ST C Nyquist-Rate ADCs CCJM 15, 17 Project Mismatch & MM-Shaping ST , Continuous-Time Σ ST 6.6, Exam Project Presentation (Project Report Due at start of class) 2

3 NLCOTD: Schmitt Trigger Problem: Input is noisy or slowly varying How do we turn this into a clean digital output? 3

4 What you will learn Motivation for SC Circuits Basic sampling switch and charge injection errors Fundamental SC Circuits Sample & Hold, Gain and Integrator Other Circuits Bootstrapping, SC CMFB 4

5 Why Switched-Capacitor? Used in discrete-time or sampled-data circuits Alternative to continuous-time circuits Capacitors instead of resistors Capacitors won t reduce the gain of high output impedance OTAs No need for low output impedance buffer to drive resistors Accurate frequency response Filter coefficients determined by capacitor ratios (rather than RC time constants and clock frequencies) Capacitor matching on the order of 0.1% - when the transfer characteristics are a function of only a capacitor ratio, it can be very accurate RC time constants vary by up to 20% 5

6 Opamps Basic Building Blocks Ideal usually assumed Some important non-idealities to consider include: 1. DC Gain: sets the accuracy of the charge transfer, how grounded the virtual ground is 2. Unity-gain freq, Phase Margin & Slew Rate: determines maximum clock frequency 3. DC Offsets: circuit techniques to combat this and 1/f noise Correlated Double Sampling, Chopping Capacitors Large absolute variation, good matching Large bottom plate capacitor adds parasitic cap 6

7 Switches Basic Building Blocks MOSFET switches are good large off resistance (GΩ), small on resistance (100Ω - 5kΩ, depending on transistor sizing) MOSFET switches have non-linear parasitic capacitors Non-Overlapping Clocks Clocks are never on at the same time Required so that charge is never lost/shared 7

8 Basic Sampling Switch MOSFET used as sample-and-hold When CLK is HIGH, V OUT follows V IN through the lowpass filter created by R ON and C R ON varies depending on V IN, V OUT, and V DD When CLK is LOW, V OUT holds the value on C 8

9 On-Resistance Variation With an NMOS sampling switch, as V IN approaches V DD -V TH, R ON increases dramatically In smaller technologies, as V DD decreases the swing at V IN is severely limited R ON = 1 W µ ncox ( VDD VIN VTH ) L R ON V DD -V TH V IN Sampling switch must be sized for worst case R ON so that the bandwidth is still sufficient 9

10 On-Resistance Variation PMOS switches suffer from the same problem as V IN approaches V TH Complementary switch can allow rail-to-rail input swings Ignoring variation of V TH with V IN, R ON,eq is constant with V IN if W µ C = µ C n ox p ox L n W L p R ON,n R ON,p R ON,p R ON,n V TH V DD -V TH V DD V IN 10

11 Settling Accuracy Two situations to consider 1. Discrete-time signal When analyzing a signal within a switched-capacitor circuit (for example, at the output of the first OTA) 2. Continuous-time signal When analyzing a signal that is sampled at the input 11

12 Settling Accuracy - DT Discrete-Time Signal Settle in T/4 seconds Settling Error = e -T/4RC For N-bit accuracy R ON C This is the maximum R ON (for a given C) Example: < T 4Nln2 Assume 1 GHz to 4 GHz variation of Input sinusoidal signal at 50 MHz 1 2πRONC For f S =100 MHz, N=22 bits with discrete-time signal (typically you are limited by the OTA) 12

13 Settling Accuracy - CT Continuous-Time Signal R ON C acts as a low-pass filter and introduces amplitude and phase change Variations in the input signal size cause variations in R ON, causing distortion in the sampled signal Both the amplitude and phase vary which one causes distortion? 13

14 Distortion in sampled CT input Input ~50 MHz, sampled at 100MHz Distortion at 57dB, or ~9 bits This is larger than the maximum variation in amplitude (phase error must be significant) dbfs Normalized Frequency 14

15 Less significant error Amplitude Error Due to variation in magnitude of low-pass filter At 50 MHz (with same R ON C variation as DT case), maximum variation in amplitude is 0.1% 15

16 More significant error Phase Error Due to variation in phase of low-pass filter At 50 MHz (with same R ON C variation as DT case), maximum variation is a few percent (error is less than that) 16

17 Charge Injection When a transistor turns off, the channel charge Q CH goes into the circuit Doesn t exactly divide in half - depends on impedance seen at each terminal and the clock transition time Q = WLC ( V V V ) CH ox DD IN TH Charge into V IN has no impact on output node Doesn t create error in the circuit Charge into C causes error V in V OUT V = = Q CH 2C WLC ox( VDD VIN VTH ) 2C 17

18 Charge Injection In previous analysis, charge injection introduces a gain and offset error This is still linear and could be tolerated or corrected But VOUT = VIN V WLC ox WLC ox( VDD VTH ) = VIN 1+ 2C 2C V TH is actually a function of ~ V IN Introduces non-linear term that cannot be corrected in the circuit 18

19 Charge Injection vs. Speed Charge injection Proportional to transistor size (WL) Speed R ON inversely proportional to aspect ratio (W/L) Figure of Merit Product of speed (1/τ) and charge injection (1/ V) C WLC ox ( τ V) = ( VDD VIN VTH ) µ ncox ( W / L)( VDD VIN VTH ) C µ n = 2 L 19

20 Clock Feedthrough Overlap capacitance allows clock to couple from the gate to drain/source terminals Change in voltage V independent of the input signal Error is an offset voltage which is cancelled with differential operation V = C ov C + C ov V CLK 20

21 Charge Error Cancellation Differential operation Cancels offset errors, depending on the matching between differential circuits Applies to signal independent portion of charge injection error, and clock feedthrough error Complementary Switches Error cancelled for 1 input level W L C ( V V V ) = W L C ( V V ) n n ox CLK IN TH, n p p ox IN TH, p Clock feedthrough cancelled depending on similarity of overlap capacitance for PMOS and NMOS switches 21

22 Charge Error Cancellation Dummy Switch Use second transistor to remove charge injection by main transistor Inverted clock operates on dummy switch Charge from M1: qm1 = W1 L1C ox( VCK VIN VTH 1) / 2 Charge from M2: qm2 = W2 L2Cox ( VCK VIN VTH 2) If charge splits equally in M1 (not quite true), then with M2 half the size of M1, q = q M1 M2 22

23 Sample and Hold Amplifier Input dependent charge from S 1 onto C When S 1 turns off, charge q adds to C V OUT is then equal to V IN +q/c where q has a non-linear dependence on V IN We can improve on this by making V OUT independent of input-dependent charge 23

24 Two phases S/H Amplifier Phase 1: S 1 and S 2 closed, V IN sampled on C Phase 2: S 3 closed, C is tied to V OUT Phase 1 Charge on C is CV IN S 2 opens, injecting signal indep. charge at node X Then S 1 opens, injecting signal dependent charge q onto C + C p 24

25 Phase 2 S/H Amplifier S 3 closes, node X is a virtual ground Charge on C p is zero, charge on C is still CV IN S 3 injects charge on X that must be discharged due to virtual ground node it does not disturb charge on C V OUT = V IN S 1 / S 3 are non-overlapping, S 2 slightly ahead of S 1 25

26 Gain of the S/H Finite OTA gain reduces gain of sampler On Phase 1, C charges to V IN On Phase 2, node X goes from 0 to V X = -V OUT /A Charge comes from C, changing q C to CV IN + C p V X V OUT - (CV IN + C p V X )/C = V X V OUT VIN = 1 Cp 1+ 1 A + C 1 Cp VIN A C 26

27 Speed of the S/H In sampling mode (Phase 1) At node X, R X ~ 1/G M, τ 1 ~ (R on1 +1/G M )C In amplification mode (Phase 2) Replace charge on C by voltage source V IN (like switching in voltage source at start of Phase 2) After analysis, τ 2 = (C L C p +C p C+CC L )/G M C Reduces to τ 2 ~ C L /G M if C p is small 27

28 Basic Amplifier Sampling phase when S 1 and S 2 closed Input signal sampled onto C 1 Amplifying phase when S 3 closed Charge on C 1 transferred to C 2 so that the final output is C1 VOUT = VIN C 2 28

29 Basic Amplifier S 2 must open before S 1 for the charge injection to be signal independent Charge from S 2 opening is deposited on C 1, but is not signal dependent Charge from S 1 opening causes glitch in V OUT When S 3 closes, V OUT goes to final value, regardless of what happened between S 2 opening and S 3 closing 29

30 Precision Gain-2 Sampling phase when S 1, S 2, S 3 closed Input signal sampled onto C 1 and C 2 Amplifying phase when S 4, S 5 closed Charge on C 1 is transferred to C 2, doubling the charge on C 2 Final output is 2V IN since C 1 = C 2 30

31 Precision Gain-2 How is it more precise? The feedback factor in both gain circuits is C2 C + C + C 2 1 p In the precision Gain-2 circuit, C 1 = C 2 The basic amplifier has C 1 = 2C 2, resulting in a smaller feedback factor and a slower circuit The gain error is inversely proportional to the feedback factor, so the precision circuit is more accurate for a given amplifier gain A V OUT V IN C2 + C1 + C 2 1 AC2 p 31

32 Resistor Equivalence of SC Average current through switched-capacitor φ : Q = CV φ : Q = CV Q1 Q2 C( V1 V2 ) IAVG = = T T Equivalent current through a resistor (f IN << f S ) I EQ V V = R 1 2 EQ R EQ T = = C 1 Cf S 32

33 Switched-Capacitor Integrator Two non-overlapping clock phases control S 1,S 2 Phase 1: Sampling phase input is sampled onto capacitor C 1 Phase 2: Integrating phase additional charge is added to previous charge on C 2 33

34 Switched-Capacitor Integrator -VO[n]C2 +VO[n]C2 -VO[n]C2+VI[n]C1 +VO[n]C2-VI[n]C1 Final charge on L.S. of C 2 is +V O [n+1]c 2 + V [ n + 1] C = + V [ n] C V[ n] C O 2 O 2 I 1 zv ( z) C = V ( z) C V ( z) C O 2 O 2 I 1 V V O I ( z) = C1 C z

35 Parasitic Sensitive Parasitic capacitances C p1, C p3 and C p4 have no impact on transfer function C p2 in parallel with C 1, changes transfer function V ( C1 + Cp2) O 1 ( z ) = V C z 1 I 2 35

36 Parasitic Insensitive Transfer function is non-inverting, delaying V V O I ( z) = C1 1 C z

37 Parasitic Insensitive Parasitics have no impact on transfer function Better linearity since non-linear capacitors are unimportant Top plate on virtual ground node Minimizes parasitics, improves amplifier speed and resolution, reduces noise coupled to node Two extra switches needed More power to drive the switches for the same onresistance 37

38 Delay-Free Integrator Same structure, still parasitic insensitive Transfer function is inverting, delay-free VO C1 z ( z) = V C z 1 I 2 38

39 Bootstrapping At low supply voltages, signal swing is limited Maximum distortion determines the tolerable variation in R ON, and this limits the signal swing Want to increase V GS on the sampling switch Can do this by increasing the supply voltage for the sampling switch, but this requires slower thick oxide devices Alternatively, add a constant voltage to the input signal and use that as the gate voltage keep V GS constant, reducing the variation in R ON 39

40 Bootstrapped Circuit Basic operation φ 2 : C is charged to V DD and gate of sampling switch is discharged to V SS (turned off) φ 1 : V IN is added to voltage across C, sampling switch turns on, gate voltage of the sampling switch is V IN + V DD Ideally, there is always V GS = V DD for the sampling switch 40

41 Bootstrapped Circuit C must be sized so that charge sharing between gate capacitance of switch is not significant C VG = ( VIN + VDD ) C + C Rise time controlled by size of S 4, fall time controlled by size of S 5 G Extra transistors required to limit gate-source voltages to V DD and prevent overstress See Dessouky, JSSC Mar

42 Switched-Capacitor CMFB Two parts to a CMFB circuit 1. Sense the common mode of the output 2. Compare the common mode to the expected common mode, and adjust the bias accordingly Sensing Could use 2 resistors they are either too small and reduce the gain, or they can get prohibitively large Could use 2 capacitors they don t reduce the gain, but the voltage across them is undefined and must be refreshed every clock cycle 42

43 Switched-Capacitor CMFB One alternative Phase 1: precharge capacitors to ideal value Phase 2: sense the difference and adjust the bias accordingly 2 1 V CM V B1 C C 2 1 V CM V IN + V IN - C P 1 V B2 But there may be large changes in the tail current bias 43

44 Switched-Capacitor CMFB Alternatively, use 2 capacitors so that only a fraction of the charge is shared to adjust the bias voltage Typically, C 2 is 4-10 times C 1 44

45 What You Learned Today Errors introduced with simple sampling switch R ON variation, charge injection Main SC Circuits S/H, Gain and Integrators Parasitic Insensitive Signal-independent charge injection Bootstrapped Circuit Switched Capacitor CMFB 45

46 NLCOTD: Schmitt Trigger 46