Lecture 3 SwitchedCapacitor Circuits Trevor Caldwell


 Elfrieda Perkins
 1 years ago
 Views:
Transcription
1 Advanced Analog Circuits Lecture 3 SwitchedCapacitor Circuits Trevor Caldwell
2 Lecture Plan Date Lecture (Wednesday 24pm) Reference Homework MOD1 & MOD2 ST 2, 3, A 1: Matlab MOD1& MODN + Σ Toolbox ST 4, B 2: Σ Toolbox SC Circuits R 12, CCJM Comparator & Flash ADC CCJM 10 3: Comparator Example Design 1 ST 9.1, CCJM Example Design 2 CCJM 18 4: SC MOD Reading Week Amplifier Design Amplifier Design Noise in SC Circuits ST C NyquistRate ADCs CCJM 15, 17 Project Mismatch & MMShaping ST , ContinuousTime Σ ST 6.6, Exam Project Presentation (Project Report Due at start of class) 2
3 NLCOTD: Schmitt Trigger Problem: Input is noisy or slowly varying How do we turn this into a clean digital output? 3
4 What you will learn Motivation for SC Circuits Basic sampling switch and charge injection errors Fundamental SC Circuits Sample & Hold, Gain and Integrator Other Circuits Bootstrapping, SC CMFB 4
5 Why SwitchedCapacitor? Used in discretetime or sampleddata circuits Alternative to continuoustime circuits Capacitors instead of resistors Capacitors won t reduce the gain of high output impedance OTAs No need for low output impedance buffer to drive resistors Accurate frequency response Filter coefficients determined by capacitor ratios (rather than RC time constants and clock frequencies) Capacitor matching on the order of 0.1%  when the transfer characteristics are a function of only a capacitor ratio, it can be very accurate RC time constants vary by up to 20% 5
6 Opamps Basic Building Blocks Ideal usually assumed Some important nonidealities to consider include: 1. DC Gain: sets the accuracy of the charge transfer, how grounded the virtual ground is 2. Unitygain freq, Phase Margin & Slew Rate: determines maximum clock frequency 3. DC Offsets: circuit techniques to combat this and 1/f noise Correlated Double Sampling, Chopping Capacitors Large absolute variation, good matching Large bottom plate capacitor adds parasitic cap 6
7 Switches Basic Building Blocks MOSFET switches are good large off resistance (GΩ), small on resistance (100Ω  5kΩ, depending on transistor sizing) MOSFET switches have nonlinear parasitic capacitors NonOverlapping Clocks Clocks are never on at the same time Required so that charge is never lost/shared 7
8 Basic Sampling Switch MOSFET used as sampleandhold When CLK is HIGH, V OUT follows V IN through the lowpass filter created by R ON and C R ON varies depending on V IN, V OUT, and V DD When CLK is LOW, V OUT holds the value on C 8
9 OnResistance Variation With an NMOS sampling switch, as V IN approaches V DD V TH, R ON increases dramatically In smaller technologies, as V DD decreases the swing at V IN is severely limited R ON = 1 W µ ncox ( VDD VIN VTH ) L R ON V DD V TH V IN Sampling switch must be sized for worst case R ON so that the bandwidth is still sufficient 9
10 OnResistance Variation PMOS switches suffer from the same problem as V IN approaches V TH Complementary switch can allow railtorail input swings Ignoring variation of V TH with V IN, R ON,eq is constant with V IN if W µ C = µ C n ox p ox L n W L p R ON,n R ON,p R ON,p R ON,n V TH V DD V TH V DD V IN 10
11 Settling Accuracy Two situations to consider 1. Discretetime signal When analyzing a signal within a switchedcapacitor circuit (for example, at the output of the first OTA) 2. Continuoustime signal When analyzing a signal that is sampled at the input 11
12 Settling Accuracy  DT DiscreteTime Signal Settle in T/4 seconds Settling Error = e T/4RC For Nbit accuracy R ON C This is the maximum R ON (for a given C) Example: < T 4Nln2 Assume 1 GHz to 4 GHz variation of Input sinusoidal signal at 50 MHz 1 2πRONC For f S =100 MHz, N=22 bits with discretetime signal (typically you are limited by the OTA) 12
13 Settling Accuracy  CT ContinuousTime Signal R ON C acts as a lowpass filter and introduces amplitude and phase change Variations in the input signal size cause variations in R ON, causing distortion in the sampled signal Both the amplitude and phase vary which one causes distortion? 13
14 Distortion in sampled CT input Input ~50 MHz, sampled at 100MHz Distortion at 57dB, or ~9 bits This is larger than the maximum variation in amplitude (phase error must be significant) dbfs Normalized Frequency 14
15 Less significant error Amplitude Error Due to variation in magnitude of lowpass filter At 50 MHz (with same R ON C variation as DT case), maximum variation in amplitude is 0.1% 15
16 More significant error Phase Error Due to variation in phase of lowpass filter At 50 MHz (with same R ON C variation as DT case), maximum variation is a few percent (error is less than that) 16
17 Charge Injection When a transistor turns off, the channel charge Q CH goes into the circuit Doesn t exactly divide in half  depends on impedance seen at each terminal and the clock transition time Q = WLC ( V V V ) CH ox DD IN TH Charge into V IN has no impact on output node Doesn t create error in the circuit Charge into C causes error V in V OUT V = = Q CH 2C WLC ox( VDD VIN VTH ) 2C 17
18 Charge Injection In previous analysis, charge injection introduces a gain and offset error This is still linear and could be tolerated or corrected But VOUT = VIN V WLC ox WLC ox( VDD VTH ) = VIN 1+ 2C 2C V TH is actually a function of ~ V IN Introduces nonlinear term that cannot be corrected in the circuit 18
19 Charge Injection vs. Speed Charge injection Proportional to transistor size (WL) Speed R ON inversely proportional to aspect ratio (W/L) Figure of Merit Product of speed (1/τ) and charge injection (1/ V) C WLC ox ( τ V) = ( VDD VIN VTH ) µ ncox ( W / L)( VDD VIN VTH ) C µ n = 2 L 19
20 Clock Feedthrough Overlap capacitance allows clock to couple from the gate to drain/source terminals Change in voltage V independent of the input signal Error is an offset voltage which is cancelled with differential operation V = C ov C + C ov V CLK 20
21 Charge Error Cancellation Differential operation Cancels offset errors, depending on the matching between differential circuits Applies to signal independent portion of charge injection error, and clock feedthrough error Complementary Switches Error cancelled for 1 input level W L C ( V V V ) = W L C ( V V ) n n ox CLK IN TH, n p p ox IN TH, p Clock feedthrough cancelled depending on similarity of overlap capacitance for PMOS and NMOS switches 21
22 Charge Error Cancellation Dummy Switch Use second transistor to remove charge injection by main transistor Inverted clock operates on dummy switch Charge from M1: qm1 = W1 L1C ox( VCK VIN VTH 1) / 2 Charge from M2: qm2 = W2 L2Cox ( VCK VIN VTH 2) If charge splits equally in M1 (not quite true), then with M2 half the size of M1, q = q M1 M2 22
23 Sample and Hold Amplifier Input dependent charge from S 1 onto C When S 1 turns off, charge q adds to C V OUT is then equal to V IN +q/c where q has a nonlinear dependence on V IN We can improve on this by making V OUT independent of inputdependent charge 23
24 Two phases S/H Amplifier Phase 1: S 1 and S 2 closed, V IN sampled on C Phase 2: S 3 closed, C is tied to V OUT Phase 1 Charge on C is CV IN S 2 opens, injecting signal indep. charge at node X Then S 1 opens, injecting signal dependent charge q onto C + C p 24
25 Phase 2 S/H Amplifier S 3 closes, node X is a virtual ground Charge on C p is zero, charge on C is still CV IN S 3 injects charge on X that must be discharged due to virtual ground node it does not disturb charge on C V OUT = V IN S 1 / S 3 are nonoverlapping, S 2 slightly ahead of S 1 25
26 Gain of the S/H Finite OTA gain reduces gain of sampler On Phase 1, C charges to V IN On Phase 2, node X goes from 0 to V X = V OUT /A Charge comes from C, changing q C to CV IN + C p V X V OUT  (CV IN + C p V X )/C = V X V OUT VIN = 1 Cp 1+ 1 A + C 1 Cp VIN A C 26
27 Speed of the S/H In sampling mode (Phase 1) At node X, R X ~ 1/G M, τ 1 ~ (R on1 +1/G M )C In amplification mode (Phase 2) Replace charge on C by voltage source V IN (like switching in voltage source at start of Phase 2) After analysis, τ 2 = (C L C p +C p C+CC L )/G M C Reduces to τ 2 ~ C L /G M if C p is small 27
28 Basic Amplifier Sampling phase when S 1 and S 2 closed Input signal sampled onto C 1 Amplifying phase when S 3 closed Charge on C 1 transferred to C 2 so that the final output is C1 VOUT = VIN C 2 28
29 Basic Amplifier S 2 must open before S 1 for the charge injection to be signal independent Charge from S 2 opening is deposited on C 1, but is not signal dependent Charge from S 1 opening causes glitch in V OUT When S 3 closes, V OUT goes to final value, regardless of what happened between S 2 opening and S 3 closing 29
30 Precision Gain2 Sampling phase when S 1, S 2, S 3 closed Input signal sampled onto C 1 and C 2 Amplifying phase when S 4, S 5 closed Charge on C 1 is transferred to C 2, doubling the charge on C 2 Final output is 2V IN since C 1 = C 2 30
31 Precision Gain2 How is it more precise? The feedback factor in both gain circuits is C2 C + C + C 2 1 p In the precision Gain2 circuit, C 1 = C 2 The basic amplifier has C 1 = 2C 2, resulting in a smaller feedback factor and a slower circuit The gain error is inversely proportional to the feedback factor, so the precision circuit is more accurate for a given amplifier gain A V OUT V IN C2 + C1 + C 2 1 AC2 p 31
32 Resistor Equivalence of SC Average current through switchedcapacitor φ : Q = CV φ : Q = CV Q1 Q2 C( V1 V2 ) IAVG = = T T Equivalent current through a resistor (f IN << f S ) I EQ V V = R 1 2 EQ R EQ T = = C 1 Cf S 32
33 SwitchedCapacitor Integrator Two nonoverlapping clock phases control S 1,S 2 Phase 1: Sampling phase input is sampled onto capacitor C 1 Phase 2: Integrating phase additional charge is added to previous charge on C 2 33
34 SwitchedCapacitor Integrator VO[n]C2 +VO[n]C2 VO[n]C2+VI[n]C1 +VO[n]C2VI[n]C1 Final charge on L.S. of C 2 is +V O [n+1]c 2 + V [ n + 1] C = + V [ n] C V[ n] C O 2 O 2 I 1 zv ( z) C = V ( z) C V ( z) C O 2 O 2 I 1 V V O I ( z) = C1 C z
35 Parasitic Sensitive Parasitic capacitances C p1, C p3 and C p4 have no impact on transfer function C p2 in parallel with C 1, changes transfer function V ( C1 + Cp2) O 1 ( z ) = V C z 1 I 2 35
36 Parasitic Insensitive Transfer function is noninverting, delaying V V O I ( z) = C1 1 C z
37 Parasitic Insensitive Parasitics have no impact on transfer function Better linearity since nonlinear capacitors are unimportant Top plate on virtual ground node Minimizes parasitics, improves amplifier speed and resolution, reduces noise coupled to node Two extra switches needed More power to drive the switches for the same onresistance 37
38 DelayFree Integrator Same structure, still parasitic insensitive Transfer function is inverting, delayfree VO C1 z ( z) = V C z 1 I 2 38
39 Bootstrapping At low supply voltages, signal swing is limited Maximum distortion determines the tolerable variation in R ON, and this limits the signal swing Want to increase V GS on the sampling switch Can do this by increasing the supply voltage for the sampling switch, but this requires slower thick oxide devices Alternatively, add a constant voltage to the input signal and use that as the gate voltage keep V GS constant, reducing the variation in R ON 39
40 Bootstrapped Circuit Basic operation φ 2 : C is charged to V DD and gate of sampling switch is discharged to V SS (turned off) φ 1 : V IN is added to voltage across C, sampling switch turns on, gate voltage of the sampling switch is V IN + V DD Ideally, there is always V GS = V DD for the sampling switch 40
41 Bootstrapped Circuit C must be sized so that charge sharing between gate capacitance of switch is not significant C VG = ( VIN + VDD ) C + C Rise time controlled by size of S 4, fall time controlled by size of S 5 G Extra transistors required to limit gatesource voltages to V DD and prevent overstress See Dessouky, JSSC Mar
42 SwitchedCapacitor CMFB Two parts to a CMFB circuit 1. Sense the common mode of the output 2. Compare the common mode to the expected common mode, and adjust the bias accordingly Sensing Could use 2 resistors they are either too small and reduce the gain, or they can get prohibitively large Could use 2 capacitors they don t reduce the gain, but the voltage across them is undefined and must be refreshed every clock cycle 42
43 SwitchedCapacitor CMFB One alternative Phase 1: precharge capacitors to ideal value Phase 2: sense the difference and adjust the bias accordingly 2 1 V CM V B1 C C 2 1 V CM V IN + V IN  C P 1 V B2 But there may be large changes in the tail current bias 43
44 SwitchedCapacitor CMFB Alternatively, use 2 capacitors so that only a fraction of the charge is shared to adjust the bias voltage Typically, C 2 is 410 times C 1 44
45 What You Learned Today Errors introduced with simple sampling switch R ON variation, charge injection Main SC Circuits S/H, Gain and Integrators Parasitic Insensitive Signalindependent charge injection Bootstrapped Circuit Switched Capacitor CMFB 45
46 NLCOTD: Schmitt Trigger 46
Chapter 13: Introduction to Switched Capacitor Circuits
Chapter 13: Introduction to Switched Capacitor Circuits 13.1 General Considerations 13.2 Sampling Switches 13.3 SwitchedCapacitor Amplifiers 13.4 SwitchedCapacitor Integrator 13.5 SwitchedCapacitor
More informationAdvanced Operational Amplifiers
IsLab Analog Integrated Circuit Design OPA247 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA21 Advanced Current Mirrors and Opamps Twostage
More informationA Unity Gain FullyDifferential 10bit and 40MSps SampleAndHold Amplifier in 0.18μm CMOS
A Unity Gain FullyDifferential 0bit and 40MSps SampleAndHold Amplifier in 0.8μm CMOS Sanaz Haddadian, and Rahele Hedayati Abstract A 0bit, 40 MSps, sample and hold, implemented in 0.8μm CMOS technology
More informationLowPower Pipelined ADC Design for Wireless LANs
LowPower Pipelined ADC Design for Wireless LANs J. Arias, D. Bisbal, J. San Pablo, L. Quintanilla, L. Enriquez, J. Vicente, J. Barbolla Dept. de Electricidad y Electrónica, E.T.S.I. de Telecomunicación,
More informationECEN620: Network Theory Broadband Circuit Design Fall 2014
ECEN620: Network Theory Broadband Circuit Design Fall 2014 Lecture 8: Charge Pump Circuits Sam Palermo Analog & MixedSignal Center Texas A&M University Announcements & Agenda HW2 is due Oct 6 Exam 1 is
More informationLecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 11
Lecture 16 Complementary metal oxide semiconductor (CMOS) CMOS 11 Outline Complementary metal oxide semiconductor (CMOS) Inverting circuit Properties Operating points Propagation delay Power dissipation
More informationSummary of Last Lecture
EE47 Lecture 7 DAC Converters (continued) Dynamic element matching DAC reconstruction filter ADC Converters Sampling Sampling switch considerations Thermal noise due to switch resistance Sampling switch
More informationChapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier
Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in doubleended
More informationCommonSource Amplifiers
Lab 2: CommonSource Amplifiers Introduction The commonsource stage is the most basic amplifier stage encountered in CMOS analog circuits. Because of its very high input impedance, moderatetohigh gain,
More informationDifference between BJTs and FETs. Junction Field Effect Transistors (JFET)
Difference between BJTs and FETs Transistors can be categorized according to their structure, and two of the more commonly known transistor structures, are the BJT and FET. The comparison between BJTs
More informationBasic OpAmp Design and Compensation. Chapter 6
Basic OpAmp Design and Compensation Chapter 6 6.1 OpAmp applications Typical applications of OpAmps in analog integrated circuits: (a) Amplification and filtering (b) Biasing and regulation (c) Switchedcapacitor
More informationDesign of HighSpeed OpAmps for Signal Processing
Design of HighSpeed OpAmps for Signal Processing R. Jacob (Jake) Baker, PhD, PE Professor and Chair Boise State University 1910 University Dr. Boise, ID 837252075 jbaker@ieee.org Abstract  As CMOS
More informationCHAPTER 3 DESIGN OF PIPELINED ADC USING SCSCDS AND OPAMP SHARING TECHNIQUE
CHAPTER 3 DESIGN OF PIPELINED ADC USING SCSCDS AND OPAMP SHARING TECHNIQUE 3.1 INTRODUCTION An ADC is a device which converts a continuous quantity into discrete digital signal. Among its types, pipelined
More informationOperational Amplifier with TwoStage GainBoost
Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization, Lisbon, Portugal, September 2224, 2006 482 Operational Amplifier with TwoStage GainBoost FRANZ SCHLÖGL
More informationA PSEUDOCLASSAB TELESCOPICCASCODE OPERATIONAL AMPLIFIER
A PSEUDOCLASSAB TELESCOPICCASCODE OPERATIONAL AMPLIFIER M. TaherzadehSani, R. Lotfi, and O. Shoaei ABSTRACT A novel classab architecture for singlestage operational amplifiers is presented. The structure
More informationAnalysis and Design of Analog Integrated Circuits Lecture 18. Key Opamp Specifications
Analysis and Design of Analog Integrated Circuits Lecture 8 Key Opamp Specifications Michael H. Perrott April 8, 0 Copyright 0 by Michael H. Perrott All rights reserved. Recall: Key Specifications of Opamps
More informationNOISE IN SC CIRCUITS
ECE37 Advanced Analog Circuits Lecture 0 NOISE IN SC CIRCUITS Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca Course Goals Deepen Understanding of CMOS analog circuit
More informationA Successive Approximation ADC based on a new Segmented DAC
A Successive Approximation ADC based on a new Segmented DAC segmented currentmode DAC successive approximation ADC bidirection segmented currentmode DAC DAC INL 0.47 LSB DNL 0.154 LSB DAC 3V 8 2MS/s
More informationLab 8: SWITCHED CAPACITOR CIRCUITS
ANALOG & TELECOMMUNICATION ELECTRONICS LABORATORY EXERCISE 8 Lab 8: SWITCHED CAPACITOR CIRCUITS Goal The goals of this experiment are:  Verify the operation of basic switched capacitor cells,  Measure
More informationChapter 12 Opertational Amplifier Circuits
1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS opamp architectures: the twostage circuit and the singlestage, folded cascode circuit.
More informationAnalysis and Design of Analog Integrated Circuits Lecture 20. Advanced Opamp Topologies (Part II)
Analysis and Design of Analog Integrated Circuits Lecture 20 Advanced Opamp Topologies (Part II) Michael H. Perrott April 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Outline of Lecture
More informationOp Amp Technology Overview. Developed by Art Kay, Thomas Kuehl, and Tim Green Presented by Ian Williams Precision Analog Op Amps
Op Amp Technology Overview Developed by Art Kay, Thomas Kuehl, and Tim Green Presented by Ian Williams Precision Analog Op Amps 1 Bipolar vs. CMOS / JFET Transistor technologies Bipolar, CMOS and JFET
More informationBasic OpAmp Design and Compensation. Chapter 6
Basic OpAmp Design and Compensation Chapter 6 6.1 OpAmp applications Typical applications of OpAmps in analog integrated circuits: (a) Amplification and filtering (b) Biasing and regulation (c) Switchedcapacitor
More informationSelfBiased PLL/DLL. ECG minute Final Project Presentation. Wenlan Wu Electrical and Computer Engineering University of Nevada Las Vegas
SelfBiased PLL/DLL ECG721 60minute Final Project Presentation Wenlan Wu Electrical and Computer Engineering University of Nevada Las Vegas Outline Motivation SelfBiasing Technique Differential Buffer
More informationECEN689: Special Topics in HighSpeed Links Circuits and Systems Spring 2010
ECEN689: Special Topics in HighSpeed Links Circuits and Systems Spring 010 Lecture 7: PLL Circuits Sam Palermo Analog & MixedSignal Center Texas A&M University Announcements Project Preliminary Report
More informationChapter 9: Operational Amplifiers
Chapter 9: Operational Amplifiers The Operational Amplifier (or opamp) is the ideal, simple amplifier. It is an integrated circuit (IC). An IC contains many discrete components (resistors, capacitors,
More informationLecture 300 Low Voltage Op Amps (3/28/10) Page 3001
Lecture 300 Low Voltage Op Amps (3/28/10) Page 3001 LECTURE 300 LOW VOLTAGE OP AMPS LECTURE ORGANIZATION Outline Introduction Low voltage input stages Low voltage gain stages Low voltage bias circuits
More informationRailToRail Output OpAmp Design with Negative Miller Capacitance Compensation
RailToRail OpAmp Design with Negative Miller Capacitance Compensation Muhaned Zaidi, Ian Grout, Abu Khari bin A ain Abstract In this paper, a twostage opamp design is considered using both Miller
More informationA Compact Foldedcascode Operational Amplifier with ClassAB Output Stage
A Compact Foldedcascode Operational Amplifier with ClassAB Output Stage EEE 523 Advanced Analog Integrated Circuits Project Report Fuding Ge You are an engineer who is assigned the project to design
More informationSystem on a Chip. Prof. Dr. Michael Kraft
System on a Chip Prof. Dr. Michael Kraft Lecture 4: Filters Filters General Theory Continuous Time Filters Background Filters are used to separate signals in the frequency domain, e.g. remove noise, tune
More informationLesson number one. Operational Amplifier Basics
What About Lesson number one Operational Amplifier Basics As well as resistors and capacitors, Operational Amplifiers, or Opamps as they are more commonly called, are one of the basic building blocks
More information6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers
6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott Broadband Communication
More informationLow Voltage SC Circuit Design with Low  V t MOSFETs
Low Voltage SC Circuit Design with Low  V t MOSFETs Seyfi S. azarjani and W. Martin Snelgrove Department of Electronics, Carleton University, Ottawa Canada K1S56 Tel: (613)7638473, Email: seyfi@doe.carleton.ca
More informationTopology Selection: Input
Project #2: Design of an Operational Amplifier By: Adrian Ildefonso Nedeljko Karaulac I have neither given nor received any unauthorized assistance on this project. Process: Baker s 50nm CAD Tool: Cadence
More informationEE247 Lecture 20. Comparator architecture examples Flash ADC sources of error Sparkle code Metastability
EE247 Lecture 2 ADC Converters ADC architectures (continued) Comparator architectures Latched comparators Latched comparators incorporating preamplifier Sampledata comparators Offset cancellation Comparator
More informationEECS 247 Lecture 18: Data Converters Track & Hold ADC Design 2009 Page 1. EE247 Lecture 18
EE247 Lecture 8 ADC Converters Sampling (continued) Bottomplate switching Track & hold T/H circuits T/H combined with summing/difference function T/H circuit incorporating gain & offset cancellation T/H
More informationMICROELECTRONIC CIRCUIT DESIGN Third Edition
MICROELECTRONIC CIRCUIT DESIGN Third Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 1/25/08 Chapter 1 1.3 1.52 years, 5.06 years 1.5 1.95 years, 6.46 years 1.8 113
More informationECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers
ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic
More informationINF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation
INF3410 Fall 2013 Compensation content Introduction Two Stage Opamps Compensation Slew Rate Systematic Offset Advanced Current Mirrors Operational Transconductance Amplifiers Current Mirror Opamps Folded
More informationECEN 474/704 Lab 8: TwoStage Miller Operational Amplifier
ECEN 474/704 Lab 8: TwoStage Miller Operational Amplifier Objective Design, simulate and test a twostage operational amplifier Introduction Operational amplifiers (opamp) are essential components of
More informationDesign of Pipeline Analog to Digital Converter
Design of Pipeline Analog to Digital Converter Vivek Tripathi, Chandrajit Debnath, Rakesh Malik STMicroelectronics The pipeline analogtodigital converter (ADC) architecture is the most popular topology
More informationECEN 5008: Analog IC Design. Final Exam
ECEN 5008 Initials: 1/10 ECEN 5008: Analog IC Design Final Exam Spring 2004 Instructions: 1. Exam Policy: Timelimited, 150minute exam. When the time is called, all work must stop. Put your initials on
More informationHow to turn an ADC into a DAC: A 110dB THD, 18mW DAC using sampling of the output and feedback to reduce distortion
How to turn an ADC into a DAC: A 110dB THD, 18mW DAC using sampling of the output and feedback to reduce distortion Axel Thomsen, Design Manager Silicon Laboratories Inc. Austin, TX 1 Why this talk? A
More informationLecture 20: Passive Mixers
EECS 142 Lecture 20: Passive Mixers Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California, Berkeley EECS 142 Lecture 20 p.
More information10Bit 5MHz Pipeline A/D Converter. Kannan Sockalingam and Rick Thibodeau
10Bit 5MHz Pipeline A/D Converter Kannan Sockalingam and Rick Thibodeau July 30, 2002 Contents 1 Introduction 8 1.1 Project Overview........................... 8 1.2 Objective...............................
More informationA low voltage railtorail operational amplifier with constant operation and improved process robustness
Graduate Theses and Dissertations Graduate College 2009 A low voltage railtorail operational amplifier with constant operation and improved process robustness Rien Lerone Beal Iowa State University Follow
More information6.776 High Speed Communication Circuits and Systems Lecture 14 Voltage Controlled Oscillators
6.776 High Speed Communication Circuits and Systems Lecture 14 Voltage Controlled Oscillators Massachusetts Institute of Technology March 29, 2005 Copyright 2005 by Michael H. Perrott VCO Design for Narrowband
More informationHW#3 Solution. Dr. Parker. Spring 2014
HW#3 olution r. Parker pring 2014 Assume for the problems below that V dd = 1.8 V, V tp0 is .7 V. and V tn0 is.7 V. V tpbodyeffect is .9 V. and V tnbodyeffect is.9 V. Assume ß n (k n )= 219.4 W/L µ A(microamps)/V
More informationDESIGN OF A FULLY DIFFERENTIAL HIGHSPEED HIGHPRECISION AMPLIFIER
DESIGN OF A FULLY DIFFERENTIAL HIGHSPEED HIGHPRECISION AMPLIFIER Mayank Gupta mayank@ee.ucla.edu N. V. Girish envy@ee.ucla.edu Design I. Design II. University of California, Los Angeles EE215A Term Project
More informationAdministrative. No office hour on Thurs. this week Instead, office hour 3 to 4pm on Wed.
Administrative No office hour on Thurs. this week Instead, office hour 3 to 4pm on Wed. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page EE247 Lecture 2 ADC Converters Sampling (continued)
More informationTechnologyIndependent CMOS Op Amp in Minimum Channel Length
TechnologyIndependent CMOS Op Amp in Minimum Channel Length A Thesis Presented to The Academic Faculty by Susanta Sengupta In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
More informationVoltage Feedback Op Amp (VFOpAmp)
Data Sheet Voltage Feedback Op Amp (VFOpAmp) Features 55 db dc gain 30 ma current drive Less than 1 V head/floor room 300 V/µs slew rate Capacitive load stable 40 kω input impedance 300 MHz unity gain
More informationDesign of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching
RESEARCH ARTICLE OPEN ACCESS Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching Annu Saini, Prity Yadav (M.Tech. Student, Department
More informationChapter 10: Operational Amplifiers
Chapter 10: Operational Amplifiers Differential Amplifier Differential amplifier has two identical transistors with two inputs and two outputs. 2 Differential Amplifier Differential amplifier has two identical
More informationDEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS 02139
DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS 019.101 Introductory Analog Electronics Laboratory Laboratory No. READING ASSIGNMENT
More informationWideband Sampling by Decimation in Frequency
Wideband Sampling by Decimation in Frequency Martin Snelgrove http://www.kapik.com 192 Spadina Ave. Suite 218 Toronto, Ontario, M5T2C2 Canada Copyright Kapik Integration 2011 WSG: New Architectures for
More informationA 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Builtin Digital Error Correction Logic
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Builtin Digital Error Correction Logic Abstract P.Prasad Rao 1 and Prof.K.Lal Kishore 2, 1 Research Scholar, JNTUHyderabad prasadrao_hod@yahoo.co.in
More informationCHAPTER. deltasigma modulators 1.0
CHAPTER 1 CHAPTER Conventional deltasigma modulators 1.0 This Chapter presents the traditional first and secondorder DSM. The main sources for nonideal operation are described together with some commonly
More informationUltra Lowvoltage Multipleloop Feedback Switchedcapacitor Filters
Ultra Lowvoltage Multipleloop Feedback Switchedcapacitor Filters By Udhayasimha Puttamreddy Submitted in partial fulfilment of the requirements For the degree of Master of Applied Science At Dalhousie
More informationOperational Amplifier BME 360 Lecture Notes Ying Sun
Operational Amplifier BME 360 Lecture Notes Ying Sun Characteristics of OpAmp An operational amplifier (opamp) is an analog integrated circuit that consists of several stages of transistor amplification
More information2. Single Stage OpAmps
/74 2. Single Stage OpAmps Francesc Serra Graells francesc.serra.graells@uab.cat Departament de Microelectrònica i Sistemes Electrònics Universitat Autònoma de Barcelona paco.serra@imbcnm.csic.es Integrated
More informationCombination Notch and Bandpass Filter
Combination Notch and Bandpass Filter Clever filter design for graphic equalizer can perform both notch and bandpass functions Gain or attenuation is controlled by a potentiometer for specific frequency
More informationLecture 10: Accelerometers (Part I)
Lecture 0: Accelerometers (Part I) ADXL 50 (Formerly the original ADXL 50) ENE 5400, Spring 2004 Outline Performance analysis Capacitive sensing Circuit architectures Circuit techniques for nonideality
More informationDesign of a 100 MHz, 5 th Order Elliptic, LowPass Switched Capacitor Filter
Design of a 100 MHz, 5 th Order Elliptic, LowPass Switched Capacitor Filter 1 Jon Guerber, ECE 626, Student Member, IEEE Abstract The design and simulation of an Elliptic switched capacitor filter with
More informationPrecision Rectifier Circuits
Precision Rectifier Circuits Rectifier circuits are used in the design of power supply circuits. In such applications, the voltage being rectified are usually much greater than the diode voltage drop,
More informationLecture 240 Cascode Op Amps (3/28/10) Page 2401
Lecture 240 Cascode Op Amps (3/28/10) Page 2401 LECTURE 240 CASCODE OP AMPS LECTURE ORGANIZATION Outline Lecture Organization Single Stage Cascode Op Amps Two Stage Cascode Op Amps Summary CMOS Analog
More informationChapter 10 Feedback ECE 3120 Microelectronics II Dr. Suketu Naik
1 Chapter 10 Feedback Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: ActiveLoaded Differential Pair 4. Ch 10: Feedback 5. Ch 11: Output
More informationA LOW POWER, HIGH DYNAMIC RANGE, BROADBAND VARIABLE GAIN AMPLIFIER FOR AN ULTRA WIDEBAND RECEIVER. A Thesis LIN CHEN
A LOW POWER, HIGH DYNAMIC RANGE, BROADBAND VARIABLE GAIN AMPLIFIER FOR AN ULTRA WIDEBAND RECEIVER A Thesis by LIN CHEN Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment
More informationLow Cost, General Purpose High Speed JFET Amplifier AD825
a FEATURES High Speed 41 MHz, 3 db Bandwidth 125 V/ s Slew Rate 8 ns Settling Time Input Bias Current of 2 pa and Noise Current of 1 fa/ Hz Input Voltage Noise of 12 nv/ Hz Fully Specified Power Supplies:
More informationUMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency
UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency Jamie E. Reinhold December 15, 2011 Abstract The design, simulation and layout of a UMAINE ECE Morse code Read Only Memory and transmitter
More informationMetalOxideSilicon (MOS) devices PMOS. ntype
MetalOxideSilicon (MOS devices Principle of MOS Field Effect Transistor transistor operation Metal (poly gate on oxide between source and drain Source and drain implants of opposite type to substrate.
More informationDAT175: Topics in Electronic System Design
DAT175: Topics in Electronic System Design Analog Readout Circuitry for Hearing Aid in STM90nm 21 February 2010 Remzi Yagiz Mungan v1.10 1. Introduction In this project, the aim is to design an adjustable
More informationSingleStage Integrated Circuit Amplifiers
SingleStage Integrated Circuit Amplifiers Outline Comparison between the MOS and the BJT From discrete circuit to integrated circuit  Philosophy, Biasing, etc. Frequency response The CommonSource and
More informationOperational Amplifiers
Monolithic Amplifier Circuits: Operational Amplifiers Chapter Jón Tómas Guðmundsson tumi@hi.is. Week Fall 200 Operational amplifiers (op amps) are an integral part of many analog and mixedsignal systems
More informationEECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design
EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design References: Analog Integrated Circuit Design by D. Johns and K. Martin and Design of Analog CMOS Integrated Circuits by B. Razavi All figures
More informationSecondOrder SigmaDelta Modulator in Standard CMOS Technology
SERBIAN JOURNAL OF ELECTRICAL ENGINEERING Vol. 1, No. 3, November 2004, 3744 SecondOrder SigmaDelta Modulator in Standard CMOS Technology Dragiša Milovanović 1, Milan Savić 1, Miljan Nikolić 1 Abstract:
More informationChapter 13: Comparators
Chapter 13: Comparators So far, we have used op amps in their normal, linear mode, where they follow the op amp Golden Rules (no input current to either input, no voltage difference between the inputs).
More informationChapter 11 Operational Amplifiers and Applications
Chapter Operational Amplifiers and Applications Chapter Goals Understand the magic of negatie feedback and the characteristics of ideal op amps. Understand the conditions for nonideal op amp behaior so
More informationHigh Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers
High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers Michael H. Perrott March 19, 2004 Copyright 2004 by Michael H. Perrott All rights reserved. 1 High Speed Frequency
More information6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain Bandwidth Issue for Broadband Amplifiers
6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain Bandwidth Issue for Broadband Amplifiers Massachusetts Institute of Technology February 17, 2005 Copyright 2005
More informationLaboratory #9 MOSFET Biasing and Current Mirror
Laboratory #9 MOSFET Biasing and Current Mirror. Objectives 1. Review the MOSFET characteristics and transfer function. 2. Understand the relationship between the bias, the input signal and the output
More informationSingle Supply, Rail to Rail Low Power FETInput Op Amp AD820
a FEATURES True Single Supply Operation Output Swings RailtoRail Input Voltage Range Extends Below Ground Single Supply Capability from + V to + V Dual Supply Capability from. V to 8 V Excellent Load
More informationMOS TRANSISTOR THEORY
MOS TRANSISTOR THEORY Introduction A MOS transistor is a majoritycarrier device, in which the current in a conducting channel between the source and the drain is modulated by a voltage applied to the
More informationMOS IC Amplifiers. Token Ring LAN JSSC 12/89
MO IC Amplifiers MOFETs are inferior to BJTs for analog design in terms of quality per silicon area But MO is the technology of choice for digital applications Therefore, most analog portions of mixedsignal
More informationTuesday, March 1st, 9:15 11:00. Snorre Aunet Nanoelectronics group Department of Informatics University of Oslo.
Nyquist Analog to Digital it Converters Tuesday, March 1st, 9:15 11:00 Snorre Aunet (sa@ifi.uio.no) Nanoelectronics group Department of Informatics University of Oslo 3.1 Introduction 3.1.1 DAC applications
More informationLow Voltage Standard CMOS Opamp Design Techniques
Low Voltage Standard CMOS Opamp Design Techniques Student name: Eliyahu Zamir Student number: 961339780 Course: ECE1352F Proffessor: Khoman Phang Page 1 of 18 1.Abstract In a neverending effort to reduce
More informationEKT 314 ELECTRONIC INSTRUMENTATION
EKT 314 ELECTRONIC INSTRUMENTATION Elektronik Instrumentasi Semester 2 2012/2013 Chapter 3 Analog Signal Conditioning Session 2 Mr. Fazrul Faiz Zakaria school of computer and communication engineering.
More informationAmplifier Frequency Response, Feedback, Oscillations; OpAmp Block Diagram and GainBandwidth Product
Amplifier Frequency Response, Feedback, Oscillations; OpAmp Block Diagram and GainBandwidth Product Physics116A,12/4/06 Draft Rev. 1, 12/12/06 D. Pellett 2 Negative Feedback and Voltage Amplifier AB
More informationA 42 fj 8bit 1.0GS/s folding and interpolating ADC with 1 GHz signal bandwidth
LETTER IEICE Electronics Express, Vol.11, No.2, 1 9 A 42 fj 8bit 1.0GS/s folding and interpolating ADC with 1 GHz signal bandwidth Mingshuo Wang a), Fan Ye, Wei Li, and Junyan Ren b) State Key Laboratory
More informationECE520 VLSI Design. Lecture 5: Basic CMOS Inverter. Payman ZarkeshHa
ECE520 VLSI Design Lecture 5: Basic CMOS Inverter Payman ZarkeshHa Office: ECE Bldg. 230B Office hours: Wednesday 2:003:00PM or by appointment Email: pzarkesh@unm.edu Slide: 1 Review of Last Lecture
More informationTuesday, February 1st, 9:15 12:00. Snorre Aunet Nanoelectronics group Department of Informatics University of Oslo
Bandgap references, sampling switches Tuesday, February 1st, 9:15 12:00 Snorre Aunet (sa@ifi.uio.no) Nanoelectronics group Department of Informatics University of Oslo Outline Tuesday, February 1st 11.11
More informationBasic Layout Techniques
Basic Layout Techniques Rahul Shukla Advisor: Jaime RamirezAngulo Spring 2005 Mixed Signal VLSI Lab Klipsch School of Electrical and Computer Engineering New Mexico State University Outline Transistor
More information55:041 Electronic Circuits
55:041 Electronic Circuits MOSFETs Sections of Chapter 3 &4 A. Kruger MOSFETs, Page1 Basic Structure of MOS Capacitor Sect. 3.1 Width = 1 106 m or less Thickness = 50 109 m or less ` MOS MetalOxideSemiconductor
More informationLecture 11 Circuits numériques (I) L'inverseur
Lecture 11 Circuits numériques (I) L'inverseur Outline Introduction to digital circuits The inverter NMOS inverter with resistor pullup 6.12 Spring 24 Lecture 11 1 1. Introduction to digital circuits:
More informationIJSRD  International Journal for Scientific Research & Development Vol. 4, Issue 02, 2016 ISSN (online):
IJSRD  International Journal for Scientific Research & Development Vol. 4, Issue 02, 2016 ISSN (online): 23210613 Design & Analysis of CMOS Telescopic Operational Transconductance Amplifier (OTA) with
More informationDESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT
DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT PRADEEP G CHAGASHETTI Mr. H.V. RAVISH ARADHYA Department of E&C Department of E&C R.V.COLLEGE of ENGINEERING R.V.COLLEGE of ENGINEERING Bangalore
More information6.976 High Speed Communication Circuits and Systems Lecture 11 Voltage Controlled Oscillators
6.976 High Speed Communication Circuits and Systems Lecture 11 Voltage Controlled Oscillators Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott VCO Design for Wireless
More informationBasic Operational Amplifier Circuits
Basic Operational Amplifier Circuits Comparators A comparator is a specialized nonlinear opamp circuit that compares two input voltages and produces an output state that indicates which one is greater.
More informationAN742 APPLICATION NOTE
APPLICATION NOTE One Technology Way P.O. Box 9106 Norwood, MA 020629106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 www.analog.com Frequency Domain Response of SwitchedCapacitor ADCs by Rob Reeder INTRODUCTION
More informationDepletionmode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET
Ch. 13 MOSFET MetalOxideSemiconductor FieldEffect Transistor : I D Dmode Emode V g The gate oxide is made of dielectric SiO 2 with e = 3.9 Depletionmode operation ( 공핍형 ): Using an input gate voltage
More information