AVoltage Controlled Oscillator (VCO) was designed and

Transcription

1 1 EECE 457 VCO Design Project Jason Khuu, Erik Wu Abstract This paper details the design and simulation of a Voltage Controlled Oscillator using a 0.13µm process. The final VCO design meets all specifications. The VCO designs considered were a complimentary cross-coupled topology and NMOS-only cross-coupled topology. Presented in this paper are the design methods used. The complimentary cross-coupled topology had poor phase noise performance, so an NMOS-only cross-coupled topology was used instead. By using an iterative process of changing one design parameter at a time, a set of baseline design parameters were found that met all the performance specifications. Lastly, the design and device parameters and performance of the optimized VCO is presented. I. INTRODUCTION AVoltage Controlled Oscillator (VCO) was designed and simulated using an NMOS-only topology seen in Figure 1. The specifications of the VCO are to be as follows: Center Frequency f = 2.4GHz with a tuning range of 11%, and phase noise of < 600kHz offset and < 1MHz offset. A load capacitance of 80fF is used in place of an LO buffer or Mixer. Fig. 2. Inductor π-model Fig. 3. Quality factor of Inductor π-model Fig. 1. NMOS-only Cross Coupled VCO II. FIRST PASS CALCUATIONS Based on the class inductor pi-model seen in figure 2 (schematic in Appendix B), an inductor with maximum quality factor was chosen. Because the inductors in the circuit would be placed with one end in a virtual ground in the complimentary cross coupled topology or V dd in the NMOS-only cross-coupled topology, the inductor model was taken to only have one branch of the pi-model. The quality factor of the inductor model is shown in figure 3. A maximum quality factor is desired in order to reduce phase noise. This occurs when L = 4nH. The equivalent parallel resistance of this inductor is approximately R p = 613Ω, and the equivalent parallel inductance is approximately 4.77nH. After choosing the inductor, the differential voltage swing was used to determine the required power for the circuit. Using equation 1 below for a complementary cross-coupled topology, the tail current I ss was calculated to be 0.65mA for a differential voltage swing of 1V. V swing = 8 π I ssr p (1) For an NMOS-only topology, equation 2 below was used. In this case, I ss = 1.3mA. V swing = 4 π I ssr p (2) The startup condition for an NMOS-only cross coupled oscillator is as shown in equation 3. Using R p as found above,

2 2 and choosing a startup factor α of 2.5, the required transconductance g m of the NMOS transistors is approximately 4mS. With I ss and g m set, the width of the NMOS transistor was found in simulation to be 10µm. g m R p > 1, g m R p = α (3) The tuning range of the oscillator is specified to be 11%. At a center frequency of 2.4GHz, this implies an upper bound f max = 2.532GHz and a lower bound of f min = 2.268GHz. Using equation 4, the required capacitance is approximately C = 920fF. The fixed capacitances in the NMOS-only topology (Load Capacitance, and various parasitic capacitances of the NMOS transistors) amount to approximately 250f F and about 300f F in the complimentary cross-coupled topology, which means that about 670fF needs to be supplied by the varactors. For f max, the varactors need to supply 560fF, and for f min, the varactors need to supply about 760fF. 1 f = 2π LC The varactors are simply an NMOS transistor that has the drain tied to its source. By varying the voltage across the gate and source, the capacitance of the device changes. From a quick simulation in figure 4, it is found that a varactor with a width of approximately 400µm has a capacitance range of 460fF to 910fF. The varactors only seemed to vary within a range of about 300mV. (4) specification. This is possibly attributed to the two PMOS transistors in the topology. Because an improvement of 30dBc seemed highly unlikely by just adjusting design variables, the NMOS-only topology was used instead. This topology has fewer transistors, so there are fewer sources of thermal noise. The simulation results for the NMOS-only topology showed that the tuning range specification was met, but the oscillation frequency was off. However, the phase noise was much better than the complimentary cross-coupled topology, but it still missed the target by 10dBc. The simulated oscillation frequency was 2.375GHz which was close to the required center frequency of 2.4GHz. The varactors were made smaller to bring the center frequency up to 2.4GHz. IV. OPTIMIZATION In order to improve phase noise, the power consumption had to be increased. The tail current I ss and NMOS width were scaled up by a factor of 2, then the tail current was further brought up to further reduce phase noise. A parametric sweep was done to find the optimal tail current of 3.8mA, and any more current beyond this point would not be effective due to the oscillator operating in the voltage-limited region. Because the tail current was brought up so high, the output voltage swing also increased. There did not seem to be any obvious way to bring the voltage swing down to the desired level of 1V. R p is dependent only on the inductor L. In order to reduce R p, L would also need to be reduced. Doing this would lower the Q factor of the output tank and therefore increase phase noise. An alternative would be to put in a resistor in parallel to reduce the resistance, but that also adds more thermal noise. For that reason, the voltage swing of the oscillator increased to about 6V. Capacitive dividers can be used when connecting to the next stage to lower the output voltage amplitude. V. RESULTS The design parameters of the hand calculated design and final design can be found in table I. TABLE I HAND CALCULATED VS. POWER OPTIMIZED RESULTS Fig. 4. Varactor Capacitance as a function of V gs III. SIMULATION Using Cadence Virtuoso and SpectreRF, the complimentary cross-coupled VCO circuit with the first-pass calculations from section II were implemented and simulated. The simulation results showed that the tuning range was very good (about 17%), however, the phase noise was very poor. At an offset of 1MHz, the phase noise was found to be 100dBc, which is 30dBc away from the required Results Parameter Hand Calculation Simulation L 4nH 4nH R p(ω) 613Ω 613Ω g m3,4 (ms) 4mS 11.34mS W/L 10µm/0.13µm 20µm/0.13µm V swing (V ) 1V 6V f center (Hz) 2.4GHz 2.405GHz f min (Hz) 2.268GHz 2.273GHz f max (Hz) 2.532GHz 2.547GHz T uningrange 11% 11.41% I bias(total) 1.3mA 3.8mA P ower(mw ) 1.56mW 5.11mW The operating points of the transistors can be seen in table II.

3 3 TABLE II DC OPERATING POINTS OF TRANSISTORS Parameter Switching Transistors Varactors C gg 41.61fF 841.9fF C gd 9.19fF 349fF C gs 31.83fF 496.9fF C db 1.144fF 33.32fF g m 11.34mS N/A g ds 736.3uS 109.7mS V gs 689.6mV 590.2mV V th 433.2mV 465mV V dsat 141.6mV 90.15mV V ds 689.6mV 0mV W/L 20/ /0.13 Figure 5 shows the VCO gain plot. The tuning range is 11.41% which is 0.41% above the specification. The VCO gain is approximately 4.38mV/M Hz Figure 6 shows the phase noise relative to 2.4GHz. At 600kHz offset, the phase noise is 125.2dBc and at 1MHz phase noise it is 130.1dBc. Fig. 6. Phase Noise relative to 2.4GHz Fig. 5. VCO Gain Fig. 7. Phase 1MHz Offset Figure 7 shows the phase noise at a 1M Hz offset at different frequencies. It appears to have a very sporadic profile. Figure 8 shows the top 10 noise contributors at 1MHz offset. M3 and M4 are the switching transistors, and M5 and M6 are the varactors. The noise due to M3, M4, and the inductor s series resistance are the biggest contributors to the noise. Figure 9, 10, 11, and 12 show the single ended voltage outputs, differential voltage output, and tail current waveforms. The RMS current was measured to be 4.26mA. Fig. 8. Top 10 Noise 1MHz offset

4 4 Fig. 9. Node X Output Voltage Fig. 11. Differential Output Voltage (Vx-Vy) Fig. 10. Node Y Output Voltage VI. CONCLUSION A VCO was designed using an NMOS-only cross-coupled topology. The final set of design parameters for the VCO were optimized so that the mixer met all required performance specifications and had a power consumption of 5.11mW. This was done by first basing simulations on first-hand calculations of the design parameters. The calculated design parameters were then changed iteratively to meet all the performance specifications. Fig. 12. Tail Current

5 5 VCO Schematic APPENDIX A APPENDIX B Inductor Model Schematic