EE105 Fall 2015 Microelectronic Devices and Circuits

Transcription

1 EE105 Fall 2015 Microelectronic Devices and Circuits Multi-Stage Amplifiers Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)

2 Terminal Gain and I/O Resistances of MOS Amplifiers Common Source (CS) Common Drain (CD) Common Gate (CG) A V,t = g mr L 1+ g m R S R i = ( 1+ g m R E ) R o = #$ r o % & A I,t = Without degeneration: Simply set R S = 0 A V,t = R i = R o = 1 g m A I,t = R L 1 g m + R L A V,t = g m R L R i = 1 g m R o =!" r o ( 1+ g m R E )# $ A I,t 1 For the gain, R i, R o of the whole amplifier, you need to include voltage/current dividers at input and output stages

3 Summary of MOS Single-Transistor Amplifiers MOS Common Source Common Source with Deg. Common Drain Common Gate R i Small R o Large Very Large Small Large A V Moderate Small ~ 1 Moderate f H Small Moderate Large Large

4 Single Stage Amplifier Cannot Meet All Requirements For example, a general purpose operational amplifier requires High input resistance ~ 1MΩ Low output resistance ~ 100Ω High voltage gain ~ 100,000 No single transistor amplifier can satisfy all spec s Cascading multiple stages of amplifiers offers a path towards the design

5 Multistage Amplifiers Usually An input stage to provide required input resistance Middle stage(s) to provide gain An output stage to provide required output resistance or drive external loads More gain! Gain/stage limited, especially in nanoscale devices Improve Bandwidth De-couple high impedance nodes from large capacitors DC coupling (no passive elements to block the signal) Use amplifiers to naturally level shift signal

6 Impedance Match On-chip circuits often use voltage/current matching to minimize loading Keep in mind the input resistance and output resistance of each type of stage so that the loading does not create an undesired effect Ideal R in Ideal R out Voltage Amplifier 0 Current Amplifier 0 Transconductance Amplifier Transresistance Amplifier 0 0

7 Two-Stage Voltage Amplifier Boost gain by cascading Common-Source stages CS 1 CS 2 CS 1,2 Can combine into a single 2-port model Results of new 2-port: R in = R in1, R out = R out2

8 CS Cascade Analysis v in g m1 v in v int g m2 v int v out Results of new 2-port: R in = R in1 = R out = R out2 = A V = v out /v in =

9 CS Cascade Bandwidth v in g m1 v in v int g m2 v int v out Two time constants: τ 1 = τ 2 =

10 Bandwidth Extension Common Source stage has high gain, but low bandwidth Note that Miller effect is the culprit Follower stage can buffer source resistance from Miller cap

11 Bandwidth Extension Using Source Follower (SF) COMMON SOURCE COMMON DRAIN COMMON SOURCE v in g m1 v in v v int g out m2 v int

12 CS Example with Cap Load C in and C S are very large, therefore they look like short circuits to the AC signal. If C L is very large, its pole dominates, let s analyze

13 CS with Cap Load Small Signal R d R 2 //R g1 //R g2 ~R 2 What are the time constants associated with the capacitors in this circuit? What can we do if we have to drive a large C L?

14 CS with Cap Load Bandwidth How can we reduce the impact of C L? One way is to reduce the resistance R d, but this reduces our low-frequency gain To recover the gain we can increase g m1. What does this cost us?

15 CS with Cap Load BW Extension A better way to extend the bandwidth is to add a sourcefollower stage. Similar to previous example

16 CS with Cap Load BW Extension 1/g m2 v in g m1 v in v int v int By adding a CD (Source Follower) we can increase the bandwidth It costs us power for the CD stage Remember that increasing the BW by increasing g m1 costs us much more

17 CS + CG Common source provides gain, CG acts as a buffer, but is it even helping? How do you bias this circuit?

18 Merged CS + CG = Cascode Let s apply 2-port small-signal analysis v out v int In this case, we care about the input current to the second stage Note that the input resistance of the CG is low, therefore the majority of the CS current is fed to the CG A v =

19 Cascode Bandwidth Draw in the C gs and C gd capacitors. Which ones are Miller effected? Is this better or worse than a CS without a CG?

20 Cascode Bandwidth Draw in the capacitors and input resistance v out v int

21 Cascode Biasing l l l CG has a very large output resistance Loading it with R D is likely to reduce the voltage gain We can increase the gain by using a current source load, but r oc needs to be very large. Can use a cascode current mirror!

22 Complete Amplifier Design Goals: g m1 = 1 ms, R out =5 MW For simplicity, let s assume all g m and r o values are equal A V g m1 R out = 1mS * 5MΩ = 5, 000 R out 1 2 g mr o 2 = 5MΩ r o = 20MΩ = 10MΩ g m 1mS =100kΩ

23 Bias Current & Device Sizing Need to know process parameters to solve for W/L k = 100 μa/v 2 λ = 0.1 [V -1 ] r o = 1 =100kΩ λi DS I DS = g m = W L = 1.1V 1 *100kΩ =100µA 2k ' W L g 2 m = 2k 'I DS I DS =1mS (1mS) 2 2 *100µ *100µA = 50

24 Output (Voltage) Swing Need to know V GS V T (e.g. V DSAT, V OV ) g m = 2I DS V GS V T =1mS V GS V T = 2I DS g m = 2 *100µA 1mS = 0.2V Maximum V OUT = Minimum V OUT = Input Bias V IN =