2.5 V, k' n. W/L = 3 maa^2, V tn. and V as. = 0, find v s. = +1 V. (d) Repeat (b) for v c u. = -1 V. (e) What is the highest value of v CM

Size: px
Start display at page:

Download "2.5 V, k' n. W/L = 3 maa^2, V tn. and V as. = 0, find v s. = +1 V. (d) Repeat (b) for v c u. = -1 V. (e) What is the highest value of v CM"

Transcription

1 774 CHAPTER 7 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS PROBLEMS 775 S With the two input terminals connected to a suitable dc voltage V cu, the bias current 7 of a perfectly symmetrical differential pair divides equally between the two transistors of the pair, resulting in a zero voltage difference between the two drains (collectors) To steer the current completely to one side of the pair, a difference input voltage v id of at least J2V 0V (4V T for bipolar) is needed 9 Superimposing a differential input signal v id on the dc common-mode input voltage V CM such that v n V CM + v id /2 v I2 V cu -v id /2 causes a virtual signal ground to appear on the common source (emitter) connection In response to v jd, the current in Q x increases by g ln v id /2 the current in Q 2 decreases by g m v id /2 Thus, voltage signals of ±g M (R D II r 0 )v id /2 develop at the two drains (collectors, with R D replaced by R c ) If the output voltage is taken single-endedly, that is, between one of the drains (collectors) ground, a differential gain of \g (R D [I r 0 ) is realized Taking the output differentially, that is, between the two drains (collectors) the differential gain realized is twice as large: S g m( R D I r 0) The analysis of a differential amplifier to determine differential gain, differential input resistance, frequency response of differential gain, so on is facilitated by employing the differential half-circuit, which is a common-source (common-emitter) transistor biased at 1/2 An input common-mode signal v icm gives rise to drain (collector) voltage signals that are ideally equal given by -v icm (R D /2R ss ) [-v lcm (R c /2R EE ) for the bipolar pair], where R ss (R EE ) is die output resistance of the current source that supplies the bias current / When the output is taken single-endedly a common-mode gain of magnitude \A cm\ RD/ 2R SS ( R C/2R EE for the bipolar case) results Taking the output differentially results in the perfectly matched case in zero A cm (infinite CMRR) Mismatches between the two sides of the pair make A cm finite even when the output is taken differentially: A mismatch AR D causes A cm (R D /2R SS )(AR D /R D ); a mismatch Ag, causes \A cm \ (R D /2R ss )(Ag m /gj Corresponding expressions apply for the bipolar pah' While the input differential resistance R M of the MOS pair is infinite, that for the bipolar pair is only 2r n but can be increased to 2(f5 + l)(r e + R e ) by including resistances R e in the two emitters The latter action, however, lowers A j Mismatches between the two sides of a differential pair result in a differential dc output voltage V 0 even when the two input terminals are tied together connected to a dc voltage V CM This signifies the presence of an input offset voltage V os V 0 /A d In a MOS pair there are three main sources for V os : AR r A(W/L) Vgv D 2 R n VÇY_ A(W/L) > V os -SZ- 2 W/L For the bipolar pair there are two main sources: AR C ARr > Vn VT Rc A/, A popular circuit in both MOS bipolar analog ICs is the current-mirror-loaded differential pair It realizes a high differential gain t 8m( R o \R N, r ) a low common-mode gain, A cm \i for the MOS circuit (r o 4 /B 3 R E E for the bipolar circuit), as well as performing the differential-to-single-ended conversion with no loss of gain The common-mode gain of the differential amplifier exhibits a transmission zero caused by the finite output resistance capacitance of the bias current source; fz T C ss R ss (t^eeree for bipolar) Thus the CMRR has a pole at this relatively low frequency A multistage amplifier usually consists of three stages: an input stage having a high input resistance, a reasonably high gain,, if differential, a high CMRR; an intermediate stage that realizes the bulk of the gain; an output stage having a low output resistance Many CMOS amplifiers serve to drive only small on-chip capacitive loads hence do not need an output stage In designing analyzing a multistage amplifier; the loading effect of each stage on the one that precedes it must be taken into account AI S P R O B L E M S SECTION 71: THE MOS DIFFERENTIAL PAIR 71 For an NMOS differential pair with a common-mode voltage v CM applied, as shown in Fig 72, let V DD V ss 25 V, k' n W/L 3 maa^2, V tn 07 V, 7 02 ma, R D 5 k 2 neglect channel-length modulation (a) Find V ov V as for each transistor (b) For v CM 0, find v s, i Dl, i D2, v Dl, v D2 (c) Repeat (b) for v c u +1 V (d) Repeat (b) for v c u -1 V (e) What is the highest value of v CM for which Q x remain in saturation? (f) If current source I requires a minimum voltage of 03 V to operate properly, what is the lowest value allowed for v s hence for v CM 7 72 For the PMOS differential amplifier shown in Fig P72 let V tp -08 V k' p W/L 35 maa^2 Neglect channellength modulation (a) For v Gl V G2 0 V, find V ov V GS for each of <2i Q 2 Also find v s, v m, v D2 (b) If the current source requires a minimum voltage of 05 V, find the input common-mode range %i 1 v m o- 2kO FIGURE P72 Qi +25 V 0-25 V 07 ma "2kn -0%2 73 For the differential amplifier specified in Problem 71 let v G2 0 v G1 v id Find the value of v ld that corresponds to each of the following situations: (a) i m i D2 01 ma; (b) i m 015 ma i D2 005 ma; (c) im 02 ma i D2 0 (Q 2 just cuts off); (d) i Dl 005 ma i D2 015 ma; (e) i m 0 ma (Q_ just cuts off) i D2 02 ma For each case, find v s, v m, v D2, (v D2 - v m ) 74 For the differential amplifier specified in Problem 72, let v G2 0 v Gl v id Find the range of v id needed to steer the bias current from one side of the pair to the other At each end of this range, give the value of the voltage at the common-source terminal the drain voltages 75 Consider the differential amplifier specified in Problem 71 with G 2 grounded v G1 v id Let v id be adjusted to the value that causes i m 011 ma i D2 009 ma Find the corresponding values of v GS2, v s, v GSl, hence v id What is the difference output voltage v D2 - v m l What is the voltage gain (v D2 - v Dl )/v id l What value of v id results in i m 009 ma i D2 011 ma? 76 The table providing the answers to Exercise 73 shows that as the maximum input signal to be applied to the differential pair is increased, linearity is maintained at the same level by operating at a higher V ov If v jd max is to be 150 mv, use the data in the table to determine the required V ov the corresponding values of W/L g m 77 Use Eq (723) to show that if the term involving v\ d is to be kept to a maximum value of k then the maximum possible fractional change in the transistor current is given by fa!,, \ 1/2 2jk(l-k) the corresponding maximum value of v id is given by ^Wmax 2jkV ov Evaluate both expressions for k 001, 01, An NMOS differential amplifier utilizes a bias current of 200 LiA The devices have V, 08 V,W 100 Ltm, L 16 jtan, in a technology for which /U n 90 tia/v 2 Find V G s, gm^ the value of v u for full-current switching To what value should the bias current be changed in order to double the value of v id for full-current switching? D79 Design the MOS differential amplifier of Fig 75 to operate at V ov 02 V to provide a transconductance g m of 1 ma/v Specify the W/L ratios the bias current The technology available provides V, 08 V fi n 90 jiain Consider the NMOS differential pair illustrated in Fig 75 under the conditions that jia, using FETs for which k' n (W/L) 400 ^A'V 2, V, 1 V What is the voltage on the common-source connection for v Gl v G2 0? 2 V? What is the relation between the drain currents in each

2 776 CHAPTER 7 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS PROBLEMS, of these situations? Now for v G2 0 V, at what voltages must v al be placed to reduce i D2 by 10%? to increase i D2 by 10%? What is the differential voltage, v u v G2 - v cl, for which the ratio of drain currents i D2 A m is 10? 05? 09? 099? For the current ratio i Dl /i D 200, what differential input is required? SECTION 72: SMALL-SIGNAL OPERATION OF THE M0S DIFFERENTIAL PAIR 711 An NMOS differential amplifier is operated at a bias current I of 05 ma has a W/L ratio of 50, Ei n 250 HAN, V A 10 V, R D 4 kq Find V ov, g m, r 0 A rf D712 It is required to design an NMOS differential amplifier to operate with a differential input voltage that can be as high as 02 V while keeping the nonlinear term under the square root in Eq (723) to a maximum of 01 A transconductance g m of 3 ma/v is needed Find the required values of V ov, I, W/L Assume that the technology available has p,,c BX 100 paiv 1 What differential gain A d results when R D 5 kq? Assume X 0 What is the resulting output signal corresponding to v id at its maximum value? 0*713 Figure P713 shows a circuit for a differential amplifier with an active load Here Q x form the differential pair while the current source transistors Q A Q 5 form the active loads for <2i, respectively The dc +25 V bias circuit that establishes an appropriate dc voltage at the drains of CJi is not shown Note that the equivalent differential half-circuit is an active-loaded common-source transistor of the type studied in Section 65 It is required to design the circuit to meet the following specifications: (a) Differential gain A d 80 V/V (b) 7^ fia (c) The dc voltage at the gates of Q 6 Q 3 is +15 V (d) The dc voltage at the gates of Q 7, Q 4, Q 5 is -15 V The technology available is specified as follows: )i n C ox 3N p 90 M/V 2 ; V tn \V tp \ 07 V, V An V Ap 20 V Specify the required value of R the W/L ratios for all transistors Also specify I D V GS \at which each transistor is operating For dc bias calculations you may neglect channellength modulation 714 A design error has resulted in a gross mismatch in the circuit of Fig P714 Specifically, Q 2 has twice the W/L ratio of Q y If v ld is a small sine-wave signal, find: (a) I m I D2 (b) V ov for each of GJi (c) The differential gain A d in terms of R D, I, V ov (a) If the output is taken single-endedly, find \A d \, \A cm \, CMRR (b) If the output is taken differentially there is a 1% mismatch between the drain resistances, find \A d \, \A cm \, CMRR 71 S For the differential amplifier shown in Fig P72, let ft have k' p (WIL) 35 ma/v 2, assume that the bias current source has an output resistance of 30 kq Find V ov, g m, \A d \, \A cm \, the CMRR (in db) obtained with the output taken differentially The drain resistances are known to have a mismatch of 2% 12*7 J 7 The differential amplifier in Fig P717 utilizes a resistor R ss to establish a 1-mA dc bias current Note that this amplifier uses a single 5-V supply thus needs a dc common-mode voltage V CM Transistors Q x have k' W/L 25 ma/v 2, V t 07 V, 10 (a) Find the required value of V CM (b) Find the value of R D that results in a differential gain A d of 8 V/V (c) Determine the dc voltage at the drains (d) Determine the common-mode gain AV D1 /AV CM (Hint: You need to take l/g m into account) (e) Use the common-mode gain found in (d) to determine the change in V CM that results in Cj\ entering the triode region A V DD 5 V A Rm RD- (AR D /2) Also let g ml g m + (Ag m /2) g m2 8m ~ (Ag m /2) Follow an analysis process similar to that used to derive Eq (764) to show that y 2R ss/y 8 m R D ) Note that this equation indicates that R D can be deliberately varied to compensate for the initial variability in g m R D, that is, to minimize A cm (b) In a MOS differential amplifier for which R D 5 kq R ss 25 kq, the common-mode gain is measured found to be 0002 V/V Find the percentage change required in one of the two drain resistors so as to reduce A an to zero (or close to zero) 71 Recalling that g m of a MOSFET is given by 8 m k' n {^(V GS -V,) we observe that there are two potential sources for a mismatch between the g m values in a differential pair: a mismatch A(W/L) in the (W/L) values a mismatch AV, in the threshold voltage values Hence show that Ag m A(W/L) AV, 8 m W/L V 0 v Evaluate the worst-case fractional mismatch in g m for a differential pair in which the (W/L) values have a tolerance of+1% the largest mismatch in V t is specified to be 5 mv Assume that the pair is operating at V ov 025 V If R D 5 kq R ss 25 kq, find the worst-case value of A cm If the bias current 11 ma, find the corresponding worst-case CMRR A Ö3 SECTION 73: THE BJT DIFFERENTIAL PAIR 72 For the differential amplifier of Fig 713(a) let I 1 ma, V cc 5 V, vat -2 V, R c 3 kq, Q 100 Assume that the BJTs have v BE 07 V at i c 1 ma Find the voltage at the emitters at the outputs vj2 o 1 Qi Qi -FJ For the circuit of Fig 713(b) with an input of+1 V as indicated, with 71 ma, V cc 5V,R C 3 kq, B 100, find the voltage at the emitters the collector voltages Assume that the BJTs have v BE 07 V at i c 1 ma 722 Repeat Exercise 77 (pagex) for an input of -03 V 05 FIGURE P For the BJT differential amplifier of Fig 712 find the value of the input differential signal, v u v Bl - v B2, that causes i El 0807 FIGURE P V FIGURE P An NMOS differential pair is biased by a current source / 02 ma having an output resistance R ss 100 kq The amplifier has drain resistances R D 10 kq, using transistors with k' n W/L 3 ma/v 2, r 0 that is large *718 The objective of this problem is to determine the common-mode gain hence the CMRR of the differential pair arising from a simultaneous mismatch in g m in R D (a) Refer to the circuit in Fig 711 let the two drain resistors be denoted R m R D2 where R Dl R D + (AR D /2) B724 Consider the differential amplifier of Fig 712 let the B JT P be very large: (a) What is the largest input common-mode signal that can be applied while the BJTs remain comfortably in the active region with v CB 0?

3 778 CHAPTER 7 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS PROBLEMS 779 (b) If an input difference signal is applied that is large enough to steer the current entirely to one side of the pair, what is the change in voltage at each collector (from the condition for which v id 0)? (c) If the available power supply V cc is 5 V, what value of IR C should you choose in order to allow a common-mode input signal of+3 V? (d) For the value of IR C found in (c), select values for I R c Use the largest possible value for I subject to the constraint that the base current of each transistor (when I divides equally) should not exceed 2 /ia Let To provide insight into the possibility of nonlinear distortion resulting from large differential input signals applied to the differential amplifier of Fig 712, evaluate the normalized change in the current i El, Ai El /I (i El - (1/2))//, for differential input signals v u of 5, 10, 20, 30, 40 mv Provide a tabulation of the ratio ((Ai El /I)/v id ), which represents the proportional transconductance gain of the differential pair, versus v ld Comment on the linearity of the differential pair as an amplifier 0726 Design the circuit of Fig 712 to provide a differential output voltage (ie, one taken between the two collectors) of 1 V when the-differential input signal is 10 mv A current source of 2 ma a positive supply of +10 V are available What is the largest possible input common-mode voltage for which operation is as required? Assume a 1 D*727 One of the trade-offs available in the design of the basic differential amplifier circuit of Fig 712 is between the value of the voltage gain the range of commonmode input voltage The purpose of this problem is to demonstrate this trade-off (a) Use Eqs (772) (773) to obtain i ci i a corresponding to a differential input signal of 5 mv (ie, v m -v B2 5 mv) Assume 0 to be very high Find the resulting voltage difference between the two collectors (v^ - v cl ), divide this value by 5 mv to obtain the voltage gain in terms of (IR C )- (b) Find the maximum permitted value for v c u (Fig 713a) while the transistors remain comfortably in the active mode with v CB 0 Express this maximum in terms of V cc the gain, hence show that for a given value of V cc, the higher the gain achieved, the lower the common-mode range Use this expression to find % M m a x corresponding to a gain magnitude of 100, 200, 300, 400 WV For each value, also give the required value of IR C the value of R c for I 1 ma * 72 8 For the circuit in Fig 712, assuming a 1 IR C 5 V, use Eqs (767) (768) to find i cl i c2, hence determine v v C2 - v cl for input differential signals v id v m - v B2 of 5 mv, 10 mv, 15 mv, 20 mv, 25 mv, 30 mv, 35 mv, 40 mv Plot v versus v id, hence comment on the amplifier linearity As another way of visualizing linearity, determine the gain (v 0 /v id ) versus v id Comment on the resulting graph 729 In a differential amplifier using a 6-mA emitter bias current source the two BJTs are not matched Rather, one has one--a-half times the emitter junction area of the other For a differential input signal of zero volts, what do the collector currents become? What difference input is needed to equalize the collector currents? Assume a\ *730 Figure P730 shows a logic inverter based on the differential pair Here, Q x form the differential pair, whereas 6J 3 is an emitter follower that performs two functions: It shifts the level of the output voltage to make V 0H V 0L centered on the reference voltage V R, thus enabling one gate to drive another (this point will be explained in detail in Chapter 11), it provides the inverter with a low output resistance All transistors have V BE 07 V at I c 1 ma have (a) For v l sufficiently low that Q x is cut off, find the value of the output voltage v 0 This is V 0H _ (b) For v, sufficiently high that Q x is carrying all the current /, find the output voltage v 0 This is V 0L (c) Determine the value of v, that results in Q x conducting 1% of / This can be taken as V 1L (d) Determine the value of v, that results in Q x conducting 99% of I This can be taken as V IH (e) Sketch clearly label the breakpoints of the inverter voltage transfer characteristic Calculate the values of the noise margins NM H NM L Note the judicious choice of the value of the reference voltage V R (For the definitions of the parameters that are used to characterize the inverter VTC, refer to Section 17) V 0O- 0 FIGURE P730 V rr lkfu 5 V : l m v,o [öi Q 2 \ <3V Ä 364V 110 ma \jl 1 ma 731 A BJT differential amplifier uses a 300-tiA bias current What is the value of g m of each device? If 0 is 150, what is the differential input resistance? D732 Design the basic BJT differential amplifier circuit of Fig 716 to provide a differential input resistance of at least 10 kq a differential voltage gain (with the output taken between the two collectors) of 200 V/V The transistor B is specified to be at least 100 The available power supply is 10 V 733 For a differential amplifier to which a total difference signal of 10 mv is applied, what is the equivalent signal to its corresponding CE half-circuit? If the emitter current source is 100 t(a, what is r c of the half-circuit? For a load resistance of 10 kq in each collector, what is the half-circuit gain? What magnitude of signal output voltage would you expect at each collector? 7" 34 A BJT differential amplifier is biased from a 2-mA constant-current source includes a 100-Q resistor in each emitter The collectors are connected to V cc via 5-kQ resistors A differential input signal of 01 V is applied between the two bases (a) Find the signal current in the emitters (i e ) the signal voltage v be for each BJT (b) What is the total emitter current in each BJT? (c) What is the signal voltage at each collector? Assume a 1 (d) What is the voltage gain realized when the output is taken between the two collectors? S 73 5 Design a BJT differential amplifier to amplify a differential input signal of 02 V provide a differential output signal of 4 V To ensure adequate linearity, it is required to limit the signal amplitude across each base-emitter junction to a maximum of 5 mv Another design requirement is that the differential input resistance be at least 80 kq The BJTs available are specified to have 0 > 200 Give the circuit configuration specify the values of all its components 736 A particular differential amplifier operates from an emitter current source whose output resistance is 1 MQ What resistance is associated with each common-mode half-circuit? For collector resistors of 20 kq, what is the resulting common-mode gain for output taken (a) differentially, (b) single-endedly? 737 Find the voltage gain the input resistance of the amplifier shown in Fig P737 assuming P 100 FIGURE P737 t 738 Find the voltage gain input resistance of the amplifier in Fig P738 assuming that FIGURE P V i 739 Derive an expression for the small-signal voltage gain v 0 /vi of the circuit shown in Fig P739 in two different ways: (a) as a differential amplifier (b) as a cascade of a common-collector stage Q t a common-base stage Q 2 Assume that the BJTs are matched have a current gain a Verify that both approaches lead to the same result FIGURE P739 Vcc 740 The differential amplifier circuit of Fig P740 utilizes a resistor connected to the negative power supply to establish the bias current I (a) For v Bl v id /2 v B2 -v id /2, where v ld is a small signal with zero average, find the magnitude of the differential gain, \v 0 /v id \ (b) For v m v m v icm, find the magnitude of the commonmode gain, \v 0 /v icm \ (c) Calculate the CMRR

4 780 CHAPTER 7 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS <7 V PROBLEMS I 781 FIGURE P V -5 V (d) If v B1 01 sin 2K x 60f sin 2K X loooi volts, v m 01 sin 2K x 60f sin 2K X looof, volts, find v For the differential amplifier shown in Fig P741, identify sketch the differential half-circuit the Commonmode half-circuit Find the differential gain, the differential input resistance, the common-mode gain, the common-mode input resistance For these transistors, B - FIGURE P V 742 Consider the basic differential circuit in which the transistors have B 200 V A 200 V, with I 05 ma, R EE 1 MQ, R c 20 kq Find: (a) the differential gain to a single-ended output (b) the differential gain to a differential output ' (c) the differential input resistance (d) the common-mode gain to a single-ended output (e) the common-mode gain to a differential output 743 In a differential-amplifier circuit resembling that shown in Fig 723(a), the current generator represented by / R EE consists of a simple common-emitter transistor operating at 100 jua For tills transistor, those used in the differential pair, V A 200 V B 50 What common-mode input resistance would apply? 0744 It is required to design a differential amplifier to provide the largest possible signal to a pair of 10-kQ load resistances The input differential signal is a sinusoid of 5-mV peak amplitude which is applied to one input terminal while the other input terminal is grounded The power supply available is 10 V To determine the bias current required, 7, derive an expression for the total voltage at each of the collectors in terms of V cc I in the presence of the input signal Then impose the condition that both transistors should remain well out of saturation with a minimum v CB of approximately 0 V Thus determine the required value of 7 For this design, what differential gain is achieved? What is the amplitude of the signal voltage obtained between the two collectors? Assume a l P*745 Design a BJT differential amplifier that provides two single-ended outputs (at the collectors) The amplifier is to have a differential gain (to each of the two outputs) of at least 100 V/V, a differential input resistance >10 kq, a common-mode gain (to each of the two outputs) no greater than 01 V/V Use a 2-mA current source for biasing Give the complete circuit with component values suitable power supplies that allow for +2 V swing at each collector Specify the minimum value that the output resistance of the bias current source must have The BJTs available have 5 > 100 What is the value of the input common-mode resistance when the bias source has the lowest acceptable / resistance? 746 When the output of a BIT differential amplifier is taken differentially, its CMRR is found to be 40 db higher than when the output is taken single-endedly If the only source of common-mode gain when the output is taken differentially is the mismatch in collector resistances, what must this mismatch be (in percent)? * 7 o 4 7 In a particular BJT differential amplifier, a production error results in one of the transistors having an emitter-base junction area that is twice that of the other With the inputs grounded, how will the emitter bias current split between the two transistors? If the output resistance of the current source is 1 MQ the resistance in each collector (R c ) is 12 kfi, find the common-mode gain obtained when the output is taken differentially Assume a I SECTION 74: OTHER N0NIDEAL CHARACTERISTICS OF THE DIFFERENTIAL AMPLIFIER D748 An NMOS differential pair is to be used in an amplifier whose drain resistors are 10 kq ± 1% For the pair, k' w/l 4 ma/v 2 A decision is to be made concerning the bias current / to be used, whether 200 /xa or 400 pa For differential output, contrast the differential gain input offset voltage for the two possibilities D749 An NMOS amplifier, whose designed operating point is at V ov 03 V, is suspected to have a variability of V, of ±5 mv, of W/L R D (independently) of ±2% What is the worst-case input offset voltage you would expect to find? What is the major contribution to this total offset? If you used a variation of one of the drain resistors to reduce the output offset to zero thereby compensate for the uncertainties (including that of the other R D ), what percentage change from nominal would you require? If by selection you reduced the contribution of the worst cause of offset by a factor of 10, what change in R D would be needed? 75 An NMOS differential pair operating at a bias current I of 100 /ua uses transistors for which k' 100 jialy 2 W/L 20, with V, 08 V Find the three components of input offset voltage under the conditions that AR D /R D 5%, A(W/L)/(W/L) 5%, A V, 5 mv In the worst case, what might the total offset be? For the usual case of the three effects being independent, what is the offset likely to be? (Hint: For the latter situation, use a root-sum-of-squares computation) 751 A differential amplifier using a 600-^iA emitter bias source uses two well-matched transistors but collector load resistors that are mismatched by 10% What input offset voltage is required to reduce the differential output voltage to zero? 752 A differential amplifier using a 600-/M emitter bias source uses two transistors whose scale currents I s differ by 10% If the two collector resistors are well matched, find the resulting input offset voltage 753 Modify Eq (7125) for the case of a differential amplifier having a resistance R E connected in; the emitter of each transistor Let the bias current source be A differential amplifier uses two transistors whose B values are B x B 2 If everything else is matched, show that the input offset voltage is approximately V T [ (1 / B x ) - (1 /B 2 )] Evaluate V os for B_ 100 B Assume the differential source resistance to be zero * 75 5 A differential amplifier uses two transistors having V A values of 100 V 300 V If everything else is matched, find the resulting input offset voltage Assume that the two transistors are intended to be biased at a V CE of about 10 V * 75 6 A differential amplifier is fed in a balanced or pushpull manner with the source resistance in series with each base being R s Show that a mismatch AR S between the values of the two source resistances gives rise to an input offset voltage of approximately (I/2fi)AR s 757 One approach to "offset correction" involves the adjustment of the values of R cl R C2 so as to reduce the differential output voltage to zero when both input terminals are grounded This offset-nulling process can be accomplished by utilizing a potentiometer in the collector circuit, as shown in Fig VI51 We wish to find the potentiometer setting, represented by the fraction x of its value connected in series with R cl, that is required for nulling the output offset voltage that results from: (a) R cl being 5% higher than nominal i? C2 5% lower than nominal (b) <2i having an area 10% larger than that of Q 2 FIGURE P A differential amplifier for which the total emitter bias current is 600 LIA uses transistors for which ß is specified to lie between What is the largest possible input bias current? The smallest possible input bias current? The largest possible input offset current? *759 A BJT differential amplifier, operating at a bias current of 500 fia, employs collector resistors of 27 kq (each) connected to a +15-V supply The emitter current source employs a BJT whose emitter voltage is -5 V What are the

5 782 ' 'J CHAPTER 7 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS PROBLEMS positive negative limits of the input common-mode range of the amplifier for differential signals of <20-mV peak amplitude, applied in a balanced or push-pull fashion? **760 In a particular BJT differential amplifier, a production error results in one of the transistors having an emitterbase junction area twice that of the other With both inputs grounded, find the current in each of the two transistors hence the dc offset voltage at the output, assuming that the collector resistances are equal Use small-signal analysis to find the input voltage that would restore current balance to the differential pair Repeat using large-signal analysis compare results Also find the input bias offset currents assuming I 01 ma P\ P D761 A large fraction of mass-produced differentialamplifier modules employing 20-kQ collector resistors is found to have an input offset voltage ranging from +3 mv to -3 mv If the gain of the input differential stage is 90 V/V, by what amount must one collector resistor be adjusted to reduce the input offset to zero? If an adjustment mechanism is devised that raises one collector resistor while correspondingly lowering the other, what resistance change is needed? Suggest a suitable circuit using the existing collector resistors a potentiometer whose moving element is connected to V cc What value of potentiometer resistance (specified to 1 significant digit) is appropriate? SECTION 75: WITH ACTIVE LOAD THE DIFFERENTIAL AMPLIFIER D 76 2 In an active-loaded differential amplifier of the form shown in Fig 728(a), all transistors are characterized by k'w/l 32 ma/v z, V A 20 V Find the bias current I for which the gain v a /v u 80 V/V 763 In a version of the active-loaded MOS differential amplifier shown in Fig 728(a), all transistors have k'w/l 02 ma/v 2 V A 20 V For V DD 5 V, with the inputs near ground, (a) I 100 pa or (b) I400 pa, calculate the linear range of v, the g m of Q x, the output resistances of Q 2 Q 4, the total output resistance, the voltage gain 764 Consider the active-loaded MOS differential amplifier of Fig 728(a) in two cases: (a) Current-source I is implemented with a simple current mirror -(b) Current-source I is implemented with the modified Wilson current MINOR shown in Fig P764 Recalling that for the simple mirror R ss r o\ Q for the Wilson mirror R ss g m7 r o7 r o5, assuming that all transistors have the same V A k'w/l, show that for case (a) CMRR 2[ A X 2 08 FIGURE P764 for case (b) CMRR I T 07 where V ov is the overdrive voltage that corresponds to a drain current of 7/2 For k'w/l 10 ma/v 2, / 1 ma, 10 V, find CMRR for both cases D*765 Consider an active-loaded differential amplifier such as that shown in Fig 728(a) with the bias current source implemented with the modified Wilson mirror of Fig P764 with pa The transistors have V, 07 V k'iw/l) 800 pan 2 What is the lowest value of the total power supply (V DD + V ss ) that allows each transistor to operate with V n \V GS\? *766 (a) Sketch the circuit of an active-loaded MOS differential amplifier in which the input transistors are cascoded, a cascode current mirror is used for the load, (b) Show that if all transistors are operated at an overdrive voltage V ov have equal Early voltages V A, the gain is given by JÎ A d 2(V A/V 0 V) 2 Evaluate the gain for V o v 025 V V A 20 V 767 The differential amplifier in Fig 732(a) is operated with pa, with devices for which V A 160 V d 100 What differential input resistance, output resistance, equivalent transconductance, open-circuit voltage gain would you expect? What will the voltage gain be if the input resistance of the subsequent stage is 100 kq? 0*768 Design the circuit of Fig 732(a) using a basic current mirror to implement the current source I It is required that the equivalent transconductance be 5 ma/v Use ±5-V power supplies BJTs that have P 150 V A 100 V Give the complete circuit with component values specify the differential input resistance R id, the output resistance R 0, the open-circuit voltage gain A d, the input bias current, the input common-mode range, the common-mode input resistance D*769 Repeat the design of the amplifier specified in Problem 768 utilizing a Widlar current source [Fig 662] to supply the bias current Assume that the largest resistance available is 2 kq D770 Modify the design of the amplifier in Problem 768 by connecting emitter-degeneration resistances of values that result in R id 100 kq What does A d become? 771 An active-loaded bipolar differential amplifier such as that shown in Fig 732(a) has I 05 ma, V A 120 V, P 150 Find G m, R 0, A d, R id If the bias-current source is implemented with a simple npn current mirror, find R EE, A cm, CMRR If the amplifier is fed differentially with a source having a total of 10 kq resistance (ie, 5 kq in series with the base lead of each of O x ), find the overall differential voltage gain * 77 2 Consider the differential amplifier circuit of Fig 732(a) with the two input terminals tied together an input common-mode signal v wm applied Let the output resistance of the bias current source be denoted by R EE, let the P of the pnp transistors be denoted B p Assuming that P of the npn transistors is high, use the current transfer ratio of the mirror to show that there will be an output current of v icm /PpR EB Thus, show that the common-mode transconductance is 1 /ppr EE Use this result together with the differential transconductance G m (derived in the text) to find an alternative measure of the common-mode rejection, unserve that this result differs from the CMRR expression in Eq (7174) by a factor of 2, which is simply the ratio of the output resistance for common-mode inputs (r o4 ) the output resistance for differential inputs (r o2 // r o4 ) *773 Repeat Problem 772 for the case in which the current mirror is replaced with a Wilson mirror Show that in this case the output current will be v ICM /P 2 pr EE Find the common-mode transconductance theratio G mcm /G m 774 Figure P774 shows a differential cascode amplifier with an active load formed by a Wilson current mirror Utilizing the expressions derived in Chapter 6 for the output resistance of a bipolar cascode the output resistance of the Wilson mirror, assuming all transistors to be identical, show that the differential voltage gain A d is given by A d 3ßgm r o Evaluate A d for the case I 04 ma, P 100, V A 120 V d 5 FIGURE P774 Vrr +5 (3 > V7 ~V EE -5V Ü2 r -o v 0 D775 Consider the bias design of the Wilson-loaded cascode differential amplifier shown in Fig P774 (a) What is the largest signal voltage possible at the output without Q 7 saturating? Assume that the CB junction conducts when the voltage across it exceeds 04 V (b) What should the dc bias voltage established at the output (by an arrangement not shown) be in order to allow for positive output signal swing of 15 V? (c) What should the value of V BIAS be in order to allow for a negative output signal swing of 15 V? (d) What is the upper limit on the input common-mode voltage v ct p *776 Figure P776 shows a modified cascode differential amplifier Here 3 Q 4 are the cascode transistors However, the manner in which Q 3 is connected with its base current feeding the current mirror Q-,-Q s results in very interesting input properties Note that for simplicity the circuit is shown with the base of Q 2 grounded

6 784 CHAPTER 7 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS PROBLEMS y j SECTION 76: DIFFERENTIAL AMPLIFIER FREQUENCY RESPONSE OF THE 7,8 A MOSFET differential amplifier such as that shown in Fig 736(a) is biased with a current source I 200 pa The transistors have W/L 25, k' 128 pa/v 2, V A 20 V, C gs 30 ff, C gd 5 ff, C ib 5 ff The drain resistors are 20 kq each Also, there is a 90-fF capacitive load between each drain ground D784 It is required to increase the 3-dB frequency of the differential amplifier specified in Problem 782 to 1 MHz by adding an emitter resistance R e Use the open-circuit timeconstants method to perform this design Specifically, use the formulas for R K given in the statement for Problem 783 to determine the required value of the factor (1 + g mr e) hence find R e Make appropriate approximations to simplify the calculations What does the dc gain become? Also determine the resulting gain-bwidth product V[ o- FIGURE P776 0 (a) With v I OV dc, find the input bias current I B assuming all transistors have equal value of B Compare the case without the Q 7 -Q a connection (b) With»j 0V (dc) + v m, find the input signal current i b hence the input differential resistance R i d Compare with the case without the Qj-Qn connection (Observe that Q 4 arranges that the emitter currents of Q_ are very nearly the same!) 777 Utilizing the expression for the current transfer ratio of the Wilson mirror derived in Section 6123 (Eq 6193) derive an expression for the systematic offset voltage of a B JT differential amplifier that utilizes apnp Wilson current mirror load Evaluate V os for B P 50 IN for p-channel MOSFETs is 10 V, V A \ for npn transistors is 120 V Find G m,r 0, A d '0 a, (a) Find V ov g m for each transistor (b) Find the differential gain A d (c) If the input signal source has a small resistance R sig thus the frequency response is determined primarily by the output pole, estimate the 3-dB frequency f H (d) If, in a different situation, the amplifier is fed symmetrically with a signal source of 40 kq resistance (ie, 20 kq in series with each gate terminal), use the open-circuit timeconstants method to estimate f H 781 The amplifier specified in Problem 780 has R s s 100 kq C ss 02 pf Find the 3-dB frequency of the CMRR 782 A BJT differential amplifier operating with a 1-mA current source uses transistors for which B 100, f T 600 MHz, C u 05 pf, r x 100 Q Each of the collector resistances is 10 kq, r a is very large The amplifier is fed in a symmetrical fashion with a source resistance of 10 kq in series with each of the two input terminals (a) Sketch the differential half-circuit its high-frequency equivalent circuit (b) Determine the low-frequency value of the overall differential gain (c) Use Miller's theorem to determine the input capacitance hence estimate the 3-dB frequency f H the gainbwidth product 783 The differential amplifier circuit specified in Problem 782 is modified by including 100-Q resistor in each of the emitters Determine the low-frequency value of the overall differential voltage gain; Also, use the method of opencircuit time-constants to obtain an estimate for/ H Toward that end, note that the resistance 7? u seen by C is given by l(ru g + r x)\\rinkl+g mr c)+r c 785 A current-mirror-loaded MOS differential amplifier is biased with a current source 7 06 ma The two NMOS transistors of the differential pair are operating at V ov 03 V, the PMOS devices of the mirror are operating at V ov 05 V The Early voltage V An \V Ap \ 9 V The total capacitance at the input node of the mirror is 01 pf that at the output node of the amplifier is 02 pf Find the dc value the frequencies of the poles zero of the differential voltage gain 786 A differential amplifier is biased by a current source having an output resistance of 1 MQ an output capacitance of 10 pf The differential gain exhibits a dominant pole at 500 khz What are the poles of the CMRR? 787 For the differential amplifier specified in Problem 782, find the dc gain / H when the circuit is modified by eliminating the collector resistor of the left-h-side transistor the input signal is fed to the base of the left-h-side transistor while the base of the other transistor in the pair is grounded Let the source resistance be 20 kq neglect r x (Hint: Refer to Fig 657) 788 Consider the circuit of Fig P788 for the case: pa V o v 025 V, R sig 200 kq, R D 50 kq, C gs C gd 1 pf Find the dc gain, the high-frequency poles, an estimate oif H 778 For the folded-cascode differential amplifier of Fig 735, find the value of V" BIAS that results in the largest possible positive output swing, while keeping Q 3, Q 4, the pnp transistors, that realize the current sources out of saturation Assume v cc VEE 5 V If the dc level at the output is 0 V, find the maximum allowable output signal swing For I 04 ma, B P 50, i% 150, V A 120 V find G m, R^, R o S, R 0, A d 779 For the BiCMOS differential amplifier in Fig P779 let V DD V SS 3V,I 04 ma, k'w/l 64 ma/v 2 ; IV J FIGURE P779 -V, 'ss where % (B+l)(R e + r e) The resistance R T seen by C is given by nr s i + r x + R e R r \\ gm K e Also determine the gain-bwidth product FIGURE P788

7 786 fcl? CHAPTER 7 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS PROBLEMS V V sig /2 ~V sig /2 FIGURE P For the circuit in Fig P789, let the bias be such that each transistor is operating at \QQ-(iA collector current Let the BJTs have B 200, f T 600 MHz, C p 02 pf, neglect r a r x Also, R sig R c 50 ki2 Find the low-frequency gain, the input differential resistance, the high-frequency poles, an estimate off H SECTION 77: MULTISTAGE AMPLIFIERS 790 Consider the circuit in Fig 740 with the device geometries (in (an) shown at the bottom of this page: Let 7REF 225 (la, \V,\ 075 V for all devices, (i n 180 fia/v-, (i p 60 (la/v 9 V for all devices, V ss 15 V Determine the width of Q 6, W, that will ensure that the op amp will not have a systematic offset voltage Then, for all devicesevaluatei D, )V 0V \, \V GS \, g m, r Provide your results in a table similar to Table 71 Also find Aj, A 2, the dc open-loop voltage gain, the input commonmode range, the output voltage range Neglect the effect of V A on the bias current 0*791 In a particular design of the CMOS op amp of Fig 740 the designer wishes to investigate the effects of increasing the W/L ratio of both Q x by a factor of 4 Assuming that all other parameters are kept unchanged, refer to Example 73 to help you answer the following questions: (a) Find the resulting change in V ov in g m of <2i (b) What change results in the voltage gain of the input stage? In the overall voltage gain? (c) What is the effect on the input offset voltages? (You might wish to refer to Section 74) (d) Iff, is to be kept unchanged, how must C c be changed? 792 Consider the amplifier of Fig 740, whose parameters are specified in Example 73 If a manufacturing error results in the W/L ratio of Q 7 being 50/08, find the current that Q 7 will now conduct Thus find the systematic offset voltage that will appear at the output (Use the results of Example 73) Assuming that the open-loop gain will remain approximately unchanged from the value found in Example 73, find the corresponding value of input offset voltage, V os 793 Consider the input stage of the CMOS op amp in Fig 740 with both inputs grounded Assume that the two sides of the input stage are perfectly matched except that the threshold voltages of Q 3 Q A have a mismatch AV t Show Transistor Q Q 2 Q 3 Q 4 Q s Q 6 Q 7 Q 8 I W/L 30/05 30/05 10/05 10/05 60/05 W/05 60/05 60/05 j FIGURE P795 that a current g m3 AV, appears at the output of the first stage What is the corresponding input offset voltage? Evaluate this offset voltage for the circuit specified in Example 73 for AV, 2mV (Use the results of Example 73) 794 A CMOS op amp with the topology in Fig 740 has Sm\ gmi 1 ma/v, g m6 3 ma/v, the total capacitance between node D 2 ground 02 pf, the total capacitance between the output node ground 3 pf Find the value of C c that results iaf, 50 MHz verify that/, is lower than/ z / K *795 Figure P795 shows a bipolar op-amp circuit that resembles the CMOS op amp of Fig 740 Here, the input differential pair Q_-Q 2 is loaded in a current mirror formed by Q 3 6j 4 The second stage is formed by the current-sourceloaded common-emitter transistor Q 5 Unlike the CMOS circuit, here there is an output stage formed by the emitter follower Q 6 Capacitor C c is placed in the negative-feedback path of Q 5 thus is Miller-multiplied by the gain of Q 5 The resulting large capacitance forms a dominant low-frequency pole with r n5, thus providing the required uniform -20-dB/decade gain rolloff All transistors have B 100, V BE \ 07 V, r- 0 " (a) For inputs grounded output held at 0 V (by negative feedback, not shown) find the emitter currents of all transistors (b) Calculate the dc gain of the amplifier with 7^ 10 kq (c) With R L as in (b), find the value of C c to obtain a 3-dB frequency of 100 Hz What is the value off, that results? 0796 It is required to design the circuit of Fig 742 to provide a bias current I B of 225 (la with Q_ Q 9 as matched devices having W/L 60/05 Transistors Q w, Q n, Q n are to be identical must have the same g m as Q_ Q 9 Transistor Q i2 is to be four times as wide as Qi3- Let k' n 3k p 180 (la/v 2, V DD V ss 15 V Find the required value of R B What is the voltage drop across R B 7 Also specify the W/L ratios of Q l0, Q n, Q t2, Q i3 give the expected dc voltages at the gates of Q l2, Q w, g A BJT differential amplifier, biased to have r e 50 Q utilizing two 100-Q emitter resistors 5-kii loads, drives a second differential stage biased to have r e 20 Q All BJTs have /3 120 What is the voltage gain of the first stage? Also find the input resistance of the first stage, the current gain from the input of the first stage to the collectors of the second stage 798 In the multistage amplifier of Fig 743, emitter resistors are to be introduced 100 Q in the emitter lead of each of the first-stage transistors 25 Q for each of the secondstage transistors What is the effect on input resistance, the voltage gain of the first stage, the overall voltage gain? Use the bias values found in Example 74 D799 Consider the circuit of Fig 743 its output resistance Which resistor has the most effect on the output resistance? What should this resistor be changed to if the output resistance is to be reduced by a factor of 2? What will the amplifier gain become after this change? What other change can you make to restore the amplifier gain to approximately its prior value? 0*7100 (a) If, in the multistage amplifier of Fig 743, the resistor R 5 is replaced by a constant-current source 1 ma, such that the bias situation is essentially unaffected, what does the overall voltage gain of the amplifier become?

8 788 CHAPTER 7 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS PROBLEMS I V +5 V lokfl ov 0-10V FIGURE P7101 Assume that the output resistance of the current source is very high Use the results of Example 75, (b) With the modification suggested in (a), what is the effect of the change on output resistance? What is the overall gain of the amplifier when loaded by 100 Q to ground? The original amplifier (before modification) has an output resistance of 152 Q a voltage gain of 8513 V/V What is its gain when loaded by 100 O? Comment Use j3 100 *7101 Figure P7101 shows a three-stage amplifier in which the stages are directly coupled The amplifier, however, utilizes bypass capacitors,, as such, its frequency response falls off at low frequencies For our purposes here, we shall assume that the capacitors are large enough to act as perfect short circuits at all signal frequencies of interest (a) Find the dc bias current in each of the three transistors Also find the dc voltage at the output Assume j V BE \ 07 V, P 100, neglect the Early effect (b) Find the input resistance the output resistance (c) Use the current-gain method to evaluate the voltage gain v 0 /v t (d) Find the frequency of the high-frequency pole formed at the interface between the first the second stages Assume that C^ 2 pf C %2 10 pf D***7102 For the circuit shown in Fig P7102, which uses a folded cascode involving transistor Q 3, all transistors have\v B E \ 07 Vfor the currents involved, V A 200 V, P 100 The circuit is relatively conventional except for Q 5, which operates in a Class B mode (we will study this in Chapter 14) to provide an increased negative output swing for low-resistance loads (a) Perform a bias calculation assuming Vg 07 V, high A VA, v+ v_ 0 V, v 0 is stabilized by feedback to about 0 V Find R so that the reference current I MP is 100 /JA What are the voltages at all the labeled nodes? (b) Provide in tabular form the bias currents in all transistors together with g m r a for the signal transistors (Q X, Q 2, Q 3, QA, Q S ) r 0 for Q C, Q D, Q G (c) Now, using P 100, find the voltage gain v 0 /(v+ - v_), in the process, verify the polarity of the input terminals (d) Find the input output resistances (e) Find the input common-mode range for linear operation (f) For no load, what is the range of available output voltages, assuming V C sat 03 V? (g) Now consider the situation with a load resistance connected from the output to ground At the positive negative limits of the output signal swing, find the smallest load resistance that can be driven if one or the other of Q X or Q 2 is allowed to cut off 0***71 03 In the CMOS op amp shown in Fig P7103, all MOS devices have V, 1 V, ji n C ox 2 ( o p C OT 40 pan 2, \V A \ 50 V, L 5 /an Device widths are indicated on the diagram as multiples of W, where W 5 /mi (a) Design R to provide a 10-/iA reference current (b) Assuming v 0 0 V, as established by external feedback, perform a bias analysis, finding all the labeled node voltages, V GS I D for all transistors (c) Provide in table form 7 0, V GS, g,, r 0 for all devices (d) Calculate the voltage gain v 0 /(v + - v_), the input resistance, the output resistance (e) What is the input common-mode range? (f) What is the output signal range for no load? (g) For what load resistance connected to ground is the output negative voltage limited to -1 V before Q-, begins to conduct? (h) For a load resistance one-tenth of that found in (g), what is the output signal swing? FIGURE P7102 FIGURE P V +5 V

Solid State Devices & Circuits. 18. Advanced Techniques

Solid State Devices & Circuits. 18. Advanced Techniques ECE 442 Solid State Devices & Circuits 18. Advanced Techniques Jose E. Schutt-Aine Electrical l&c Computer Engineering i University of Illinois jschutt@emlab.uiuc.edu 1 Darlington Configuration - Popular

More information

Chapter 12 Opertational Amplifier Circuits

Chapter 12 Opertational Amplifier Circuits 1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded cascode circuit.

More information

ECE 442 Solid State Devices & Circuits. 15. Differential Amplifiers

ECE 442 Solid State Devices & Circuits. 15. Differential Amplifiers ECE 442 Solid State Devices & Circuits 15. Differential Amplifiers Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 442 Jose Schutt Aine 1 Background

More information

Microelectronic Circuits II. Ch 10 : Operational-Amplifier Circuits

Microelectronic Circuits II. Ch 10 : Operational-Amplifier Circuits Microelectronic Circuits II Ch 0 : Operational-Amplifier Circuits 0. The Two-stage CMOS Op Amp 0.2 The Folded-Cascode CMOS Op Amp CNU EE 0.- Operational-Amplifier Introduction - Analog ICs : operational

More information

Chapter 8 Differential and Multistage Amplifiers

Chapter 8 Differential and Multistage Amplifiers 1 Chapter 8 Differential and Multistage Amplifiers Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: Active-Loaded Differential Pair 4.

More information

CHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS

CHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS CHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS Chapter Outline 8.1 The CMOS Differential Pair 8. Small-Signal Operations of the MOS Differential Pair 8.3 The BJT Differential Pair 8.4 Other Non-ideal

More information

Applied Electronics II

Applied Electronics II Applied Electronics II Chapter 2: Differential Amplifier School of Electrical and Computer Engineering Addis Ababa Institute of Technology Addis Ababa University Daniel D./Abel G. April 4, 2016 Chapter

More information

Building Blocks of Integrated-Circuit Amplifiers

Building Blocks of Integrated-Circuit Amplifiers Building Blocks of ntegrated-circuit Amplifiers 1 The Basic Gain Cell CS and CE Amplifiers with Current Source Loads Current-source- or active-loaded CS amplifier Rin A o R A o g r r o g r 0 m o m o Current-source-

More information

F9 Differential and Multistage Amplifiers

F9 Differential and Multistage Amplifiers Lars Ohlsson 018-10-0 F9 Differential and Multistage Amplifiers Outline MOS differential pair Common mode signal operation Differential mode signal operation Large signal operation Small signal operation

More information

Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier

Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in double-ended

More information

Improving Amplifier Voltage Gain

Improving Amplifier Voltage Gain 15.1 Multistage ac-coupled Amplifiers 1077 TABLE 15.3 Three-Stage Amplifier Summary HAND ANALYSIS SPICE RESULTS Voltage gain 998 1010 Input signal range 92.7 V Input resistance 1 M 1M Output resistance

More information

Chapter 15 Goals. ac-coupled Amplifiers Example of a Three-Stage Amplifier

Chapter 15 Goals. ac-coupled Amplifiers Example of a Three-Stage Amplifier Chapter 15 Goals ac-coupled multistage amplifiers including voltage gain, input and output resistances, and small-signal limitations. dc-coupled multistage amplifiers. Darlington configuration and cascode

More information

ECEN 474/704 Lab 6: Differential Pairs

ECEN 474/704 Lab 6: Differential Pairs ECEN 474/704 Lab 6: Differential Pairs Objective Design, simulate and layout various differential pairs used in different types of differential amplifiers such as operational transconductance amplifiers

More information

COMPARISON OF THE MOSFET AND THE BJT:

COMPARISON OF THE MOSFET AND THE BJT: COMPARISON OF THE MOSFET AND THE BJT: In this section we present a comparison of the characteristics of the two major electronic devices: the MOSFET and the BJT. To facilitate this comparison, typical

More information

Building Blocks of Integrated-Circuit Amplifiers

Building Blocks of Integrated-Circuit Amplifiers CHAPTER 7 Building Blocks of Integrated-Circuit Amplifiers Introduction 7. 493 IC Design Philosophy 7. The Basic Gain Cell 494 495 7.3 The Cascode Amplifier 506 7.4 IC Biasing Current Sources, Current

More information

ECE 546 Lecture 12 Integrated Circuits

ECE 546 Lecture 12 Integrated Circuits ECE 546 Lecture 12 Integrated Circuits Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine 1 Integrated Circuits IC Requirements

More information

The Differential Amplifier. BJT Differential Pair

The Differential Amplifier. BJT Differential Pair 1 The Differential Amplifier Asst. Prof. MONTREE SRPRUCHYANUN, D. Eng. Dept. of Teacher Training in Electrical Engineering, Faculty of Technical Education King Mongkut s nstitute of Technology North Bangkok

More information

Index. Small-Signal Models, 14 saturation current, 3, 5 Transistor Cutoff Frequency, 18 transconductance, 16, 22 transit time, 10

Index. Small-Signal Models, 14 saturation current, 3, 5 Transistor Cutoff Frequency, 18 transconductance, 16, 22 transit time, 10 Index A absolute value, 308 additional pole, 271 analog multiplier, 190 B BiCMOS,107 Bode plot, 266 base-emitter voltage, 16, 50 base-emitter voltages, 296 bias current, 111, 124, 133, 137, 166, 185 bipolar

More information

Analog Integrated Circuit Design Exercise 1

Analog Integrated Circuit Design Exercise 1 Analog Integrated Circuit Design Exercise 1 Integrated Electronic Systems Lab Prof. Dr.-Ing. Klaus Hofmann M.Sc. Katrin Hirmer, M.Sc. Sreekesh Lakshminarayanan Status: 21.10.2015 Pre-Assignments The lecture

More information

EE 140 / EE 240A ANALOG INTEGRATED CIRCUITS FALL 2015 C. Nguyen PROBLEM SET #7

EE 140 / EE 240A ANALOG INTEGRATED CIRCUITS FALL 2015 C. Nguyen PROBLEM SET #7 Issued: Friday, Oct. 16, 2015 PROBLEM SET #7 Due (at 8 a.m.): Monday, Oct. 26, 2015, in the EE 140/240A HW box near 125 Cory. 1. A design error has resulted in a mismatch in the circuit of Fig. PS7-1.

More information

Applied Electronics II

Applied Electronics II Applied Electronics II Chapter 3: Operational Amplifier Part 1- Op Amp Basics School of Electrical and Computer Engineering Addis Ababa Institute of Technology Addis Ababa University Daniel D./Getachew

More information

Unit 3: Integrated-circuit amplifiers (contd.)

Unit 3: Integrated-circuit amplifiers (contd.) Unit 3: Integrated-circuit amplifiers (contd.) COMMON-SOURCE AND COMMON-EMITTER AMPLIFIERS The Common-Source Circuit The most basic IC MOS amplifier is shown in fig.(1). The source of MOS transistor is

More information

Course Number Section. Electronics I ELEC 311 BB Examination Date Time # of pages. Final August 12, 2005 Three hours 3 Instructor

Course Number Section. Electronics I ELEC 311 BB Examination Date Time # of pages. Final August 12, 2005 Three hours 3 Instructor Course Number Section Electronics ELEC 311 BB Examination Date Time # of pages Final August 12, 2005 Three hours 3 nstructor Dr. R. Raut M aterials allowed: No Yes X (Please specify) Calculators allowed:

More information

Gechstudentszone.wordpress.com

Gechstudentszone.wordpress.com UNIT 4: Small Signal Analysis of Amplifiers 4.1 Basic FET Amplifiers In the last chapter, we described the operation of the FET, in particular the MOSFET, and analyzed and designed the dc response of circuits

More information

Course Outline. 4. Chapter 5: MOS Field Effect Transistors (MOSFET) 5. Chapter 6: Bipolar Junction Transistors (BJT)

Course Outline. 4. Chapter 5: MOS Field Effect Transistors (MOSFET) 5. Chapter 6: Bipolar Junction Transistors (BJT) Course Outline 1. Chapter 1: Signals and Amplifiers 1 2. Chapter 3: Semiconductors 3. Chapter 4: Diodes 4. Chapter 5: MOS Field Effect Transistors (MOSFET) 5. Chapter 6: Bipolar Junction Transistors (BJT)

More information

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

Radivoje Đurić, 2015, Analogna Integrisana Kola 1 OTA-output buffer 1 According to the types of loads, the driving capability of the output stages differs. For switched capacitor circuits which have high impedance capacitive loads, class A output stage

More information

LECTURE 19 DIFFERENTIAL AMPLIFIER

LECTURE 19 DIFFERENTIAL AMPLIFIER Lecture 19 Differential Amplifier (6/4/14) Page 191 LECTURE 19 DIFFERENTIAL AMPLIFIER LECTURE ORGANIZATION Outline Characterization of a differential amplifier Differential amplifier with a current mirror

More information

transistor operated at 7 C is realized? C 0X CD- FIGURE P6.9 = 0.2 V. Also, find W Fill in the table below. For the BJT, let B = 100 and V A

transistor operated at 7 C is realized? C 0X CD- FIGURE P6.9 = 0.2 V. Also, find W Fill in the table below. For the BJT, let B = 100 and V A 666 CHAPTER 6 SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS PROBLEMS, 6 6 7 ii The CG CB amplifiers act as current buffers Their impedance transformation properties are displayed in Fig 629 (CG) Fig 635 (CB)

More information

Lecture 030 ECE4430 Review III (1/9/04) Page 030-1

Lecture 030 ECE4430 Review III (1/9/04) Page 030-1 Lecture 030 ECE4430 Review III (1/9/04) Page 0301 LECTURE 030 ECE 4430 REVIEW III (READING: GHLM Chaps. 3 and 4) Objective The objective of this presentation is: 1.) Identify the prerequisite material

More information

UNIT-1 Bipolar Junction Transistors. Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press

UNIT-1 Bipolar Junction Transistors. Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press UNIT-1 Bipolar Junction Transistors Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press Figure 6.1 A simplified structure of the npn transistor. Microelectronic Circuits, Sixth

More information

Integrated Circuit: Classification:

Integrated Circuit: Classification: Integrated Circuit: It is a miniature, low cost electronic circuit consisting of active and passive components that are irreparably joined together on a single crystal chip of silicon. Classification:

More information

QUESTION BANK for Analog Electronics 4EC111 *

QUESTION BANK for Analog Electronics 4EC111 * OpenStax-CNX module: m54983 1 QUESTION BANK for Analog Electronics 4EC111 * Bijay_Kumar Sharma This work is produced by OpenStax-CNX and licensed under the Creative Commons Attribution License 4.0 Abstract

More information

Advanced Operational Amplifiers

Advanced Operational Amplifiers IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage

More information

55:041 Electronic Circuits The University of Iowa Fall Exam 3. Question 1 Unless stated otherwise, each question below is 1 point.

55:041 Electronic Circuits The University of Iowa Fall Exam 3. Question 1 Unless stated otherwise, each question below is 1 point. Exam 3 Name: Score /65 Question 1 Unless stated otherwise, each question below is 1 point. 1. An engineer designs a class-ab amplifier to deliver 2 W (sinusoidal) signal power to an resistive load. Ignoring

More information

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1 Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1 LECTURE 300 LOW VOLTAGE OP AMPS LECTURE ORGANIZATION Outline Introduction Low voltage input stages Low voltage gain stages Low voltage bias circuits

More information

BJT Amplifier. Superposition principle (linear amplifier)

BJT Amplifier. Superposition principle (linear amplifier) BJT Amplifier Two types analysis DC analysis Applied DC voltage source AC analysis Time varying signal source Superposition principle (linear amplifier) The response of a linear amplifier circuit excited

More information

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,

More information

I1 19u 5V R11 1MEG IDC Q7 Q2N3904 Q2N3904. Figure 3.1 A scaled down 741 op amp used in this lab

I1 19u 5V R11 1MEG IDC Q7 Q2N3904 Q2N3904. Figure 3.1 A scaled down 741 op amp used in this lab Lab 3: 74 Op amp Purpose: The purpose of this laboratory is to become familiar with a two stage operational amplifier (op amp). Students will analyze the circuit manually and compare the results with SPICE.

More information

Current Mirrors & Current steering Circuits:

Current Mirrors & Current steering Circuits: Current Mirrors & Current steering Circuits: MOS Current Steering Circuits: Once a constant current is generated, it can be replicated to provide DC bias currents for the various amplifier stages in the

More information

Operational Amplifiers

Operational Amplifiers Operational Amplifiers Table of contents 1. Design 1.1. The Differential Amplifier 1.2. Level Shifter 1.3. Power Amplifier 2. Characteristics 3. The Opamp without NFB 4. Linear Amplifiers 4.1. The Non-Inverting

More information

Chapter 11. Differential Amplifier Circuits

Chapter 11. Differential Amplifier Circuits Chapter 11 Differential Amplifier Circuits 11.0 ntroduction Differential amplifier or diff-amp is a multi-transistor amplifier. t is the fundamental building block of analog circuit. t is virtually formed

More information

UNIT I BIASING OF DISCRETE BJT AND MOSFET PART A

UNIT I BIASING OF DISCRETE BJT AND MOSFET PART A UNIT I BIASING OF DISCRETE BJT AND MOSFET PART A 1. Why do we choose Q point at the center of the load line? 2. Name the two techniques used in the stability of the q point.explain. 3. Give the expression

More information

Homework Assignment 07

Homework Assignment 07 Homework Assignment 07 Question 1 (Short Takes). 2 points each unless otherwise noted. 1. A single-pole op-amp has an open-loop low-frequency gain of A = 10 5 and an open loop, 3-dB frequency of 4 Hz.

More information

Lecture 240 Cascode Op Amps (3/28/10) Page 240-1

Lecture 240 Cascode Op Amps (3/28/10) Page 240-1 Lecture 240 Cascode Op Amps (3/28/10) Page 2401 LECTURE 240 CASCODE OP AMPS LECTURE ORGANIZATION Outline Lecture Organization Single Stage Cascode Op Amps Two Stage Cascode Op Amps Summary CMOS Analog

More information

Pg: 1 VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 Department of Electronics & Communication Engineering Regulation: 2013 Acadamic Year : 2015 2016 EC6304 Electronic Circuits I Question

More information

Homework Assignment 07

Homework Assignment 07 Homework Assignment 07 Question 1 (Short Takes). 2 points each unless otherwise noted. 1. A single-pole op-amp has an open-loop low-frequency gain of A = 10 5 and an open loop, 3-dB frequency of 4 Hz.

More information

EE301 Electronics I , Fall

EE301 Electronics I , Fall EE301 Electronics I 2018-2019, Fall 1. Introduction to Microelectronics (1 Week/3 Hrs.) Introduction, Historical Background, Basic Consepts 2. Rewiev of Semiconductors (1 Week/3 Hrs.) Semiconductor materials

More information

Operational Amplifiers

Operational Amplifiers CHAPTER 9 Operational Amplifiers Analog IC Analysis and Design 9- Chih-Cheng Hsieh Outline. General Consideration. One-Stage Op Amps / Two-Stage Op Amps 3. Gain Boosting 4. Common-Mode Feedback 5. Input

More information

HOME ASSIGNMENT. Figure.Q3

HOME ASSIGNMENT. Figure.Q3 HOME ASSIGNMENT 1. For the differential amplifier circuit shown below in figure.q1, let I=1 ma, V CC =5V, v CM = -2V, R C =3kΩ and β=100. Assume that the BJTs have v BE =0.7 V at i C =1 ma. Find the voltage

More information

INTRODUCTION TO ELECTRONICS EHB 222E

INTRODUCTION TO ELECTRONICS EHB 222E INTRODUCTION TO ELECTRONICS EHB 222E MOS Field Effect Transistors (MOSFETS II) MOSFETS 1/ INTRODUCTION TO ELECTRONICS 1 MOSFETS Amplifiers Cut off when v GS < V t v DS decreases starting point A, once

More information

Chapter 4. CMOS Cascode Amplifiers. 4.1 Introduction. 4.2 CMOS Cascode Amplifiers

Chapter 4. CMOS Cascode Amplifiers. 4.1 Introduction. 4.2 CMOS Cascode Amplifiers Chapter 4 CMOS Cascode Amplifiers 4.1 Introduction A single stage CMOS amplifier cannot give desired dc voltage gain, output resistance and transconductance. The voltage gain can be made to attain higher

More information

Common-Source Amplifiers

Common-Source Amplifiers Lab 2: Common-Source Amplifiers Introduction The common-source stage is the most basic amplifier stage encountered in CMOS analog circuits. Because of its very high input impedance, moderate-to-high gain,

More information

Design and Simulation of Low Voltage Operational Amplifier

Design and Simulation of Low Voltage Operational Amplifier Design and Simulation of Low Voltage Operational Amplifier Zach Nelson Department of Electrical Engineering, University of Nevada, Las Vegas 4505 S Maryland Pkwy, Las Vegas, NV 89154 United States of America

More information

Linear electronic. Lecture No. 1

Linear electronic. Lecture No. 1 1 Lecture No. 1 2 3 4 5 Lecture No. 2 6 7 8 9 10 11 Lecture No. 3 12 13 14 Lecture No. 4 Example: find Frequency response analysis for the circuit shown in figure below. Where R S =4kR B1 =8kR B2 =4k R

More information

Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem

Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem A report Submitted to Canopus Systems Inc. Zuhail Sainudeen and Navid Yazdi Arizona State University July 2001 1. Overview

More information

Chapter 4: Differential Amplifiers

Chapter 4: Differential Amplifiers Chapter 4: Differential Amplifiers 4.1 Single-Ended and Differential Operation 4.2 Basic Differential Pair 4.3 Common-Mode Response 4.4 Differential Pair with MOS Loads 4.5 Gilbert Cell Single-Ended and

More information

SAMPLE FINAL EXAMINATION FALL TERM

SAMPLE FINAL EXAMINATION FALL TERM ENGINEERING SCIENCES 154 ELECTRONIC DEVICES AND CIRCUITS SAMPLE FINAL EXAMINATION FALL TERM 2001-2002 NAME Some Possible Solutions a. Please answer all of the questions in the spaces provided. If you need

More information

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic

More information

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

Radivoje Đurić, 2015, Analogna Integrisana Kola 1 Low power OTA 1 Two-Stage, Miller Op Amp Operating in Weak Inversion Low frequency response: gm1 gm6 Av 0 g g g g A v 0 ds2 ds4 ds6 ds7 I D m, ds D nvt g g I n GB and SR: GB 1 1 n 1 2 4 6 6 7 g 2 2 m1

More information

ECE 363 FINAL (F16) 6 problems for 100 pts Problem #1: Fuel Pump Controller (18 pts)

ECE 363 FINAL (F16) 6 problems for 100 pts Problem #1: Fuel Pump Controller (18 pts) ECE 363 FINAL (F16) NAME: 6 problems for 100 pts Problem #1: Fuel Pump Controller (18 pts) You are asked to design a high-side switch for a remotely operated fuel pump. You decide to use the IRF9520 power

More information

BJT Circuits (MCQs of Moderate Complexity)

BJT Circuits (MCQs of Moderate Complexity) BJT Circuits (MCQs of Moderate Complexity) 1. The current ib through base of a silicon npn transistor is 1+0.1 cos (1000πt) ma. At 300K, the rπ in the small signal model of the transistor is i b B C r

More information

Unit 6 Operational Amplifiers Chapter 5 (Sedra and Smith)

Unit 6 Operational Amplifiers Chapter 5 (Sedra and Smith) Unit 6 Operational Amplifiers Chapter 5 (Sedra and Smith) Prepared by: S V UMA, Associate Professor, Department of ECE, RNSIT, Bangalore Reference: Microelectronic Circuits Adel Sedra and K C Smith 1 Objectives

More information

Basic Circuits. Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair,

Basic Circuits. Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair, Basic Circuits Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair, CCS - Basic Circuits P. Fischer, ZITI, Uni Heidelberg, Seite 1 Reminder: Effect of Transistor Sizes Very crude classification:

More information

MICROELECTRONIC CIRCUIT DESIGN Third Edition

MICROELECTRONIC CIRCUIT DESIGN Third Edition MICROELECTRONIC CIRCUIT DESIGN Third Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 1/25/08 Chapter 1 1.3 1.52 years, 5.06 years 1.5 1.95 years, 6.46 years 1.8 113

More information

Experiment #6 MOSFET Dynamic circuits

Experiment #6 MOSFET Dynamic circuits Experiment #6 MOSFET Dynamic circuits Jonathan Roderick Introduction: This experiment will build upon the concepts that were presented in the previous lab and introduce dynamic circuits using MOSFETS.

More information

Output Stages and Power Amplifiers

Output Stages and Power Amplifiers CHAPTER 11 Output Stages and Power Amplifiers Introduction 11.7 Power BJTs 911 11.1 Classification of Output Stages 11. Class A Output Stage 913 11.3 Class B Output Stage 918 11.4 Class AB Output Stage

More information

EE 482 Electronics II

EE 482 Electronics II EE 482 Electronics II Lab #4: BJT Differential Pair with Resistive Load Overview The objectives of this lab are (1) to design and analyze the performance of a differential amplifier, and (2) to measure

More information

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,

More information

Chapter 7 Building Blocks of Integrated Circuit Amplifiers: Part D: Advanced Current Mirrors

Chapter 7 Building Blocks of Integrated Circuit Amplifiers: Part D: Advanced Current Mirrors 1 Chapter 7 Building Blocks of Integrated Circuit Amplifiers: Part D: Advanced Current Mirrors Current Mirror Example 2 Two Stage Op Amp (MOSFET) Current Mirror Example Three Stage 741 Opamp (BJT) 3 4

More information

EE LINEAR INTEGRATED CIRCUITS & APPLICATIONS

EE LINEAR INTEGRATED CIRCUITS & APPLICATIONS UNITII CHARACTERISTICS OF OPAMP 1. What is an opamp? List its functions. The opamp is a multi terminal device, which internally is quite complex. It is a direct coupled high gain amplifier consisting of

More information

Code: 9A Answer any FIVE questions All questions carry equal marks *****

Code: 9A Answer any FIVE questions All questions carry equal marks ***** II B. Tech II Semester (R09) Regular & Supplementary Examinations, April/May 2012 ELECTRONIC CIRCUIT ANALYSIS (Common to EIE, E. Con. E & ECE) Time: 3 hours Max Marks: 70 Answer any FIVE questions All

More information

ES 330 Electronics II Homework # 2 (Fall 2016 Due Wednesday, September 7, 2016)

ES 330 Electronics II Homework # 2 (Fall 2016 Due Wednesday, September 7, 2016) Page1 Name ES 330 Electronics II Homework # 2 (Fall 2016 Due Wednesday, September 7, 2016) Problem 1 (15 points) You are given an NMOS amplifier with drain load resistor R D = 20 k. The DC voltage (V RD

More information

4.2.2 Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

4.2.2 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 4.2.2 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) The Metal Oxide Semitonductor Field Effect Transistor (MOSFET) has two modes of operation, the depletion mode, and the enhancement mode.

More information

Current Mirrors. Current Source and Sink, Small Signal and Large Signal Analysis of MOS. Knowledge of Various kinds of Current Mirrors

Current Mirrors. Current Source and Sink, Small Signal and Large Signal Analysis of MOS. Knowledge of Various kinds of Current Mirrors Motivation Current Mirrors Current sources have many important applications in analog design. For example, some digital-to-analog converters employ an array of current sources to produce an analog output

More information

d. Can you find intrinsic gain more easily by examining the equation for current? Explain.

d. Can you find intrinsic gain more easily by examining the equation for current? Explain. EECS140 Final Spring 2017 Name SID 1. [8] In a vacuum tube, the plate (or anode) current is a function of the plate voltage (output) and the grid voltage (input). I P = k(v P + µv G ) 3/2 where µ is a

More information

Chapter 13: Introduction to Switched- Capacitor Circuits

Chapter 13: Introduction to Switched- Capacitor Circuits Chapter 13: Introduction to Switched- Capacitor Circuits 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4 Switched-Capacitor Integrator 13.5 Switched-Capacitor

More information

ES 330 Electronics II Homework # 6 Soltuions (Fall 2016 Due Wednesday, October 26, 2016)

ES 330 Electronics II Homework # 6 Soltuions (Fall 2016 Due Wednesday, October 26, 2016) Page1 Name Solutions ES 330 Electronics Homework # 6 Soltuions (Fall 016 ue Wednesday, October 6, 016) Problem 1 (18 points) You are given a common-emitter BJT and a common-source MOSFET (n-channel). Fill

More information

Input Stage Concerns. APPLICATION NOTE 656 Design Trade-Offs for Single-Supply Op Amps

Input Stage Concerns. APPLICATION NOTE 656 Design Trade-Offs for Single-Supply Op Amps Maxim/Dallas > App Notes > AMPLIFIER AND COMPARATOR CIRCUITS Keywords: single-supply, op amps, amplifiers, design, trade-offs, operational amplifiers Apr 03, 2000 APPLICATION NOTE 656 Design Trade-Offs

More information

Rail to Rail Input Amplifier with constant G M and High Unity Gain Frequency. Arun Ramamurthy, Amit M. Jain, Anuj Gupta

Rail to Rail Input Amplifier with constant G M and High Unity Gain Frequency. Arun Ramamurthy, Amit M. Jain, Anuj Gupta 1 Rail to Rail Input Amplifier with constant G M and High Frequency Arun Ramamurthy, Amit M. Jain, Anuj Gupta Abstract A rail to rail input, 2.5V CMOS input amplifier is designed that amplifies uniformly

More information

C H A P T E R 02. Operational Amplifiers

C H A P T E R 02. Operational Amplifiers C H A P T E R 02 Operational Amplifiers The Op-amp Figure 2.1 Circuit symbol for the op amp. Figure 2.2 The op amp shown connected to dc power supplies. The Ideal Op-amp 1. Infinite input impedance 2.

More information

An Improved Bandgap Reference (BGR) Circuit with Constant Voltage and Current Outputs

An Improved Bandgap Reference (BGR) Circuit with Constant Voltage and Current Outputs International Journal of Research in Engineering and Innovation Vol-1, Issue-6 (2017), 60-64 International Journal of Research in Engineering and Innovation (IJREI) journal home page: http://www.ijrei.com

More information

Current Mirrors. Basic BJT Current Mirror. Current mirrors are basic building blocks of analog design. Figure shows the basic NPN current mirror.

Current Mirrors. Basic BJT Current Mirror. Current mirrors are basic building blocks of analog design. Figure shows the basic NPN current mirror. Current Mirrors Basic BJT Current Mirror Current mirrors are basic building blocks of analog design. Figure shows the basic NPN current mirror. For its analysis, we assume identical transistors and neglect

More information

Homework Assignment 12

Homework Assignment 12 Homework Assignment 12 Question 1 Shown the is Bode plot of the magnitude of the gain transfer function of a constant GBP amplifier. By how much will the amplifier delay a sine wave with the following

More information

Electronics Lab. (EE21338)

Electronics Lab. (EE21338) Princess Sumaya University for Technology The King Abdullah II School for Engineering Electrical Engineering Department Electronics Lab. (EE21338) Prepared By: Eng. Eyad Al-Kouz October, 2012 Table of

More information

Gechstudentszone.wordpress.com

Gechstudentszone.wordpress.com 8.1 Operational Amplifier (Op-Amp) UNIT 8: Operational Amplifier An operational amplifier ("op-amp") is a DC-coupled high-gain electronic voltage amplifier with a differential input and, usually, a single-ended

More information

Homework Assignment EE 435 Homework 4 Spring 2014 Due Wednesday Feb 26

Homework Assignment EE 435 Homework 4 Spring 2014 Due Wednesday Feb 26 Homework Assignment EE 435 Homework 4 Spring 2014 Due Wednesday Feb 26 In the following problems, if reference to a semiconductor process is needed, assume processes with the following characteristics:

More information

UNIT - 1 OPERATIONAL AMPLIFIER FUNDAMENTALS

UNIT - 1 OPERATIONAL AMPLIFIER FUNDAMENTALS UNIT - 1 OPERATIONAL AMPLIFIER FUNDAMENTALS 1.1 Basic operational amplifier circuit- hte basic circuit of an operational amplifier is as shown in above fig. has a differential amplifier input stage and

More information

EE105 Fall 2015 Microelectronic Devices and Circuits

EE105 Fall 2015 Microelectronic Devices and Circuits EE105 Fall 2015 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 11-1 Transistor Operating Mode in Amplifiers Transistors are biased in flat part of

More information

Chapter 10 Differential Amplifiers

Chapter 10 Differential Amplifiers Chapter 10 Differential Amplifiers 10.1 General Considerations 10.2 Bipolar Differential Pair 10.3 MOS Differential Pair 10.4 Cascode Differential Amplifiers 10.5 Common-Mode Rejection 10.6 Differential

More information

ELC224 Final Review (12/10/2009) Name:

ELC224 Final Review (12/10/2009) Name: ELC224 Final Review (12/10/2009) Name: Select the correct answer to the problems 1 through 20. 1. A common-emitter amplifier that uses direct coupling is an example of a dc amplifier. 2. The frequency

More information

Current Mirrors. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-1

Current Mirrors. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-1 Current Mirrors Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08 { Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08 { Current Source and Sink Symbol

More information

Experiments #6. Differential Amplifier

Experiments #6. Differential Amplifier Experiments #6 Differential Amplifier 1) Objectives: To understand the DC and AC operation of a differential amplifier. To measure DC voltages and currents in differential amplifier. To obtain measured

More information

A 16Ω Audio Amplifier with 93.8 mw Peak loadpower and 1.43 quiscent power consumption

A 16Ω Audio Amplifier with 93.8 mw Peak loadpower and 1.43 quiscent power consumption A 16Ω Audio Amplifier with 93.8 mw Peak loadpower and 1.43 quiscent power consumption IEEE Transactions on circuits and systems- Vol 59 No:3 March 2012 Abstract A class AB audio amplifier is used to drive

More information

Lab 2: Discrete BJT Op-Amps (Part I)

Lab 2: Discrete BJT Op-Amps (Part I) Lab 2: Discrete BJT Op-Amps (Part I) This is a three-week laboratory. You are required to write only one lab report for all parts of this experiment. 1.0. INTRODUCTION In this lab, we will introduce and

More information

EE 501 Lab 4 Design of two stage op amp with miller compensation

EE 501 Lab 4 Design of two stage op amp with miller compensation EE 501 Lab 4 Design of two stage op amp with miller compensation Objectives: 1. Design a two stage op amp 2. Investigate how to miller compensate a two-stage operational amplifier. Tasks: 1. Build a two-stage

More information

Integrated Circuit Amplifiers. Comparison of MOSFETs and BJTs

Integrated Circuit Amplifiers. Comparison of MOSFETs and BJTs Integrated Circuit Amplifiers Comparison of MOSFETs and BJTs 17 Typical CMOS Device Parameters 0.8 µm 0.25 µm 0.13 µm Parameter NMOS PMOS NMOS PMOS NMOS PMOS t ox (nm) 15 15 6 6 2.7 2.7 C ox (ff/µm 2 )

More information

Chapter 8: Field Effect Transistors

Chapter 8: Field Effect Transistors Chapter 8: Field Effect Transistors Transistors are different from the basic electronic elements in that they have three terminals. Consequently, we need more parameters to describe their behavior than

More information

EE 230 Lab Lab 9. Prior to Lab

EE 230 Lab Lab 9. Prior to Lab MOS transistor characteristics This week we look at some MOS transistor characteristics and circuits. Most of the measurements will be done with our usual lab equipment, but we will also use the parameter

More information

You will be asked to make the following statement and provide your signature on the top of your solutions.

You will be asked to make the following statement and provide your signature on the top of your solutions. 1 EE 435 Name Exam 1 Spring 216 Instructions: The points allocated to each problem are as indicated. Note that the first and last problem are weighted more heavily than the rest of the problems. On those

More information

CS and CE amplifiers with loads:

CS and CE amplifiers with loads: CS and CE amplifiers with loads: The Common-Source Circuit The most basic IC MOS amplifier is shown in fig.(1). The source of MOS transistor is grounded, also the drain resistor RD replaced by a constant-current

More information