EE311: Electrical Engineering Junior Lab, Fall 2006 Experiment 4: Basic MOSFET Characteristics and Analog Circuits

Transcription

1 EE311: Electrical Engineering Junior Lab, Fall 2006 Experiment 4: Basic MOSFET Characteristics and Analog Circuits Objective This experiment is designed for students to get familiar with the basic properties of MOSFETs and to analyze some basic MOS analogy circuits. Theoretical Background The theoretical background for this experiment is given in Microelectronic Circuit, 5th edition, by Sedra and Smith (the textbook of EE341). The subjects associated with the chapter, section and page numbers of the EE341 textbook for this experiment are given as follows: MOS IV characteristics & output resistance r o Sections , pp C biasing, current mirrors Section 4.5 & 6.3.1, pp & pp Small signal models, transconductance, voltage gain Section 4.6, pp. 296 Common source amplifier Sections & 4.7.4, pp You need to read these subjects in the EE341 textbook to get familiar with MOSFET characteristics, the operation principle, C biasing, small-signal models and common source amplifiers. For amplifier applications, MOSFETs operate in the saturation region. In this section, basic equations and concepts for the circuits in this experiment are briefly given below. Saturation Operation of MOSFTs For n-channel MOSFETs in saturation, it must satisfy the following condition, VS > VGS Vtn, and the current in saturation is given as 1 W I ( ) 2 = kn VGS Vtn (1 + λnvs), (1) 2 L where all voltages and parameters are positive. For p-channel MOSFETs in saturation, it must satisfy the following condition, VS < VGS Vtp, and the current in saturation is given as 1 W I ( ) 2 = kp VGS Vtp (1 λpvs), (2) 2 L where all voltages are negative, and W, L, k p and λ p are positive. λ (λ n or λ p for nmos and pmos, respectively) is the channel length modulation related to r o by 1 λ =, (3) ro I where r o is the output resistance and defined as Vds VS ro = =, (4) i I d at VGS which indicates that r o varies with the C bias voltage V GS. In reality, r o decreases with V GS. In the model given in Eqs. (1) and (2), λ is constant and given as λ = 1/V A, where V A is the Early voltage. If λ is small enough (or r o is large) such that λv S << 1, C current can be evaluated without considering λ in Eq. (1) or (2).

2 Transfer Characteristics of MOSFET Common Source Structure If only the C part of the amplifier is considered in Fig. 4 (see Question 3 in Preliminary Report Questions), the transfer curve will look similar to the one given in Fig. 1. Selection of the optimal operating (or quiescent) point for an amplifier needs to consider the linearity and the AC swing range to minimize output distortion. For example, the shaded area in Fig. 1 indicates a reasonable choice of the linear region with the quiescent point located at the center of the linear region. This indicates that an AC gate voltage V gs with a peak-to-peak value centered at the Q point beyond this shaded area will give rise to evident distortion in the AC output V ds. The total gate and drain voltages include C and AC components; i.e., V GS = V GS + V gs and V S = V S + V ds, where V GS and V S are C voltages, and V gs and V ds are AC voltages. The small signal voltage gain for the amplifier in Fig. 4 at this Q point with R L >> R is then given by the slope at the Q point, Vds VS = = gm( R// ro), (5) Vgs VGS where g m is transconductance of the MOSFET and defined as 2I W W g = = k ( V V ) = 2k I m n GS tn n VGS Vtn L L. (6) It is noted that g m increases with C bias voltage V S or current I, which implies that the AC voltage gain is strongly influenced by your choice of the Q point. Saturation Cutoff Triode Q point (VGS, VS) V GS V tn V tn Fig. 1 Transfer Curve of a CS amplifier, where V = 15V and V tn 3V. Overall Voltage Gain of MOSFET Common Source Amplifiers The CS amplifier given in Fig. 4 is biased by gate voltage provided by V Bias. On the other hand, the amplifier in Fig. 6 is based by current driven by the M2-M3 current mirror. If the coupling capacitors are large enough, the expressions of the voltage gain for these 2 amplifiers are actually identical (why?) and given as V V i o ( // // ) = g R r R m1 o1 L. (7) The M2-M3 current mirror provides a C current source with an internal source resistance equal to r o3 that will be measured in Step 7. Read the function of current mirrors in Sections of the EE341 text.

3 Preliminary Report Questions 1. Verify that the nmos in Fig. 2 is in saturation if V GS > V tn regardless of values of V and R. Similarly, the pmos in Fig. 3 is in saturation if V GS < V tp regardless of values of V SS and R. 2. Use the following values for nmos and pmos parameters: nmos: V tn = 0.7V, k n = 2.5E-4 A/V 2, λ n = 0.01 V -1, L = 5um and W = 10um pmos: V tp = -0.7V, k p = 0.5E-4 A/V 2, λ p = 0.01 V -1, L = 5um and W = 30um Find I of nmos in Fig. 2 at V GS - V tn = 2V and I of pmos in Fig. 3 at V GS - V tp = - 2V. 3. With only C part of the circuit (i.e., without the coupling capacitors, C C1 and C C2, input, V i, and the resistors, R and R L ), use SPICE to plot the transfer function, V S vs. V GS for 0 < V GS < 8V. Then, use Eq. (1), ignoring λ n, to solve a value for V Bias to make I = 1mA in the amplifier given in Fig. 4 (so, V ~ V /2) with the nmos parameters given in Question 2. With this value of V Bias and AC signal V i (t) = 0.2Vsinωt at f = 5kHz applied to the whole circuit in Fig. 4, use Transient Analysis in SPICE simulation to plot V o (t) and V i (t). Theoretically calculate the small signal gain compared to your SPICE results. Is V o (t) from SPICE simulation symmetrical about zero? If not, explain it (hint: look at the location of the Q point in the transfer curve carefully). 4. Estimate the slope of the transfer curve derived from SPICE in Question 3, and compared to the gain estimated in Questions 3. Why are they different? 5. In Question 3, increase the input voltage amplitude from 0.2V to 1V in your SPICE simulation. Plot V o (t) and V i (t) and explain the reasons for the distortion in V o. If you do not see evident distortion, increase the input voltage amplitude to 1.5V 6. In Question 3, perform AC Analysis in SPICE to obtain the Bode plot for the overall voltage gain V o /V i with Cgdo=5uF/m, Cgso=5uF/m, Cbd=0.03nF and Cbs=0.03nF. Use W=10um and L=5um in SPICE simulation. Sweep the frequency from 1Hz to 20MHz to observe the lower and upper 3db frequencies. (In this experiment, use these values of the device parameters, Cgdo, Cgso, Cbd, Cbs, Wand L, in all SPICE simulations) 7. Repeat Question 6 with all coupling capacitors changed to 10 uf values. Qualitatively explain your observation. 8. Select a value of R ref to make I 3 = 1.5mA in Fig. 6. Use a C current source with r o3 (calculated from I 3 and λ n3 ) to represent the current mirror in SPICE simulation to obtain the waveforms, V o (t) and V i (t). Estimate the gains from SPICE simulation and theoretical calculation. Is the gain influenced by the value of r o3? Give your reasons! Explain why the gain is larger than that observed in Question 3. Procedure Note: O NOT apply V GS, V or V SS greater than 10V. MOS Properties 1. Use one of the enhancement mode n-channel MOSFETs in the AL1116 chip to assemble the nmos circuit shown in Fig. 2. Vary V from 0V to 10V at R=100KΩ *, and use a voltmeter to measure V GS to obtain the I -V GS curve. Measure I with a 0.5V increment in V until you reach the threshold current I th ** and then use a 1V increment. To obtain the curve at a larger value of I, repeat this step with R=10KΩ and 1KΩ. Plot the I -V GS curve in regular scale (I vs. V GS ) and semi-log scale (logi vs. V GS ) for I at least as large as 5mA. I can be calculated from (V V GS )/R. * Note: when using R = 100KΩ, you need to vary V carefully to obtain I th to measure V tn. ** etermine the value of V tn based on the suggested threshold current I th on the datasheet. For AL1116, I th = 1uA at V GS = V S = V tn. Accurate values of resistance and voltage need to be measured, especially at low current.

4 2. isconnect the short between Gate and rain in Fig. 2, and apply a C voltage of (V tn + 2V) to Gate; i.e., V GS = V tn + 2V. With R = 1KΩ, measure V S at V = 5 and 10V. With these 2 sets of data for (I, V S ) and values of V GS and V tn, you are able to calculate the values of ½ k n W/L and λ n based on Eq. (1). Values of k n, λ n and V tn extracted in Steps 1 and 2 will be used in all SPICE simulations below. Simple NMOS Common Source Amplifier 3. Construct the C part of the circuit in Fig. 4 with the nmosfet used in Steps 1 and 2. Increase V Bias from 0 to 8V with an increment of 1V to measure V GS and V S to plot the transfer curve, V GS vs. V S. Within the saturation region (see Fig. 1), use a small voltage increment for V Bias (such as 0.2V) to capture the detail of the transfer curve. Choose the optimal Q point based on the transfer curve, considering the maximum output swing and linearity, and estimate the small signal gain (V o /V i ) from this curve at the selected Q point. Measure I and V S at the selected Q point. Question: Perform SPICE simulation to plot the transfer curve compared to your measurements. 4. Construct the complete circuit in Fig. 4 at your selected operating voltages using 1uF for C C1 and C C2. Verify that I and V S remain unchanged before applying V i (set V i = 0). Then, apply a sinusoidal input with a peak-to-peak value of 0.2V at f = 5K Hz. Use the oscilloscope to observe V o (t) and V i (t) on separate channels. Measure the p-to-p values of V o and V i and record the voltage gain compared to the gain estimated from Step 3. Remove R L and record the voltage gain (V o /V i ) compared to that from Step 3. Questions: Explain your findings. Perform SPICE simulation and verify the measurements with SPICE simulation. iscuss your results. 5. Increase the input peak-to-peak value until you observe the distortion on both peaks. Record the maximum and minimum voltages. Questions: Perform SPICE simulation using the same peak-to-peak input that leads to the distortion, and compare the simulation and measured results. Are these distortions caused by Triode or Cutoff operation of the nmosfet? Explain it based on the transfer curve. 6. Use the setup in Step 4 to measure the gain for every decade increment in f from 10Hz to a frequency that is at least 30 times higher than the upper 3dB frequency. However, for f near the lower and upper 3dB frequencies (f L and f H, respectively), more points are needed to obtain accurate measurements of f L and f H. o not disassemble this circuit which will be modified to the one given in Fig. 6. Question: What are the slopes in db/ecade of the Bode plot for the gain at f < f L and f > f H? Perform your SPICE simulation to draw the Bode plot. iscuss your results. What are the reasons for these corner frequencies? Explain it qualitatively. G S G S Fig. 2 Circuit for measuring the nmos threshold voltage. -V SS Fig. 3 Circuit for measuring the pmos threshold voltage.

5 V = 8V V Bias = 4kΩ V o V i 100Ω M 1 = 10kΩ Fig. 4 Single-stage nmos amplifier. C C1 = C C2 = 1uF and R G = 200KΩ. NMOS Common Source Amplifier biased by a Current Mirror 7. Construct the nmos current mirror shown in Fig 5 with V R = 0 and V SS = 8V using dual enhancement mode nmosfets in the AL1116 chip. Vary the resistance of the 10KΩ pot to obtain the current I 3 1.5I, where I is the current in Step 3. Measure R ref (when measuring this resistor, R ref must be disconnected from the circuit). With this determined R ref, vary V R from 3V to -8V and measure V S3. Plot I 3 vs. V S3, and estimate r o3 from the curve. Questions: (a) Explain your observation of I 3. To make the mirror work properly, what is the range required for V S3? Why? (b) Estimate λ n from r o3 and I 3? Is this value close to that estimated in Step 2? (c) Theoretically calculate I 3 with the determined value of R ref including the effect of r o3. 8. Use the circuits in Fig. 4 and Fig. 5 to construct the circuit in Fig. 6 with R ref determined in Step 7. Apply a sinusoidal input with a peak-to-peak value of 0.2V at f = 5K Hz and use the oscilloscope to observe V o (t) and V i (t) on separate channels. Record the overall voltage gain, V o /V i. Questions: Calculate the gain theoretically. Perform SPICE simulations. Compared the measured, calculated and simulated gains. iscuss your results. 9. Increase the input peak-to-peak value until you observe the distortion on both peaks. Record the maximum and minimum voltages. Questions: Perform SPICE simulation using the same peak-to-peak input. Compared the simulation and measured results. What are the difference between this circuit and the one given in Fig. 4 in terms of the distortion and AC swing range? V R = 1kΩ I ref R ref I 3 3 M 2 M 3 = 8V Fig. 5 nmos current mirror.

6 8V = 4kΩ C C1 0.1kΩ R G = 10kΩ I ref R ref I 3 C C2 M 2 M 3 = 8V Fig. 6 nmos CS amplifier biased by a current mirror. C C1 = C C2 = 1uF and R G = 200KΩ. Equipment List Proto-board 2 AL1116 chips (ual enhancement-mode matched pair nmosfet Array) Resistors: 200KΩ, 100KΩ, 10KΩ, 4KΩ, 1KΩ and 100Ω Potentiometer: 10K 2 Capacitors: 1uF Oscilloscope Multi-meter 2 C power supplies Function generator Prepared by M.C. Cheng, October 2005, edited by J. Carroll 2006.