12/01/2009. Practice with past exams

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1 EE40 Final Exam Review Prof. Nathan Cheung 12/01/2009 Practice with past exams Slide 1

2 Overview of Course Circuit components: R, C, L, sources I-V characteristics energy storage/dissipation Circuit analysis: Laws: Ohm s, KVL, KCL Equivalent circuits (series/ parallel, Thevenin, Norton) Superposition for linear circuits Nodal analysis Mesh analysis Phasor I and V First-order transient excitation/analysis: Second Order RLC circuits Bode Plots Slide 2 Prof. 2 Cheung

3 Overview of Course Logic gates; Combinatorial logic (sum-of-products, Karnaugh maps), sequential logic etc. Semiconductors evices pn-diodes (many types) FETs (n-channel,,p p-channel, CMOS) Useful iode and FET circuits: Amplifiers: op-amp (negative feedback), rectifiers; wave shaping circuits Slide 3 Prof. 3 Cheung

4 iode Circuit Analysis by Assumed iode States 1) Specify Ideal iode Model or Piecewise-Linear iode Model I (A) I (A) reverse bias forward bias V (V) reverse bias forward bias V on 2) Each diode can be ON or OFF 3) Circuit containing n diodes will have 2 n states 4) The combination of states that works for ALL diodes d (consistent t with KVL and KCL) will be the solution Slide 4

5 Example Problem: Perfect Rectifier Model Sketch V out versus V in Suggested problem: What if there is a 0.6V drop when diodes are on? Slide 5

6 iode with Capacitor Circuit (e.g.level Shifter) -V C V IN V C V IN - C V OUT - V OUT 1 3 t V IN (min) V OUT (t)= V C (t) V IN (t) Finds out what happens to V C when V IN changes 1) iode =open, V C (t)=0, V OUT (t)= V IN (t) 2) iode =short, V C (t)= -V IN (t), V OUT (t)=0, 3) iode =open, V C (t)= -V IN (min), V OUT (t)= V IN (t)-v IN (min) 2 t Slide 6

7 Example: iode with RL Circuit Sketch i(t) Answer Note: i(t) is continuous τ = L/R = msec Slide 7

8 Load-Line Analysis We have a circuit containing a two-terminal non-linear element NLE, and some linear components. First replace the entire linear part of the circuit by its Thevenin equivalent. Then define I and V at the NLE terminals (typically associated signs) Nonlinear 250K 1M N 200K 9µA L V S element - 1V S - - 2V E S I Slide 8

9 Example of Load-Line Analysis (con t) Given the graphical properties of two terminal non-linear circuit (i.e. the graph of a two terminal device) And have this connected to a linear (Thévenin) circuit Whose I-V can also be graphed on the same axes ( load line ) N L E N L E S - V S I 200K - 2V Application of KCL, KVL gives circuit solution I (µa) I K L The solution S - 2V! Slide 9 V S (V) 1 2

10 Example : Voltage controlled Attenuator V C and R C etermines r d at Q point of diode Slide 10

11 Example : Voltage Controlled Attenuator The large capacitors and C bias source are effective shorts for the ac signal in small-signal circuits Slide 11

12 Three-Terminal Parametric Graphs G V GS - 3-Terminal evice S I 10 I (µa) V GS = 3 V GS = 2 V GS = 1 Concept of 3-Terminal Parametric Graphs: We set a voltage (or current) at one set of terminals (here we will apply a fixed V GS, IG=0) and conceptually draw a box around the device with only two terminals emerging so we can again plot the two-terminal characteristic (here I versus V S ). 1 2 V S (V) But we can do this for a variety of values of V GS with the result that we get a family of curves. Slide 12 Prof. 12Cheung

13 Graphical Solutions for 3-Terminal evices V I G - - S 200K 2V We can only find a solution for one input (V GS ) at a time: First select V GS (e.g. 2V) and draw I vs V S for the 3-Terminal device. Now draw I vs V S for the 2V - 200KΩ Thevenin source. The only point on the I vs V plane which obeys KCL and KVL is I = 5µAat V S = 1V. Slide I I (µa) V GS = 3 V GS = 2 V GS = 1 (µa) ) V S (V) 1 2 The solution! V S (V)

14 SOLVING MOSFET CIRCUITS: STEPS 1) Guess the mode of operation for the transistor. (We will learn how to make educated guesses). 2) Write the I vs. V S equation for this guess mode of operation. 3) Use KVL, KCL, etc. to come up with an equation relating I and V S based on the surrounding linear circuit. 4) Solve these equations for I and V S. 5) Check to see if the values for I and V S are possible for the mode you guessed for the transistor. If the values are possible for the mode guessed, stop, problem solved. If the values are impossible, go back to Step 1. Slide 14

15 CHECKING THE ANSWERS NMOS Cut-off Saturation Triode 1) V GS > V T(N) in triode or saturation V GS V T(N) in cutoff 0 V to v S V to v GS 2) V S < V GS V T(N) in triode V S V GS V T(N) in saturation S GS T(N) PMOS Triode v 1) V GS <V T(P) in triode or saturation V GS V T(P) in cutoff 2) V S >V GS V T(P) in triode V S V GS V T(P) in saturation Saturation Cut-off ) S GS T(P) V 0 V S to to v GS Slide 15

16 Example Problem : MOSFET Circuit Slide 16

17 Example Problem : MOSFET Circuit Find V GS such that V S =2V Answer Guess Saturation Mode Check: V S (=2V) > V GS -V T (= =1V) 5=1V) MOSFET indeed is in saturation mode Slide 17

18 Example Problem : MOSFET Circuit Find small-signal model parameters =10-5 Siemens Slide 18

19 How do you guess the right mode? Often, the key is the value of V GS. (We can often find V GS directly without solving the whole circuit.) I V GS V T(N) definitely cutoff I V GS =V T(N) ε probably bbl saturation V S V GS -V T(N) = ε V S Slide 19

20 How do you guess the right mode? When V GS >> V TH(N), it s harder to guess the mode. I ti triode mode saturation ti mode I V GS -V TH(N) If I is small, probably triode mode Slide 20 V S

21 EXAMPLE 4 V 3 V 1.5 kω GIVEN: V TH(N) = 1 V, K= 250 µ A/V 2, λ = 0 V -1. I G V S S 1) Since V GS > V TH(N), not in cutoff mode. Guess saturation mode. 2) Write transistor I vs. V S : I = = I 1mA sat = ( 3 V 1 V ) 3) Write I vs. V S equation using KVL: - V S kΩ Ω I 4 V = 0 2 Slide 21

22 EXAMPLE 1.5 kω 4) Solve V S : I = 1mA V S = 2.5 V 4 V 3 V I G V S S 5) Check: I and V S are correct sign, and V S V GS -V T(N) as required din saturation mode. GIVEN: V TH(N) = 1 V, ½W/Lµ µ = 2 n C OX 250 µ A/V, λ = 0 V -1. Slide 22

23 WHAT IF WE GUESSE THE MOE WRONG? 1.5 kω 1) Since V GS > V TH(N), not in cutoff mode. Guess triode mode. 2) Write transistor I vs. V S : 4 V 3V G GIVEN: V TH(N) = 1 V, K= 250 µ A/V 2, λ = 0 V -1. I V S S I = (3 1 V S /2)V S 3) Write I vs. V S equation using KVL: - Slide 23 V S -1.5 kω I 4 V = 0

24 WHAT IF WE GUESSE THE MOE WRONG? 1.5 kω 4) Solve for V S with quadratic equation by combining 2) and 3): G 4 V 5) Check: 3 V I V S S V S = {4 V, 2.67 V} V S > V GS V T(N) = 2V Neither value valid in triode mode! Guess is incorrect. GIVEN: V TH(N) = 1 V, K= 250 µ A/V 2, λ = 0 V -1. Slide 24

25 Another Perspective In this circuit, the transistor delivered a constant current I SAT to the 1.5 kω resistor. 1.5 kω This circuit acts like a constant current source, as long as the transistor remains in saturation mode. I SAT does not depend on the attached resistance if saturation ti is maintained. 4 V 3V G I V S S I SAT 1.5 kω Slide 25

26 Another Perspective I SAT does depend on V GS ; one can adjust the current supplied by adjusting V GS. R L The circuit will go out of saturation mode if V GS <V T(N) or V S < V GS V T(N) This can happen if V GS is too large or too small, or if the load resistance is too large. V V GS G I V S S I SAT R L Slide 26

27 2kΩ 1.5 kω ANOTHER EXAMPLE I 1) What is V GS? No current goes into/out gate. V GS = 3 V by voltage division. Guess saturation (randomly). G 4V 2) Write transistor I vs. V S : 6kΩ GIVEN: V TH(N) = 1 V, K= 250 µ A/V 2, λ =0V -1. V S S I = I = 1mA sat = ( 3 V 1 V) 3) Write I vs. V S equation using KVL: - V S -1.5 kω I 4 V = V S =2.75V consisitent with saturation mode Effectively the same circuit as previous example: only 1 voltage source in this case 0 2 Slide 27

28 The CMOS Inverter: Current Flow V OUT N: sat P: sat i V V N: off P: Triode C V IN G I S V OUT N: sat P: Triode A B E G S N: Triode P: sat 0 0 N: Triode P: off V V IN Slide 28

29 Another CMOS Example: The LATCH CLK V CLK V ata (V IN ) is written to the internal node (V OUTINT ) when the clock is low. V OUT remains frozen. OUT V IN CLK V OUTINT CLK V OUT When the clock is high. The (inverted) internal node voltage is written to V OUT. The internal node V OUTINT remains frozen Slide 29

30 THE LATCH V V When CLK is low the lefthand transistors conduct. The CLK CLK right-hand transistors are open. 0 V V V OUT INT is charged to V IN. OUTINT g IN V IN V OUTINT V OUT V OUT remains the same; there is no charging path. CLK V CLK 0V Slide 30

31 THE LATCH V V When CLK is high, the right-hand transistors CLK CLK conduct. V the left-hand transistors are 0 V open. V IN V OUTINT V OUT V OUT is changed to V OUT INT. CLK CLK V V OUTINT remains the same; 0V there is no charging path. Slide 31

32 CONCEPT OF STATE V V A latch stores a 1 or 0. V IN CLK CLK CLK Next State CLK Current State The stored value is known as the state. This is one of the basic elements needed to make a state machine (covered in EE 20 and CS 61C). Slide 32

33 LATCH AS GATEKEEPER A signal may have to go through a complex system of gates, with paths of different delays: possibility of false output! Combinatorial Logic Signal propagates all the way through Includes our logic gates: NAN, NOT, etc. Slide 33 Sequential Element Prevents changes in output until signaled

34 Amplifier Efficiency Power Supply A Source Amplifier Power Supply B Amplifier Efficiency η = 8/22.5 =36% Slide 34 Source P i = (10-3 V) 2 /10 5 Ω =10-11 W Load P 0 = (8V) 2 /8Ω =8 W Power Supplies P s = 15W7.5W =225W 22.5 Amplifier P -11 d = 22.5W10 W-8W = 14.5 W Load

35 ifferential Signal and Common Mode Signal Redefine the inputs in terms of two other voltages: 1. differential mode input v id v i1 v i2 2. common mode input v icm (v i1 v i2 )/2 so that v i1 = v icm (v id /2) and v i2 = v icm - (v id /2) v o = A d v id Acm v icm differential mode gain common mode gain Slide 35

36 Common Mode Rejection Ratio Example CMRR (in db) = 20log A d A cm ifferential signal from sensor = 1mV (peak). We want outputs signal > 1V implies A d > 1000 Common mode signal =100V (from power line). We want common mode signal < 0.1V implies A cm <10-4 Therefore CMRR needs to be > 20log(10 7 )= 140dB Slide 36

37 Offset Voltage, Offset Current, and Bias Current Given V off =2mV I B = 100nA I off = 20nA A cm =1 A d =100 Both input terminals to ground through 100kΩ resistors Use superposition Vo = A d (V voff V Ioff ) A cm v icm = 100( )1(0.01)=0.3343V Slide 37

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