Review Sheet for Midterm #2

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1 Review Sheet for Midterm #2 Brian Bircumshaw 1 Miterm #1 Review See Table 1 on the following page for a list of the most important equations you should know from Midterm #1. 2 Large Signal (LS) & Small Signal (SS) Concepts Most real world circuits are broken up into both a large signal (LS) and a small signal (SS) model. LS models are used to determine the biasing conditions. They include common circuit elements (e.g., transistors, diodes, R, L, C, etc.), as well as constant voltage and current sources. From the LS model, a SS model can be created. This is done by transforming all circuit elements to their SS equivalents (e.g., transistors become voltage controlled current sources; R s remain the same; L s often become open circuits; C s often become shorts). Constant voltage sources beomce SS grounds while constant current sources become SS open circuits. If the sources are imperfect, the sources resistance must be taken into account. The SS model is actually a linearized model (Taylor Series approximation) of the circuit, linearized about the bias point (also known as the operating point). The SS model is extremely useful in analyzing complex circuits and determining such things as voltage/current gain, transconductance, transresistance, R in, and R out. The labeling convention used by the book for mixed LS and SS sources is as follows: v I (t) }{{} LS + SS = V I }{{} LS + v i (t) }{{} SS (1) where V I is a constant in time. The full, real world circuit can be formed by incorporating all of the SS sources into the LS model. The SS models for both NMOSFETs and PMOSFETs in saturation are shown in Figure 1. The small signal transconductances are found via a Taylor Series approximation of I d : i ds I DS v gs + I DS v bs + I DS v ds V }{{ GS V }}{{ BS V }}{{ DS } g m g mb g d = 1 r o i sd I SD v sg + I SD v sb + I (2) SD v sd V }{{ SG V }}{{ SB V }}{{ SD } g m g mb g d = 1 r o The above definitions for g m, g mb, and r o are valid for all three regions of operation: saturation, triode, and cutoff. In saturation, for given bias condtions, I D = I DS = I SD and V dsat = V dsatn = 1

2 Misc. PMOSFET NMOSFET I, R, Velocity, Doping ] Description Variable Example Ohm s Law V = IR 1 kω Mass-Action Law np = n { 2 i /cm 3 V µ n E = µ n Drift Velocity v dn = L E E sat 10 6 cm/s v satn E E sat Drift Current Density J d = J dn + J dp = q (nv n + pv p ) 1 A/cm 2 Drift Current I = J d A A = width thickness 100 µa Resistivity ρ = 1 q(nµ n+pµ p) 100 mω cm Conductivity σ = 1 ρ 10 S/cm Resistance R = L ρ W t 1 kω Sheet Resistance R sh = ρ t 5 kω/ Cutoff I ds = 0 [ V GS < V T n ] 0 A Triode I ds = W L k n V GS V T n V DS 2 V DS 100 µa V GS > V T n, V DS V GS V T n Saturation I ds = 1 W 2 L k n [V GS V T n ] 2 (1 + λ n V DS ) 1 ma V GS > V T n (, V DS V GS V T n Backgate Effect V T n = V T 0n + γ n 2φp V BS ) 2φ p 1.5 V V BS < 0, φ p < 0, V T n > V T 0n Cutoff I sd = 0 [ V SG < V T p 0 A Triode I sd = W L k n V SG + V T p V SD 2 V SD 50 µa V SG > V T p, V SD V SG + V T p Saturation I sd = 1 W 2 L k n [V SG + V T p ] 2 (1 + λ n V SD ) 0.5 ma V SG > V ( T p, V SD V SG + V T p Backgate Effect V T p = V T 0p γ p 2φn V SB ) 2φ n 1.5 V V SB < 0, φ n > 0, V T p > V T 0p V dsatn V GS V T n 0.5 V V dsatp V SG + V T p 0.5 V L Channel Modulation λ n = λ 0 0n L λ 0 = 0.01, L 0 = 1µm /V µm L Channel Modulation λ n = λ 0 0n L λ 0 = 0.01, L 0 = 1µm /V µm Table 1: Table summarizing materials covered up to Midterm #1. 2

3 (a) NMOS (b) PMOS Figure 1: Full small signal models for the n-channel and p-channel MOSFETs. Ignore the capacitors for Midterm #2 (i.e., for Midterm #2, replace the capacitors in the figure above with open circuits). These are figures 4.24 and 4.26 from Howe and Sodini, respectively. V dsatp, the small signal transconductances are: g m 2I D W 2I D k n V dsat L g m γ g mb 2 V BS 2φ p r o = 1 1 g d λi D (3) Note the following: The equations in (3) are good for both NMOS and PMOS. The equations in (3) are good for transistors in saturation only. The equations are different for the triode region, though the models depicted in Figure 1 are correct for both saturation and triode regions. 3

4 Changing I D will change both g m and r o. Increasing W and L by the same factor will change only r o. Hence, g m and r o can be changed independently of one another. If the bulk of the transistor is attached to the source, V BS = V SB = 0 = g mb = 0. If the bulk terminal is not explicitly shown, assume that it is attached to the lowest potential if it is a NMOS, and the highest potential if it is a PMOS. 3 Single Transistor Amplifiers There are three single transistor amplifiers: 1. Common Source (CS). The source terminal is attached to a constant voltage. It is a good transconductance amplifier. 2. Common Gate (CG). The gate terminal is attached to a constant voltage. It is a good current buffer (output stage for a current amplifier). 3. Common Gate (CD). The drain terminal is attached to a constant voltage. It is a good voltage buffer (output stage for a voltage amplifier). The configuration of each amplifier is depicted in Figure 2. Remember the following: The input is never at the drain. The input is at the gate, unless the gate is a SS ground (CG). In this case, the input is at the source. The output is never at the gate. The output is at the drain, unless the drain is a SS ground (CD). In this case, the output is at the source. 3.1 Gain, R in, and R out With amplifiers, we are concerned with the controlled source gain (e.g., A v for a voltage amplifier, G m for a transconductance amplifier), R in, and R out. To determine the controlled source gain, we first remove the source and load resistances, R S and R L. Next, we bias the circuit. Finally, we hook up a SS voltage or current source at the input and mearsure the output current or voltage, as illustrated in Figure 3. Mathematically, this is equivalent to: A v = V OUT V IN v out v in Voltage Gain A i = I OUT I IN G m = I OUT V IN i out i in i out v in Current Gain Transconductance (4) R m = V OUT I IN v out i in Transresistance 4

5 Figure 2: Single transistor amplifier configurations. This is a figure from the backside cover of Howe and Sodini. 5

6 Figure 3: Method to calculate two-port SS models. For any circuit, to find the equivalent two-port controlled source gain (A v, A i, G m, and R m ), R in, or R out, replace the dark gray boxes in this figure with the biased circuit of interest. As directed in the figure, attach the test voltage/current source and, if applicable, the load or source resistance (R L and R S ). Then, measure the output current/voltage or test current/voltage indicated in the figure. Use (4) and (5) to calculate the controlled source gain, R in, or R out. This is figure 8.3 from Howe and Sodini. 6

7 Figure 4: The controlled source gain, R in, and R out of the three single transistor amplifiers. The values presented are approximations. This is a figure from the backside cover of Howe and Sodini. Notice that we have used the book s labeling convention (1). The values of A v, A i, G m, and R m are most readily obtained via hand analysis of the SS model. To find R in, we hook up the load resistance (R L ) and bias the circuit. Then, we attach a SS test source (voltage or current) at the input, and measure the current or voltage accross the input source. R out is found in a similar manner. We hook up the source resistance (R S ) and bias the circuit. Then, we attach a SS test source (voltage or current) at the output, and measure the current or voltage accross the output source. Mathematically: R in = V IN I IN R out = V OUT I OUT v in i in v out i out (5) The controlled source gain, R in, and R out of the three single transistor amplifiers is recorded in Figure 4. Note that these values are approximations. When in doubt, always perform a SS analysis. Also note that these values correspond to 2-port models that take the forms depicted in Figure 5. The 2-port models are all equivalent. That is, using Thevenin and Norton equivalents (Figure 6), any 2-port can be converted into any other 2-port model. 7

8 Figure 5: The four possible 2-port models. This is a figure from the backside cover of Howe and Sodini. 8

9 R eq I o I o V T + + V o I N = V T R eq + R eq V o (a) Thevenin to Norton I o R eq I o I N + R eq V o V T = I N R eq + + V o (b) Norton to Thevenin Figure 6: Procedure for transforming between Thevenin and Norton equivalent circuits. 4 Current Mirrors A current mirror is a very convenient way of generating a specific current in a circuit. Most single transistor amplifiers are biased with current sources obtained, in some way or another, from a current mirror. An example current mirror is pictured in Figure 7. For the mirror pictured: V REF = V T n + I OUT = ( W L ( W L ) ) 2 1 IREF ( W ) k n2 (6) L 1 I REF (7) Notice that the current mirror structure can also provide a very good voltage reference: V REF. Further, note that for an effective mirror we usually require L 1 = L 2. An even better mirror is one in which the controlled transistors (like M2 in Figure 7) are all of the same size. 1 By shorting the drains of the controlled transistors together, it is possible to get any integer multiple of I REF. 1 NOTE: For the exam, it is not required that you know/understand the following footnoted material. This information is provided for your enlightenment as a circuit designer. When transistors have the same W/L, and are situated relatively close to one another physically, the transistors are said to be well matched. The ratios of (W/L) s between well matched transistors will remain constant despite variations in fabrication. Due to variations in fabrication and operation, fabricated transistors never have the exact same dimensions as designed. Typically, the dimensions of all transistors in a particular area of a chip vary by the same amount. For example, if the fabricated dimensions of M1 in Figure 7 are actually W fab 1 = α(w design 1 2ɛ a) and L fab 1 = β(l design 2ɛ b ), then the fabricated dimensions of M2 will vary similarly: W fab 2 = α(w design 2 2ɛ a) and L fab 2 = β(l design If our transistors are well matched, then L design 1 = L design 2 and W design 1 = W design W fab L 2 W fab L 1 = 9 W design L 2 W design L 1 2. In this case: 1 2 2ɛ b ). (8)

10 Figure 7: Sample current mirror. This is figure 9.27 from Howe and Sodini. The SS output resistance of the current mirror, r oc, looking into the drain of M2, is: 5 Voltage Swing r oc = r o2 1 λ 2 I OUT (9) As transistors have scaled down and voltage supplies have dropped, voltage swing has become of greater and greater concern. The following steps can help you determine the voltage swing in a circuit. Output Swing 1. Examine the LS model. 2. Require all transistors to be in the saturation (high-gain) region. 3. Adjust V OUT above the bias point until a transistor enters the triode or cutoff regions, or until the corresponding V IN goes above its maximum value (often V DD ) or below its minimum value (often V SS ). 4. The V OUT determined in the previous step is V OUT,max. 5. Again, examine the LS model and require all transistors to be in the saturation (highgain) region. 6. Adjust V OUT below the bias point until a transistor enters the triode or cutoff regions, or until the corresponding V IN goes above its maximum value (often V DD ) or below its minimum value (often V SS ). 7. The V OUT determined in the previous step is V OUT,min. 8. The output swing is: V OUT,min < V OUT < V OUT,max. Input Swing 1. Examine the LS model. Therefore, the ratio I OUT /I REF will be as designed. 10

11 2. Require all transistors to be in the saturation (high-gain) region. 3. Adjust V IN above the bias point until a transistor enters the triode or cutoff regions, or until the corresponding V OUT goes above its maximum value (often V DD ) or below its minimum value (often V SS ). 4. The V IN determined in the previous step is V IN,max. 5. Again, examine the LS model and require all transistors to be in the saturation (highgain) region. 6. Adjust V IN below the bias point until a transistor enters the triode or cutoff regions, or until the corresponding V OUT goes above its maximum value (often V DD ) or below its minimum value (often V SS ). 7. The V IN determined in the previous step is V IN,min. 8. The output swing is: V IN,min < V IN < V IN,max. 6 Solving Circuit Problems When dealing with any analog circuits problem we are usually concerned with two things: (1) meeting the required specifications, and (2) biasing the circuit properly. Based on the given situation, one of the three general approaches presented in Table 2 on the next page can be used to solve the problem. 11

12 Situation Goals Approach Given Circuit and Bias Find Specs 1. Use LS model and bias conditions to determine bias voltages and currents. Determine W/L of each transistor. Assume MOSFETs are in saturation. 2. Check to make sure MOSFETs are in saturation. If not, something may be wrong and you should check your work. 3. Determine small signal parameters: g m, r o, and g mb. 4. Determine specs: voltage gain, current gain, R in, R out, etc. Given Circuit and Specs Find Bias 1. Use SS model to solve for given specs. Use these equations to determine bias currents and voltages. Assume MOSFETs are in saturation. 2. Check to make sure MOSFETs are in saturation. If not, something may be wrong and you should check your work. 3. If asked, determine input and output swings, and/or power consumption. Given Specs (no Circuit) Create Design 1. Postulate circuit needed. 2. Determine specs from SS model of postulated circuit, assuming MOSFETs are in saturation. 3. Determine required bias conditions based on SS parameters. If needed, determine input and output swings, and/or power consumption. 4. Check to see if your circuit meets all the specs. If you do not meet the specs, return to step Check to make sure MOSFETs are in saturation. If not, something may be wrong and you should check your work. Table 2: General circuit problem solving approaches for different situations. 12

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