Improved Inverter: Current-Source Pull-Up. MOS Inverter with Current-Source Pull-Up. What else could be connected between the drain and V DD?

Transcription

1 Improved Inverter: Current-Source Pull-Up MOS Inverter with Current-Source Pull-Up What else could be connected between the drain and? Replace resistor with current source I SUP roc i D v IN v OUT Find the voltage transfer curve graphically by superimposing vs. v OUT (load line) on top of the drain characteristics I SUP r oc r oc we have a plot of vs. and we know that v OUT = - therefore, the current source vs. v OUT is a mirrored version of the plot of vs. (c) Samll-signal (incremental) resistance can be large --> can get high small-signal gain (and therefore, a narrow transition region) Total current is large --> fast transitions

2 Load-Line nalysis of Improved Inverter Voltage transfer curve with idealized current-source pull-up is much closer to that of the ideal inverter i D p-channel MOSFET as a Current-Source Pull-Up Use p-channel MOSFET M (with well connected to the source to make V SB = 0 and source connected to the supply voltage) connect the gate to a battery V B that results in an appropriate value of DC current -I D = I D. I SUP r oc = V GS V B M I D v OUT = v DS I D M I D V MX = V M Cutoff, M Triode M Sat, M Triode Question: how to implement the current source using transistors? M Sat, M Sat M Triode, M Sat V MIN V (c) (d)

3 Voltage Transfer Curve In order to find the slope at = V M, we note that both transistors are saturated there (near point ) and that the small-signal models from Chapter are valid Complementary MOS (CMOS) Inverter Concept: transistor switches connect output either to or to ground s v sg = 0 V g g mp v sg d r op INPUT HIGH OUTPUT LOW INPUT LOW OUTPUT HIGH g d v out (c) v in v gs g mn v gs r on s Slope of transfer curve at = V M : dv OUT dv IN V M v out = = g v mn ( r on r op ) in Practical realization: connect input to gate of p-channel device. = --> V SG = - = 0 < - V Tp --> cutoff = 0 --> V SG = - = >> - V Tp --> on (triode region) Graphical analysis: need to find family of load lines since input is connected to gate of M The transition region can be much steeper than for the resistor load, while the large DC drain current at V M results in short propagation delays... what more could be desired? DC power is wasted when inverter is in = V MIN state... need a switchable current supply to disconnect when output is low

4 p-channel MOSFET Characteristics p-channel MOS load device: V SGp = - as increases, the source-gate voltage V SGp decreases. Switchable Current-Source Pull-Up * The drain characteristics are - I Dp = - I Dp (V SG, V SD ), which can be expressed as the switchable pull-up s current-voltage characteristic, = (, ) since = -I Dp and V SG = - and = V SD. V SGp V SDp = - I Dp = - I Dp = V SD = note that the bulk connection is tied to the source ( ), which results in a constant threshold voltage. - V Tp

5 CMOS Transfer Characteristic CMOS Process Sequence plotting the p-channel pull-up on the n-channel driver s drain characteristics allows us to find the input-output voltage pairs that satisfy the constraint that I Dn = - I Dp Masks and : and active V DD ctive I Dn = I Dp I Dp = I Dn thick (field) oxide n-channel p-channel

6 CMOS Process Sequence (Cont.) CMOS Process Sequence (Cont.) Masks : Mask(s) : Mask (clear field) for masking NMOS implant (s, donors -- for n source/drain regions) and is then the dark field inverse is used for masking PMOS implant (B, acceptors -- for p source/drain regions). s implant is heavier so polysilicon gate in n thick (field) oxide n p p n n p p

7 CMOS Process Sequence (Cont.) Masks -6: after depositing µm of SiO, etch contacts (mask ); deposit l metallization (mask 6) for interconnect n p p n n p p