University of Pittsburgh

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1 University of Pittsburgh Experiment #4 Lab Report MOSFET Amplifiers and Current Mirrors Submission Date: 07/03/2018 Instructors: Dr. Ahmed Dallal Shangqian Gao Submitted By: Nick Haver & Alex Williams Station #2 ECE 1212: Electronic Circuit Design Laboratory

2 Introduction The purpose of this experiment will be to design an amplifier using a metal-oxide semiconductor field-effect transistor (MOSFET). The basic operation of the MOSFET is similar to the BJT used in Experiment #3. The main difference is that while the BJT acts as a currentcontrolled switch, the MOSFET acts as a voltage-controlled switch. Therefore, MOSFET let-through current and source-to-drain voltage are both dependent on gate-to-source voltage. Comparable to the BJT, the gate-to-source voltage of the MOSFET must reach a certain level, known as the threshold voltage, before the device can start conducting between its drain and source. MOSFETs can be fabricated as one of two types: n-channel or p-channel, often referred to as NMOS or PMOS. NMOS transistors are made up of an n-type source and drain on a p-type substrate. When a voltage is applied to the gate of an NMOS transistor, an induced n-type channel is created in the p-type substrate, allowing current to flow from the source to the drain. PMOS transistors are made up of a p-type source and drain on an n-type substrate. PMOS operation can be thought of as the logical opposite of NMOS operation. When a voltage is applied to the gate of a PMOS transistor, current cannot pass from the source to the drain. When voltage is removed, however, a channel is formed in the n-type substrate, allowing for conduction from the source to drain. In Experiment #4, NMOS transistors will be used. In the MOSFET amplifier design, a current source is used at the drain of the MOSFET. Because current sources are not available in the lab, constructing this circuit element will be the first part of Experiment #4. The current source will also be constructed using NMOS transistors. Procedure Part I: Design of a Current Mirror From the CD4007 datasheet, it was determined that transistor supply voltage should be limited to 3 18 V and output current no less than 3.4mA (for V DD = 15 V) for the transistor to operate in saturation mode, allowing for the linear i D - v DS curve needed for amplification. A supply voltage of V DD = V SS = 12 V was chosen for the design. Like in Experiment #3, several device-specific characteristics of the MOSFET needed to be measured before beginning the design. This experiment utilized a CD4007 MOSFET array, whose pinout is shown in Fig. 1. As shown in Fig. 1, the device is made up of three p-type transistors and three n-type transistors. Only one of the n-type transistors was evaluated using the curve tracer. Figure 1: Pin Layout for CD4007 MOSFET Array Using the curve tracer, threshold voltage (V t) was calculated to be V. From the i D - v DS curve, it was determined that the drain current range available for saturation was approximately between 1 and 10 ma. Using i D v GS curves, gate-source voltages (v GS) was determined for the minimum and maximum drain currents, as well as a nominal value of 4.0 ma. Drain currents and their corresponding gate-source voltages are shown in Table 1. Drain Current (id) Gate-Source Voltage (vgs) 1.0 ma V 4.0 ma V 10.0 ma V Table 1: Drain Current and Gate-Source Voltages for CD4007 NMOS With device-specific values for the MOSFET obtained, parameters for the circuit in Fig. 2 were then chosen. Values for resistor R were chosen for drain currents of both 1.0 and 4.0 ma using Eq. 1.

3 I D = V DD + V SS V GS R (1) Resistor values of kω and kω were calculated for drain currents of 1.0 and 4.0 ma, respectively. For both drain currents, output resistance r o and transconductance g m were calculated. Output resistance was calculated as the inverse of the slope of the i D v DS in saturation mode. Transconductance was calculated as the slope of the i D v GS curve. Curve measurements and calculations for output resistance and transconductance for both drain currents are shown in Table 2. ID = 1.0 ma ID = 4.0 ma (V DS1, I D1) (1.762 V, ma) (3.234 V, ma) (V DS2, I D2) (8.923 V, ma) (7.958 V, ma) Output Resistance (ro) kω kω (V GS1, I D1) (2.601 V, ma) (4.331 V, ma) (V GS2, I D2) (2.708 V, ma) (4.437 V, ma) Transconductance (gm) ms ms Table 2: Output Resistance and Transconductance for Drain Currents of 1.0 and 4.0 ma Figure 2: MOSFET Current Mirror for Amplifier Biasing For the two currents, curve tracer plots were used to estimate gate-source voltages. Using Eq. 1, values for resistor R in Fig. 2 were chosen for the two sets for gate-source voltage and current. Based on the calculated resistance values, resistor values were chosen based on the resistors available in the lab. These values are shown in Table 3. ID = 1.0 ma ID = 4.0 ma V GS V V R (Calculated) kω kω R (Built) kω kω Table 3: Resistance and Gate-Source Voltage Values for Current Mirror Currents of 1.0 and 4.0 ma Next, a decade resistor (R D) was connected to the output of the current mirror. The decade box was first set the R values for each of the two currents. Supply voltage, drain-source voltage on each side of the current mirror, and reference and output current were measured for both currents. These measurements are shown in Table 4. ID = 1.0 ma ID = 4.0 ma Supply Voltage (V SS) V V Drain-Source Voltage (V DS2) V V Drain-Source Voltage (V DS3) V V Reference Current (I REF) ma ma Output Current (I OUT) ma ma Table 4: Currents and Voltage Measurements for Current Mirrors with Equal Reference and Load Resistances Lastly, the decade box was changed so that the proportion of R D/R ranged from 0.2 to 5.0 while R was fixed for the two currents. V DS and I D on the load side of the current mirror were recorded and plotted, as shown in Fig. 3.

4 Part II: Common-Source NMOS Amplifier Biased with Current Mirror In Part II, the goal was to build a common-source NMOS amplifier with a gain of -5 V/V, for I D,HIGH and I D,LOW. Given a specified input resistance of 9 MΩ and a load resistance of 1 MΩ, the circuit in Fig. 4 was designed. Figure 4: Common-Source NMOS Amplifier Biased with Current Mirror In the prelab, R D, R G, and R s were calculated for both drain currents. Circuit analysis was used to determine that the input resistance was equal to resistor R G. Therefore, R G was chosen to be 9 MΩ in both cases. Using the approximation in Eq. 2, R s was calculated. Minimum capacitor values for C 1, C 2, and C S were also calculated for both currents, as shown in Table 5. A V = g m(r D R L ) 1 + g m R s R D R L R s (2) ID = 1.0 ma ID = 4.0 ma R D 6.0 kω 1.5 kω R G 9 MΩ 9 MΩ R s Ω Ω C 1 (minimum) nf nf C 2 (minimum) nf nf C s (minimum) nf nf Table 5: Resistance and Minimum Capacitance Values for Common-Source NMOS Amplifier Based on the minimum capacitor values shown in Table 5 and the capacitors available in the lab, the values shown in Table 6 were implemented for both drain currents. Minimum Actual C nf 4.0 nf C nf 22.0 nf Cs nf 22.0 nf Table 6: Minimum and Actual Capacitance Values for Common-Source NMOS Amplifier The circuit was constructed based on the 4.0 ma drain current parameters, and a voltage gain of V/V was observed. It was determined that, in order to increase voltage gain, drain current had to be reduced. A lower drain current was desired because this allows for a far greater resistance R d to be used, though g m decreases at lower drain currents, the higher resistance value reduces the effect of g m on the gain significantly. R D was ultimately increased to 39.0 kω, resulting in a final drain current of ma. To observe the effect of input signal amplitude on amplifier gain, the circuit was connected to the oscilloscope, which functioned as a 1 MΩ load. The oscilloscope was then used observe the input and output signals at various amplitudes and calculate voltage gains. Input signal peak-to-peak voltages were set to 50 mv, 75 mv, and 100 mv, and the corresponding voltage gains were recorded, as shown in Table 7. Input and output signals were observed on the oscilloscope, as shown in Fig Input Signal Peak-to-Peak Voltage Amplifier Voltage Gain 50 mv V/V 75 mv V/V 100 mv V/V Table 7: Input Signal Peak-to-Peak Voltages and Gains for Common-Source NMOS Amplifier

5 Iout (ma) For the decreased drain current final design with input V pp = 100 mv and a frequency of 1 khz, gate-source voltage, drain-source voltage, and drain current were measured for each of the three MOSFETs, as shown in Table 8. Next, the frequency of the input signal generator was decreased to the frequency at which the voltage gain was times that at 1 khz, resulting in a frequency of 670 Hz. The frequency of the input signal generator was then increased until an equal voltage gain was observed, at 320 khz. The difference in these two frequencies was determined to be the 3-dB bandwidth of the amplifier, khz. Finally, the gain equation was analyzed for a way to reduce the effect of g m on the gain. The way to do so was by raising the values of R d and R s, which incidentally, was the method used earlier for the construction of the tested circuit. Results Part I Iout vs. Rd/Rm for Iref = 1.0 ma and Iref = 4.0 ma I = 1.0 ma I = 4.0 ma Rd/Rm Figure 3: Current Mirror IOUT vs. RD/RM for IREF = 1.0 ma and IREF = 4.0 ma From Fig. 3, it was noted that the current mirror performed better for larger values of R D. At higher values of R D, V DS decreases, increasing the voltage across the decade resistor. This increased voltage increased output current. Table 3 depicts the drain currents measured for different resistances R d when the R m value chosen was designed to get 1 ma of current. Table 4 is similar except R m was picked to get 4 ma of current. Part II From Fig. 3, it was noted that the current mirror performed better for larger values of R D. At higher values of R D, V DS decreases, increasing the voltage across the decade resistor. This increased voltage increased output current. Table 3 depicts the drain currents measured for different resistances R d when the R m value chosen was designed to get 1 ma of current. Table 4 is similar except R m was picked to get 4 ma of current. Amplifier input and output signals were observed for varying peak-to-peak input voltage. Input and output voltage signals are shown in Fig. 5 7.

6 Figure 5: Amplifier Input and Output for Input Vpp = 50 mv Figure 6: Amplifier Input and Output for Input Vpp = 75 mv Figure 7: Amplifier Input and Output for Input Vpp = 100 mv In the final amplifier design, a supply voltage of V pp = 12 V was used with an input signal frequency of 1 khz, along with R D = 39.0 kω and R m = kω. An input peak-to-peak voltage of 116 mv was observed, while an output peak-to-peak voltage of 504 mv was observed, resulting in a voltage gain of V/V. Gate-source voltages and drain-source voltages measured at this operating point are shown in Table 8. Gate-Source Voltage (VGS) Drain-Source Voltage (VDS) Drain Current (ID) Amplifier (Q1) V V ma Current Mirror (Q2) V V ma Current Mirror (Q3) V V ma Table 8: Gate-Source and Drain-Source Voltages for Final Common-Source NMOS Amplifier

7 Discussion This experiment served as a demonstration of some of the issues that arise when making simplifying assumptions as an engineer. Part I of the experiment was straightforward, but initially troublesome as the values measured were lower than what was expected. This issue however, was because of a discrepancy between the circuit used for calculations and the circuit built. The reference circuit for calculations shown in Fig. 2, with a voltage source V DD located above resistor R. However, the circuit the lab asks to be constructed is slightly different in that it is grounded at the location, resulting in a lower overall current. We found that when adding in the V DD source the measured current was exactly as predicted. Part II was a more difficult in that the circuit repeatedly failed to meet voltage gain expectations. The class as a whole struggled to achieve the gains that were calculated and had to make many adjustments before achieving gains near the desired result. This lab fits into a theme of the class, which focuses on the many differences between theory and actuality. The fact that g m changed for different currents, and that values like r o were not taken into consideration, required many adjustments. A future lab that would pair well with this lab would be to look into the effect of frequency on MOSFET amplifiers. Increasing the frequency above 1 khz resulted in gains as of nearly fifty. Conclusion In Part I, the circuit initially did not perform as well as expected. However, analyzing the difference between the constructed circuit and the circuit used for calculation accounted fully for the discrepancy in values. Overall, the current source circuit is relatively simple and was a valuable thing to learn if ever a current source is needed in the future. Part II was surprising in how poorly everyone s circuits performed initially. Despite the fact that some assumptions were used for the calculations, it was still expected that there would be some gain. But for a while most people struggled to even attain a gain of one, and everyone had to do a great amount of experimentation to achieve reasonable results. A big takeaway is the reminder that circuit design often involves many assumptions which are not always true and can sometimes influence the results dramatically. The 3-dB bandwidth was also a surprising result. As the transistor functioned effectively up until about 300 khz, a far larger value than anticipated, particularly as the BJT amplifier in Experiment #3 had a much smaller operating bandwidth. References Dr. Ahmed Dallal s ECE 1212 Lecture and Curve Tracer Notes Texas Instruments CD4007UB CMOS Integrated Circuit Data Sheet