CMOS Transistor and Circuits. Jan 2015 CMOS Transistor 1

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1 CMOS Transistor and Circuits Jan 2015 CMOS Transistor 1

2 Latchup in CMOS Circuits Jan 2015 CMOS Transistor 2

3 Parasitic bipolar transistors are formed by substrate and source / drain devices Latchup occurs by establishing a low-resistance paths connecting VDD to VSS Latchup may be induced by power supply glitches or incident radiation If sufficiently large substrate current flows, VBE of NPN device increases, and its collector current grows. This increases the current through RWELL. VBE of PNP device increases, further increasing substrate current. Jan 2015 CMOS Transistor 3

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5 If bipolar transistors satisfy βpnp x βnpn > 1, latchup may occur. Operation voltage of CMOS circuits should be below Vlatchup. Remedies of latchup problem: 1. Reduce Rsubstrate by increasing P doping of substrate by process control. 2. Reducing RWELL and resistance of WELL contacts by process control. 3. Layout techniques: separation of P and N devices, guard rings, many WELL contacts (at design). Jan 2015 CMOS Transistor 5

6 Pass Transistors q We have assumed source is grounded q What if source > 0? e.g. pass transistor passing V DD q V g = V DD If V s > V DD -V t => V gs < V t Hence transistor would turn itself off q nmos pass transistors pull no higher than V DD -V tn Called a degraded 1 Approach degraded value slowly (low I ds ) q pmos pass transistors pull no lower than V tp Jan 2015 CMOS Transistor 6

7 Pass Transistor CKTs As the source can rise to within a threshold voltage of the gate, the output of several transistors in series is no more degraded than that of a single transistor. Jan 2015 CMOS Transistor 7

8 Transmission Gates q Single pass transistors produce degraded outputs q Complementary Transmission gates pass both 0 and 1 well Jan 2015 CMOS Transistor 8

9 Transmission gate ON resistance as input voltage sweeps from 0 to 1(VSS to VDD), assuming that output follows closely. Jan 2015 CMOS Transistor 9

10 Tristates q Tristate buffer produces Z when not enabled EN A Y 0 0 Z 0 1 Z Jan 2015 CMOS Transistor 10

11 Nonrestoring Tristate q Transmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to Y Jan 2015 CMOS Transistor 11

12 Tristate Inverter q Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output Jan 2015 CMOS Transistor 12

13 Multiplexers q 2:1 multiplexer chooses between two inputs S D1 D0 Y 0 X X X X 1 Jan 2015 CMOS Transistor 13

14 Gate-Level Mux Design q q How many transistors are needed? 20 Jan 2015 CMOS Transistor 14

15 Transmission Gate Mux q Nonrestoring mux uses two transmission gates Only 4 transistors Jan 2015 CMOS Transistor 15

16 Inverting Mux q Inverting multiplexer Use compound AOI22 Or pair of tristate inverters Essentially the same thing q Noninverting multiplexer adds an inverter Jan 2015 CMOS Transistor 16

17 4:1 Multiplexer q 4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes Or four tristates Jan 2015 CMOS Transistor 17

18 Sizing for Performance NMOS and PMOS diffusion + diffusion-gate overlap. Fan-out (input gates) + interconnects. Equivalent gate resistance. Capacitive load of an inverter. S sizing factor. Propagation delay: Inverter delay loaded only by intrinsic. Jan 2015 CMOS Transistor 18

19 Intrinsic cap to gate cap ratio 1. Effective fan-out. The delay of an inverter is only a function of the ratio between its external load cap to its input cap In Out 1 2 N Jan 2015 CMOS Transistor 19

20 imply It implies that same sizing factor f is used for all stages. The optimal size of an inverter is the geometric mean of its neighbor drives Given and, and the optimal sizing factor is The minimum delay through the chain is Jan 2015 CMOS Transistor 20

21 What should be the optimal N? The derivative by N of yields or equivalently having a closed form solution only for γ=0, a case where the intrinsic self load is ignored and only the fan-out is considered. Jan 2015 CMOS Transistor 21