Solution HW4 Dr. Parker EE477

Transcription

1 Solution HW4 Dr. Parker EE477 Assume for the problems below that V dd = 1.8 v, V tp0 is -.7 v. and V tn0 is.7 V. V tpbodyeffect is -.9 v. and V tnbodyeffect is.9 V. Assume ß n (k n )= W/L µ A(microamps)/V 2 and ß p (k p )= 51 W/L µ A/V 2 1.a (10%) Sketch the voltage input/output transfer curve of an inverter for the case at which kn=kp. Label the 5 segments A, B, C, D, and E, the negative slopes of -1, VIL and VIH, and the input voltage at point C on the curve. 1.b (5%) What are the regions of operation of the transistors on each segment? This is answered in the above sketch.

2 2.a (2.5%) Which transistor changes its region of operation when the inverter moves from segment B to C. PMOS moves from linear to saturation 2.b (2.5%) Which transistor changes its region of operation when the inverter moves from segment C to D. NMOS moves from saturation to linear 3.a (2.5%) If Kn>Kp which transistor stays ON over more of the input/output transfer curve? the NMOS transistor stays active for a wider range of input voltages as the C region moves to the left. 3.b (5%) Is NML greater/less than or equal to NMH? Assume VOH = Vdd and VOL= 0V. NML is defined as VIL-VOL and since VOL=0, the NML=VIL. Because the transfer curve moves to the left when kn>kp, VIL decreases and so that decreases NML. In contrast, NMH is defined as VOH-VIH. Beacause VOH=Vdd, NMH=Vdd-VIH. VIH moves to a lower input voltage when kn>kp because the transfer curve moves to the left, so NMH increases. We can thus conclude that NML<NMH when Kn>kp. 3.c (5%) For Kn>Kp, if we connect the output of an inverter to the input of another inverter through a long wire that introduces noise, what should the range of input voltages at the input of the second inverter be to guarantee the output of the second inverter has a valid logic 1? To have a valid logic output of 1 at the output of the second inverter we need to guarantee that the voltage that arrives to the input of the second inverter is less than VIL. 4. (2.5%) What does it mean to have a noise margin NML of.2 in terms of the amount of noise that can be added to the signal and still have correct results? A NML=.2 means that the difference between VIL and VOL is.2 and thus as long as the noise added to VOL is less than.2 V we can guarantee to have a valid output of logic 1. 5.a (5%) Why do we typically want the inverter to be sized so that we can meet the condition kn=kp? We want to guarantee noise immunity, so we can maximize NML and NMH.

3 Vgsn 5.b (5%) If we want to have a fast inverter, is it a good idea to have a wider range of inputs between VIL and VIH? If not, explain in terms of VIL and VIH how can we have a faster inverter. No, it is not a good idea to increase the range of inputs between VIL and VIH. This would not allow the inverter to switch from either high to low or low to high at maximum speed, as the inverter needs to perform more computations during the transition before it finally reaches its steady state voltage. 6. (10%) Sketch Vgsn (Y-axis) as a function of kn/kp (x-axis) for the given formula in lecture notes for the C region. At least 3 points should be recorded, one for the condition Kn=Kp, Kp>Kn, and Kp<Kn. Vgsn =.92 Kp/Kn =.22^2/.18^2= 1.49 kp > Kn Kn/Kp =.669 Vgsn = Vdd/2 =.9 Kn=kp = 1 Vgsn =.88 Kp/Kn =.18^2/.22^2 ~=.669 kp < Kn Kn/Kp = 1.49 kn/kp Vgsn kn/kp

4 7. (5%) Do we have any current flow through either pmos and/or nmos transistor(s) in region A and E? Is this current comparable in magnitude with the current in region C? If Vin is near to 0.0 V, the current flow is negligible because the NMOS would be considered to be OFF. As we increase Vin reaching near Vtn0, then there would be some small current flow (subthreshold current) because the NMOS is not completely OFF. Similarly, when Vin is near to 1.8 V, the current flow is negligible because the PMOS would be considered to be OFF. As we decrease Vin below 1.8 and approach to 1.8+Vtp0 then there would be some small current flow (subthreshold current) because the PMOS is not completely OFF. The current in region A and E are not comparable in magnitude with the current in region C where both transistors are in saturation and a current spike is generated. 8. (10%) Assume an inverter is on segment D of the input/output transfer curve. What is the range of V in that would allow the inverter to remain in segment D? In segment D, NMOS is in linear region and PMOS in Saturation. To remain in this segment we need to guarantee this condition for the range of input voltages. By inspection from the voltage transfer curve we know that if the inverter moves from D to C the only transistor that change its operation is the NMOS (from LINEAR SAT). We can prevent this by Vds< Vgsn Vtn0 Vgsn>Vdsn+Vtn0 Vin> Vdsn+Vtn0 Similarly, by inspection from the voltage transfer curve we know that if the inverter moves from D to E region the only transistor that changes its operation is the PMOS transistor (from SAT Cut off). We can prevent this by Vgsp Vtp0 Vgsp = Vgsn Vdd Vgsn Vdd Vtp0 Vgsn Vdd +Vtp0 Thus, both conditions are satisfied for input voltages in the range of Vdsn+Vtn0 < Vin Vdd + Vtp0

5 9. (10 %) An inverter has the transistors sized so that as the output falls from V dd to G nd., a current spike occurs at V in =.75v. What does that tell us about the ratio kp/kn? Vdd/2 = 1.8/2 =.9 We have current spike when both transistor are in saturation and that occurs in region C. The spike ocurrs before Vdd/2 because Vin <.9. The voltage transfer curve moves to the left and Kp/Kn < (10%) An inverter has the transistors sized so that the ratio of k p to k n = 1.2. Does this ratio imply that the transistor switches from high to low with a larger or smaller input voltage? What regions are the transistors in when Vin is equal to Vdd/2? It switches from high to low with a larger input voltage because Kp > Kn. Since Kp > Kn, region C happens with a voltage greater than Vdd/2, so the inverter is not in region C. It is not in region A because Vin > Vtn0, therefore the inverter is in region B. NMOS is in SAT and PMOS in LINEAR. 11. (10 %) If an inverter is on segment B of the input/output transfer curve, V out = 1.7v and V in =.8v, prove that the PMOS transistor is in the linear region. Vgsp Vtp Vgsp = Vgsn Vdd = = - 1 V -1 V Vtp -1 V -.7 (This is true, PMOS ON) Vdsp> Vgsp Vtp0 (condition for PMOS LINEAR) Vdsp = Vout Vdd = = -.1 V Vgsp = -1 V -.1 > -1 - (-.7) -.1 > > -.3 (This is true, PMOS LINEAR)